EP0163177A2 - Einrichtung zum Generieren von Bildfensterseitenlinien für eine Kathodenstrahlanzeigeeinrichtung - Google Patents

Einrichtung zum Generieren von Bildfensterseitenlinien für eine Kathodenstrahlanzeigeeinrichtung Download PDF

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Publication number
EP0163177A2
EP0163177A2 EP85105721A EP85105721A EP0163177A2 EP 0163177 A2 EP0163177 A2 EP 0163177A2 EP 85105721 A EP85105721 A EP 85105721A EP 85105721 A EP85105721 A EP 85105721A EP 0163177 A2 EP0163177 A2 EP 0163177A2
Authority
EP
European Patent Office
Prior art keywords
window
signal
gate
horizontal
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85105721A
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English (en)
French (fr)
Other versions
EP0163177A3 (en
EP0163177B1 (de
Inventor
Yuji Harifu Apart. B-208 Gohda
Shinpei Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0163177A2 publication Critical patent/EP0163177A2/de
Publication of EP0163177A3 publication Critical patent/EP0163177A3/en
Application granted granted Critical
Publication of EP0163177B1 publication Critical patent/EP0163177B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/143—Circuits for displaying horizontal and vertical lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports

Definitions

  • the present invention relates to a cathode ray tube (hereinafter called CRT) display, and more particularly to a circuit for generating boderlines of a window.
  • CTR cathode ray tube
  • the borderlines of a window in a CRT display is displayed by storing dots at locations corresponding to the borderlines in an image memory.
  • this involves the problem that the capacity of the memory has to be made large.
  • the object of the present invention is to provide a circuit for generating window borderlines for a CRT display that is capable of generating borderlines of a window with a simple hardware configuration.
  • said object is advantageously solved in that a window region defining signal is generated which takes first state for a period corresponding to a desired window region, and second state for a period not corresponding to the window region during scanning period of the screen of CRT display; then this signal is delayed, and this delayed signal and said window region defining'signal are exclusive-ORed and used as a timing signal to generate borderlines of the window.
  • the invention provides the advantage that with a simple hardware configuration borderlines of a window can be generated and displayed on the screen of a CRT in the width of a character box or a dot.
  • Figs. 1 and 2 show the preferred embodiment of the circuit for generating the window borderlines for the CRT display according to the invention.
  • This circuit generates horizontal borderlines 102 and 104 of a window 4 on a CRT display screen 2, as well as vertical borderlines 106 and 108, as for example shown in Fig. 3.
  • a horizontal counter 10 counts the number of characters for one line on the screen in response to a character clock signal, and indicates a horizontal location of a scanning line.
  • a window region horizontal start point register 12 stores a signal indicating a horizontal start point XS (see Fig. 3) of the window 4. This signal is, for example, supplied from a microprocessor.
  • a comparator 16 compares the count of the horizontal counter 10 and the content of the window region horizontal start point register 12, and supplies a high level signal to a set terminal S of latch 20 when both are coincident.
  • a window region horizontal end point register 14 stores a signal indicating a horizontal end point XE (see Fig. 3) of the window 4. This signal is also, for example, supplied from a microprocessor.
  • a comparator 18 compares the count of the horizontal counter 10 and the content of the window region horizontal end point register 14, and supplies a high level signal to a reset terminal R of the latch 20 when both are coincident.
  • the latch 20 starts to generate a high level signal when the set terminal S is supplied with the high level signal, and stops to generate the high level signal when the reset terminal R is supplied with the high level signal.
  • a delay circuit 22 delays an output signal of the latch 20 by a period of one character cycle.
  • An exclusive OR gate 24 exclusive-ORs the output signal of the latch 20 and the output signal of the delay circuit 22.
  • a vertical counter 30 increments its count each time when it receives a horizontal synchronizing signal, and indicates a vertical location of a scanning line.
  • a window region vertical start point register 32 stores a signal indicating a vertical start point YS (see Fig. 3) of the window 4. This signal is, for example, supplied from a microprocessor.
  • a comparator 36 compares the count of the vertical counter 30 and the content of the window region start point register 32, and supplies a high level signal to a set terminal S of latch 40 when both are coincident.
  • a window region vertical end point register 34 stores a signal indicating a vertical end point YE (see Fig. 3) of the window 4. This signal is also, for example, supplied from a microprocessor.
  • a comparator 38 compares the count of the vertical counter 30 and the content of the window region vertical end point register 34, and supplies a high level signal to a reset terminal R of the latch 40 when both are coincident.
  • the latch 40 starts to generate a high level signal when its set terminal S is supplied with the high level signal, and stops to generate the high level signal when its reset terminal R is supplied with the high level signal.
  • a delay circuit 42 delays an output signal of the latch 40 by one horizontal scanning period.
  • An exclusive OR gate 44 exclusive-ORs the output signal of the latch 40 and an output signal of the delay circuit 42.
  • An AND gate 26 outputs a signal ANDing an output of the exclusive OR gate 24 and the output of the latch 40, while an AND gate 46 outputs a signal ANDing an output of the exclusive OR gate 44 and the output of the latch 20.
  • Fig. 4 shows waveforms at various points in the circuit of Fig. 1. Now referring to Fig. 4, operation of the circuit in Fig. 1 is described.
  • the latch 20 generates the high level signal from the time when the output signal of the horizontal counter 10 is coincident with the window horizontal start point XS stored in the register 12, to the time when it is coincident with the window horizontal end point XE stored on the register 14. Therefore, the latch 20 generates a signal defining a horizontal region of the window (see Fig: 4(A)). Because the delay circuit 22 delays the output signal of the latch 20 by a period of one character cycle, the exclusive OR gate 24 generates high level signals from each of the horizontal start point XS and the end point XE of the window for a duration of one character cycle.
  • the latch 40 generates a high level signal from the time when the output signal of the vertical counter 30 is coincident with the window vertical start point YS stored in the register 32, to the time when it is coincident with the window vertical end point YE stored in the register 34. Therefore, the latch 40 generates a signal specifying a vertical region of the window (see Fig. 4(D)). Because the delay circuit 42 delays the output signal of the latch 40 by one horizontal scanning period, the exclusive OR gate 44 generates high level signals from each of the vertical start point YS and the end point YE of the window for a duration of one horizontal scanning period.
  • the AND gate 26 selects only those pulses included in the vertical region of the window from pulses of one character cycle from the horizontal start point XS and the end point XE that are generated for any of horizontal scanning period, by ANDing the output signal of the exclusive OR gate 24 and the signal defining the vertical region of the window generated from the latch 40.
  • output pulses 206 and 208 of the AND gate 26 correspond to vertical lines 106 and 108 of the window 4 (see Fig. 3), respectively.
  • the AND gate 46 takes out only portions included in the horizontal region of the window from a pulse covering entirely one horizontal scanning interval by ANDing the output of the exclusive OR gate 44 and the signal defining the horizontal region of the window generated from the latch 20.
  • output pulses 202 and 204 of the AND gate 46 correspond to horizontal lines 102 and 104 of the window 4 (see Fig. 3), respectively.
  • a command register 50 stores a horizontal dot location in a character requiring generation of a borderline, and, for example, stores the fourth dot location (any dot location can be stored and not restricted to this example).
  • a dot counter 52 counts the number of dots to the horizontal dot location in response to a dot clock.
  • a comparator 54 generates a high level signal when the content of the command register 50 is coincident with the count of the counter 52.
  • An AND gate 56 ANDs the output signal of the AND gate 26 of Fig. 1 and the output signal of the comparator 54.
  • a NOT circuit 60 reverses the output of the AND gate 46.
  • a latch 64 generates a high level signal from the time when a high level signal is supplied to a set terminal S from the AND gate 58, to the time when a high level signal is supplied to a reset terminal R from the AND gate 62.
  • An OR gate 70 ORs the output signal of the AND gate 56 and the output signal of the latch 64.
  • Fig. 5 shows waveforms at various parts of the circuit shown in Fig. 2. Now referring to Fig. 5, operation of the circuit of Fig. 2 is described. Now it is assumed that the fourth dot location in the horizontal direction of a character is stored in the command register 50. The comparator 54 generates a high level signal at locations corresponding to the fourth dot location in horizontal direction of the character for the entire scanning interval (see Fig. 5(P)). Therefore, the AND gate 56 can extract pulses corresponding to the fourth dot location (see Fig. 5(R)) from the pulses 206 and 208 with one character width. Thus, the AND gate 56 thins the vertical line with one character width to that with one dot width.
  • the AND gate 58 generates a pulse at a time delayed by four bits from the start point of the output pulse 202 of the AND gate 46, while the AND gate 62 generates a pulse at a time delayed for four bits from the end point of the output pulse 202 of the AND gate 46. Therefore, the latch 64 generates a pulse 302 of which start and end points are delayed by a time for four bits from the start and the end points of the pulse 202, respectively (see Fig. 5(W)). Thus, the latch 64 aligns the start and the end points of a horizontal line with the location of the vertical lines.
  • An OR gate 70 combines the output signal of the AND gate 56 that defines driving duration for the CRT for displaying the vertical lines 106 and 108 with the output signal of the latch 64 that defines driving duration for the CRT for displaying the horizontal lines 102 and 104, and supplies it to the CRT. Therefore, the borderlines of a window can be displayed by causing the CRT to be luminous only when the output signal of the OR gate 70 is at high level.
  • this invention allows to display the borderlines of a window on the CRT display with a simple hardware configuration.
EP85105721A 1984-05-22 1985-05-10 Einrichtung zum Generieren von Bildfensterseitenlinien für eine Kathodenstrahlanzeigeeinrichtung Expired - Lifetime EP0163177B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP101885/84 1984-05-22
JP59101885A JPS60250389A (ja) 1984-05-22 1984-05-22 陰極線管表示装置の窓境界線発生回路

Publications (3)

Publication Number Publication Date
EP0163177A2 true EP0163177A2 (de) 1985-12-04
EP0163177A3 EP0163177A3 (en) 1989-11-15
EP0163177B1 EP0163177B1 (de) 1992-12-30

Family

ID=14312387

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85105721A Expired - Lifetime EP0163177B1 (de) 1984-05-22 1985-05-10 Einrichtung zum Generieren von Bildfensterseitenlinien für eine Kathodenstrahlanzeigeeinrichtung

Country Status (6)

Country Link
EP (1) EP0163177B1 (de)
JP (1) JPS60250389A (de)
KR (1) KR890003034B1 (de)
CA (1) CA1236601A (de)
DE (1) DE3586928T2 (de)
IN (1) IN165132B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104447597A (zh) * 2014-10-26 2015-03-25 威海普瑞森医药技术开发有限公司 一种地克珠利的制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3027272A1 (de) * 1980-07-18 1982-02-11 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur erzeugung einer umrandung
DE3305710A1 (de) * 1982-02-18 1983-08-25 Fuji Electric Co., Ltd., Kawasaki, Kanagawa Schaltungsanordnung zur merkmalsgewinnung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158372A (en) * 1980-05-10 1981-12-07 Nippon Electric Co Cursor circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3027272A1 (de) * 1980-07-18 1982-02-11 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur erzeugung einer umrandung
DE3305710A1 (de) * 1982-02-18 1983-08-25 Fuji Electric Co., Ltd., Kawasaki, Kanagawa Schaltungsanordnung zur merkmalsgewinnung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104447597A (zh) * 2014-10-26 2015-03-25 威海普瑞森医药技术开发有限公司 一种地克珠利的制备方法

Also Published As

Publication number Publication date
CA1236601A (en) 1988-05-10
KR890003034B1 (ko) 1989-08-19
EP0163177A3 (en) 1989-11-15
JPS60250389A (ja) 1985-12-11
DE3586928T2 (de) 1993-07-15
DE3586928D1 (de) 1993-02-11
IN165132B (de) 1989-08-19
EP0163177B1 (de) 1992-12-30
JPH0576038B2 (de) 1993-10-21
KR850008013A (ko) 1985-12-11

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