EP0161966A1 - Verfahren und Einrichtung zur Codeumwandlung von Farben, die Verbindung zwischen zwei Geräten mit verschiedener Farbdefinition ermöglichend - Google Patents

Verfahren und Einrichtung zur Codeumwandlung von Farben, die Verbindung zwischen zwei Geräten mit verschiedener Farbdefinition ermöglichend Download PDF

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Publication number
EP0161966A1
EP0161966A1 EP85400754A EP85400754A EP0161966A1 EP 0161966 A1 EP0161966 A1 EP 0161966A1 EP 85400754 A EP85400754 A EP 85400754A EP 85400754 A EP85400754 A EP 85400754A EP 0161966 A1 EP0161966 A1 EP 0161966A1
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EP
European Patent Office
Prior art keywords
color
character
word
output
words
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Granted
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EP85400754A
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English (en)
French (fr)
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EP0161966B1 (de
Inventor
Françoise Coutrot
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Public De Diffusion Dit Telediffu Ets
Ministere des PTT
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Telediffusion de France ets Public de Diffusion
Etat Francais
Centre National dEtudes des Telecommunications CNET
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Priority to AT85400754T priority Critical patent/ATE37455T1/de
Publication of EP0161966A1 publication Critical patent/EP0161966A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed

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  • the subject of the present invention is a method for transcoding colors and a corresponding transcoder.
  • the field of application of the invention is vast. It covers in particular videography which is, as we know, a telecommunication method making it possible to present albhanumeric or graphic messages to a user on a display screen. In its broadcast variant, this process is often designated by "teletext" and in its interactive variant by "videotex".
  • the invention can also be applied to the field of computers or microcomputers, as well as to that of printers, and various display devices such as flat screens.
  • the problem which the invention proposes to solve is a problem of incompatibility between equipment working with a different number of colors. This is the case, for example, when we want display an eight-color videography image on a two-color flat screen, or when you want to couple a high-definition microcomputer using 64 colors to an 8-color printer, etc.
  • FIG. 1 illustrates the place occupied by the transcoder of the invention in known installations with two incompatible devices.
  • the transcoder TR is located between an EQE input device and an EQS output device.
  • Figure 2 shows how this same transcoder fits into a videography chain which includes a central processing unit UCT, a page memory MP, a UV display unit and a television receiver RT. The transcoder is then inserted between the page memory MP and the UV display unit and it allows the control of an EOS output device.
  • the images to be processed are images of the mosaic type.
  • images are made up of characters, each character being included in a matrix.
  • the mosaic image consists of a grid (row, column) of such matrices, these being arranged contiguously both horizontally and vertically.
  • the characters are either alphanumeric or graphic.
  • Figure 3 shows an alphanumeric character (in this case the letter A).
  • Such a character is defined by a form F, by the color of the character, ie Cc, (this color being shown diagrammatically by inclined stripes) and by the background color, ie Cf (diagrammed by dotted lines).
  • Certain other attributes of the character D can be added to the two preceding ones (such as for example the flashing, the height, the width etc ).
  • examples will be described later, with reference to FIGS. 9a and 9b.
  • the background color is necessarily that of the medium used (paper in the first case and screen in the second) and the Character color must be that of the ribbon ink (for the printer) or that of the excited material (for the screen). If the screen is liquid crystal, the background of the screen is usually bright and the character is dark. With a CRT screen, the background is usually dark and the character bright.
  • the principle of the invention is first of all to establish a correspondence table between the N colors of the input equipment and the M colors of the output equipment. If we denote by K0, Kl, ..., KN-2, KN-1 the N colors of the input equipment, we can arrange these colors in a certain order. As, in practice, the color information is coded by binary words, this amounts to arranging such words.
  • Figure 4 on its left side, shows the N colors in question as horizontal lines.
  • the number of binary elements, or bits, of the words translating the colors is then equal to n (3 in the previous example). But the invention is not limited to this one case, of course.
  • the numerical code chosen is not necessarily the color code used for display on a screen of the color television type, such as the RT screen in FIG. 2.
  • the correspondence table to be established must allow each of the N colors K0, Kl, ..., KN-1 to be associated with one of the M colors C0, Cl, ..., CM-2, CM-1 of the output equipment. It is therefore necessary to establish, in the same way, a second color scale with these M colors. Since M is, hypothetically, less than N, the two scales do not coincide. This second scale is represented in the middle part of FIG. 4.
  • each color C can be associated with a word of m bits.
  • the number m is less than n.
  • the extreme colors C0 and CM-1 are black and white, so it makes sense to match KO to C0 and KN-1 to CM-1.
  • the transcoding between a color K and a color C therefore only really arises for the intermediate colors.
  • the transcoding operation will consist of processing on the binary words associated with each of the colors of the two families. As these words do not have the same number of bits (the N colors are associated with words of n bits and the M colors with words of m bits), these are first completed by n-m least significant bits.
  • Co which includes m bits equal to zero
  • the word will be completed with n-m other bits equal to 0 to obtain a word identical to that which characterizes K0.
  • To the input Ko color we will therefore immediately match the output Co color.
  • CM-1 which includes m times bit 1
  • the word will be completed with n-m least significant bits equal to 1, which will give an n-bit word identical to that of KN-1.
  • the words of m bits will be supplemented by bits equal to 0 or 1, depending on the colors in question, while endeavoring to make the intermediate colors common to the two systems coincide.
  • a character to be displayed is defined by a character color Cc, taken from among the N colors K0, ..., KN-1 and a background color Cf, taken from the same colors.
  • the color Cc can moreover be identical to the color Cf, in which case it is a question of displaying a uniform space.
  • the problem amounts to attributing to Cc and Cf two colors taken from the m colors C0, ..., CM-1.
  • Cc does not coincide with one of these colors, but falls between two colors, which one denote Ci and Ci + 1 respectively, the index i being a number between 0 and M-2.
  • Cf does not necessarily coincide with one of the colors of the output equipment, but falls between two colors Cj and Cj + 1, the index j also being a number between 0 and M-2.
  • i and j can be equal.
  • the invention makes it possible to choose between the colors Ci and Ci + 1 for the character color Cc and between Cj and Cj + 1 for the background color.
  • the present invention also relates to a transcoder which implements the method which has just been defined.
  • the transcoder generally comprises:
  • FIG. 7a shows a subset 300 comprising M comparators 301, etc ... 30M with two inputs, one receiving the word Cc coming from the input register 102, the other one of the M words C0,. .., CM-1 representing the output colors.
  • These comparators work on n bits and they have an output which indicates whether the word received on one of the inputs is or is not less than the word received on the other.
  • the sub-assembly 300 also comprises a multiplexer 310 with M inputs connected to the preceding comparators and with m outputs; these m outputs, by their binary state, give the rank i of the color Ci for which Ci is less than Cc and for which Ci + 1 is greater than Cc.
  • i is the rank of the last comparator 301, ..., 30M indicating that the color Ci is less than Cc.
  • the sub-assembly 300 also comprises an adder 311 with n bits, adding 1 to the number i it receives and therefore delivering the number i + 1.
  • the subset 300 gives the information relating to the interval i / i + 1 in which the character color Cc is situated.
  • Two read only memories 1001 and 1002 containing the words C0, ..., CM + 1 are addressed respectively by i and i + l. They therefore deliver the words Ci and Ci + 1 limiting the interval in which Cc is found.
  • the set of four read-only memories 1001 to 1004 constitutes the read-only memory 1000, which can also deliver the words C0, ..., CM-1 necessary for the blocks 300 and 400.
  • a first comparator 600 which includes a NON gate 606 receiving the word Ci coming from the memory 1001 and delivering the complementary word Ci, an adder 601 adding +1 to Ci and delivering Ci + l, an adder 602 with n bits receiving This +1 and Cc and delivering the sum of these two words.
  • the sub-assembly 600 also includes a NON 607 door receiving Cc and delivering CC , an adder 605 adding 1 to this number, an adder 603 receiving Cc + 1 and Ci + 1 coming from memory 1002, and delivering CC + 1 + Ci + 1; finally, block 600 includes an n-bit comparator 604, which compares Ci + l + Cc and CC + 1 + Ci + 1.
  • This comparator has an output 5 which is active (that is to say which delivers a logic 1) if Ci + l + Cc is less than CC + 1-t-Ci + 1, in other words if Cc-Ci is less than Ci + l-Cc.
  • the sub-assembly 700 shown in FIG. 7b comprises an inverter 706, an adder 701, an adder 703, an inverter 707, an adder 705, an adder 702, a com parator 704, whose output 6 is active if Cf-Cj is less than Cj + l-Cf.
  • FIG. 7c shows, on its left side, a comparator 201 having two inputs, connected respectively to the input registers 102 and 103 and receiving Cc and Cf, and three outputs, respectively 3, 1 and 4, indicating whether Cc is lower, equal to or greater than Cf.
  • FIG. 7c also shows, on its right side, a comparator 501 having two inputs connected to the multiplexers 310 and 410, from which they receive the numbers i and j, and an output 2 indicating whether these two numbers are equal.
  • the comparator 501 operates with m bits since the numbers i and j are themselves with m bits. But one could work on the words Ci and Cj, provided that the comparator 501 is connected downstream of the memories 1001 and 1004 and no longer upstream.
  • FIG. 7d represents two blocks 801 and 802 belonging to the decision logic circuit 800.
  • the first 801 comprises three inverters 897, 898, 899, two AND gates 895 and 896, an OR gate 894 whose output 8 is the general output of 801.
  • the second circuit comprises, in the same way, three inverters 890, 891, 892, two AND gates 888 and 889, and an OR gate 887 whose output 7 is the general output of circuit 802.
  • FIG. 7e shows the structure of the multiplexer 900. This consists of three multiplexers 2 ⁇ 1, the first 901, controlled by the signal coming from the output 1 of the comparator 201 and receiving the shape and space data, the second 902, controlled by the signal from output 7 of logic circuit 802, and receiving the words Ci and Ci + 1, and the third, 903, controlled by the signal from output 8 of circuit 801 and receiving the words Cj and Cj + l.
  • the word relative to the form ie RO
  • Rl relating to the colors
  • Rl is loaded in a double register 1109, 1110 for Cc and Cf.
  • These output registers are actuated by a connection 11 coming from the sequencer 1201.
  • the output of these registers is connected to the output equipment which thus receives a form of information RO and a color information R1.
  • FIG. 7f shows a detail of the sequencing circuit.
  • This circuit includes a sequencer 1201 and a counter 1202, with connections which have already been indicated in connection with FIG. 6b. We simply note an additional counter reset connection (RESET) by the sequencer.
  • RESET counter reset connection
  • FIG. 9a In the case of videotex, in addition to the alphanumeric character sets, semi-graphic games are used, the principle of which is illustrated in FIG. 9a.
  • the matrix containing the character is broken down into 6 blocks b 0 to b 5 which can each be switched on or off. This gives 64 different shapes. Each of these shapes can be matched with the complementary shape, as illustrated in the figure 9b.
  • the two shapes shown are said to be "paired". We pass from one to the other by inverting the command of the state of the paving stones.
  • alphanumeric character set As for the alphanumeric character set, it is also linked to an inversion bit.
  • This algorithm applies differently rent depending on whether the output equipment interprets the inversion bit or not.
  • the structure of the transcoder takes a simplified form compared to the general variant of FIGS. 7a to 7f.
  • the corresponding diagram is represented in FIG. 11 where the numerical references designate the same elements as for FIGS. 7a to 7f.
  • the notations ⁇ and y of the register 105 signify “alphanumeric” and “grapbic”;
  • the hlClmis notation for register 104 designates attribute codes meaning respectively "height, width, flashing, masking, overlay, underlining". These attributes will completely occupy the output register 1109 (content R1). In this particular case, there is more strictly speaking no color word to select.
  • the above variant corresponds to the case where reversal is possible in the output equipment.
  • the invention can be applied in the case where this equipment does not accept inversion.
  • the decision algorithm should then be slightly modified to simulate this inversion by acting on the shape of the displayed character.
  • the output register 1109 loading Rl will no longer contain the information I, and the loading register RO will contain either F or F.
  • the multiplexer 901 receives not only the form F but also the inverted form F, and not only the space but also the solid block.
  • the multiplexer 901 therefore changes from a type 2-1 to a type 4 ⁇ 1.
  • a second variant of the transcoder of the invention relates to the 16-bit parallel and serial videotex, with 8 colors for the input equipment, the output equipment being a printer or a flat screen in two colors. , not having the inversion bit. This is the most complex case.
  • FIGS. 14a to 14f illustrate the structure of the transcoder in this particular case, with the same conventions for the numerical references as for the preceding figures.
  • the 16 bits coming from the image memory are referenced BO to B15.
  • the colors are coded on 3 bits denoted BcVcRc for the character color and BfVfRf for the background color.
  • the different bits of the color words are conveyed by connections bearing the references 13, 14, 15 for BfVfRf and 16, 17, 18 for BcVcRc for a given character and, respectively, 22, 23, 24 and 25, 26, 27 for the next character.
  • the connection 12 conveys a signal concerning the presence of delimiters.
  • the input register comprises two additional registers 106 and 107 intended to receive the 16 bits (D'0, ..., D'7 and D'8, ..., D ' 15) of the character of rank n + l, when the character of rank n is loaded in the registers 102, 103, 105.
  • Form F is coded on 7 bits (D0-D6); which are compared with the 7 bits XO-X6 of space in comparator 1402 whose output is referenced 21. Similarly for the 8 bits of space X8 to X15 which are compared to the 8 character bits from 102, 103 , 104 in the comparator 14 0 3 whose output is referenced 20.
  • FIG. 14c shows an embodiment for a first logic decision circuit 801.
  • This circuit comprises: two inverters 820, 821 connected to an OR gate 822; an inverter 823; AND gates 824 and 825; an inverter 826; a NAND gate 827; two inverters 829, 830; five doors AND 831, 832, 833, 834, 835 and finally one door OR 836 whose output 31 constitutes the output of circuit 801.
  • the function of this circuit 801 is to select a code corresponding to a graphic space.
  • Figure 14d shows 3 other logic circuits.
  • the first, referenced 803 comprises an inverter 840, two ET gates 841, 842, an inverter 843; an AND gate 844; two doors OR 845, 846; two AND gates 847, 848 and finally an OR gate 850 whose output 32 constitutes the general output of circuit 803.
  • This circuit fulfills the function of selecting a full graphic block.
  • the circuit 803 ′ comprises two AND gates 861, 862 and an OR gate 863 of output 33. This circuit has the function of selecting, for R0, bits D7-DO of form.
  • circuit 803 "consists of a single AND output gate 864 34.
  • the input marked 45 of this door corresponds to the output of door 824 of the circuit 801.
  • the circuit 803" is used to select the bit D7 and the additional bits D6-DO for R0.
  • Circuit 805 includes: an OR gate 865; an AND 866 gate; a locking circuit 867 with three outputs 46, 47 and 48.
  • the circuit 805 has the function of locking the background color when a delimiter or a graphic character is present.
  • the circuit 806 includes a 2- + 3 type demultiplexer, the three outputs of which are referenced 50, 51, 52.
  • the function of this circuit 806 is the separation between delimiter, graphic character, alphanumeric character.
  • circuit 804 includes an OR gate 869; an AND 870 gate; a flip-flop 871; an inverter 872; an OR 873 door. Its output is 53 and 54. Furthermore, this circuit 804 also includes an inverter 874 and an AND gate 875 for output 58.
  • Figure 14f shows the output elements of the transcoder.
  • the multiplexer 901 receives data in the form of bits E7-EO representing the graphic space code, of bits B7-BO representing the solid block code, of bits D7-DO representing the form, of bits D7 D6-DO representing the inverted form.
  • This multiplexer 901 is controlled by the bits conveyed by the connections 31, 32, 33, 34 from the logic decision circuits 801, 803, 803 'and 803 "of FIGS. 14c and l4d, bits which are multiplexed beforehand in a multiplexer 906 of type 4 ⁇ 2, and whose outputs are referenced 29 and 30.
  • the elements represented in FIG. 14f also comprise a gate 907 receiving on the one hand the bits D14-D11 and on the other hand the attribute bits I, h, 1 by the connections 13, 14 and 15 as well as the bit flashing Cl; this door 907 is controlled by a connection 35.
  • the circuit shown comprises a door 908 receiving the data D6-D4 and controlled by a connection 36.
  • These two registers respectively deliver bits C7-CO characterizing the form and bits A6-AO characterizing the attributes of the character.
  • the timing diagram of FIG. 15 explains the operation of this variant of the transcoder. It is more complex than the previous one (see Figure 8) even if there are essentially the same phases. However, it includes an operation for loading the additional input registers 106, 107 relating to the next character. It is phase 02 which is weighed down, because it takes a double memory addressing to acquire the next character (case of the delimiter).
  • the sequencing is then as follows: sending a first read signal RD to the page memory to acquire the character to be transcoded; this signal is followed by a signal for loading the input registers 101 to 105 (3rd line); the address counter 1202 has an up / down counting input (U / D) which is positioned for up counting; the sequencer sends a signal CK, which increments the address and a signal C L K which locks the background color (case of the delimiter and the graphic).
  • An RD signal is then sent to acquire the next character; the latter is followed by a signal for loading the input registers 106 and 107 and counting down the input of the counter; then the sequencer sends a new CK signal to return to the initial address and then puts the U / D input back into counting and sends the "valid character" signal.

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  • Engineering & Computer Science (AREA)
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  • Inspection Of Paper Currency And Valuable Securities (AREA)
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  • Liquid Developers In Electrophotography (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
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  • Spectrometry And Color Measurement (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Structure Of Telephone Exchanges (AREA)
  • Optical Communication System (AREA)
  • Supplying Of Containers To The Packaging Station (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Color Image Communication Systems (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Processing And Handling Of Plastics And Other Materials For Molding In General (AREA)
  • Computer And Data Communications (AREA)
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  • Error Detection And Correction (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
EP85400754A 1984-04-20 1985-04-16 Verfahren und Einrichtung zur Codeumwandlung von Farben, die Verbindung zwischen zwei Geräten mit verschiedener Farbdefinition ermöglichend Expired EP0161966B1 (de)

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AT85400754T ATE37455T1 (de) 1984-04-20 1985-04-16 Verfahren und einrichtung zur codeumwandlung von farben, die verbindung zwischen zwei geraeten mit verschiedener farbdefinition ermoeglichend.

Applications Claiming Priority (2)

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FR8406304A FR2563400B1 (fr) 1984-04-20 1984-04-20 Procede de transcodage de couleurs permettant l'interconnexion de deux equipements de definition de couleurs differente et transcodeur correspondant
FR8406304 1984-04-20

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EP0161966A1 true EP0161966A1 (de) 1985-11-21
EP0161966B1 EP0161966B1 (de) 1988-09-21

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US (1) US4763283A (de)
EP (1) EP0161966B1 (de)
JP (1) JPS61502146A (de)
AT (1) ATE37455T1 (de)
AU (1) AU583266B2 (de)
BR (1) BR8506618A (de)
CA (1) CA1239481A (de)
DE (1) DE3565186D1 (de)
DK (1) DK594985D0 (de)
ES (1) ES8701446A1 (de)
FR (1) FR2563400B1 (de)
MX (1) MX162453A (de)
NO (1) NO167775C (de)
PT (1) PT80321B (de)
WO (1) WO1985004977A1 (de)

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Cited By (2)

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EP0358918A3 (de) * 1988-09-16 1990-06-27 Hitachi, Ltd. Anzeigensystem

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CA1239481A (fr) 1988-07-19
AU583266B2 (en) 1989-04-27
PT80321A (fr) 1985-05-01
DK594985A (da) 1985-12-19
BR8506618A (pt) 1986-04-15
DE3565186D1 (en) 1988-10-27
FR2563400B1 (fr) 1986-06-20
JPS61502146A (ja) 1986-09-25
ES542420A0 (es) 1986-11-16
WO1985004977A1 (fr) 1985-11-07
PT80321B (fr) 1986-10-20
DK594985D0 (da) 1985-12-19
ATE37455T1 (de) 1988-10-15
NO167775B (no) 1991-08-26
FR2563400A1 (fr) 1985-10-25
EP0161966B1 (de) 1988-09-21
AU4233485A (en) 1985-11-15
MX162453A (es) 1991-05-10
ES8701446A1 (es) 1986-11-16
NO167775C (no) 1991-12-04
NO855191L (no) 1985-12-20
US4763283A (en) 1988-08-09

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