EP0143279B1 - Uhr mit analogischer und numerischer Anzeige - Google Patents

Uhr mit analogischer und numerischer Anzeige Download PDF

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Publication number
EP0143279B1
EP0143279B1 EP84111882A EP84111882A EP0143279B1 EP 0143279 B1 EP0143279 B1 EP 0143279B1 EP 84111882 A EP84111882 A EP 84111882A EP 84111882 A EP84111882 A EP 84111882A EP 0143279 B1 EP0143279 B1 EP 0143279B1
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EP
European Patent Office
Prior art keywords
signal
circuit
input
output
logic level
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EP84111882A
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English (en)
French (fr)
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EP0143279A1 (de
Inventor
René Besson
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ETA Manufacture Horlogere Suisse SA
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ETA Manufacture Horlogere Suisse SA
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Publication of EP0143279A1 publication Critical patent/EP0143279A1/de
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C9/00—Electrically-actuated devices for setting the time-indicating means
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/0082—Visual time or date indication means by building-up characters using a combination of indicating elements and by selecting desired characters out of a number of characters or by selecting indicating elements the positions of which represents the time, i.e. combinations of G04G9/02 and G04G9/08

Definitions

  • the present invention relates to electronic watches having an analog display and a digital display and provided with means for synchronizing the two displays when they indicate the same time information.
  • the information on the two displays is different and independent, such as the time read on the analog display and a timed time indicated by the digital display.
  • the two displays can indicate the same information or information depending on one another.
  • the day and date read on the digital display must be related to the time of the analog display so that the calendar can change state when the hands indicate midnight.
  • a function must thus make it possible to read and correct the time indicated by the hands independently of the time indicated by the digital display or vice versa. Even if this information is not explicitly used, it is necessary for the calendar function as well as, for example, for the time zone function.
  • Patent application GB-A-2,019,052 for its part, describes a watch with mixed analog-digital display provided with a crown making it possible to electronically correct, forwards and backwards, the two displays by leaps of whole minutes. This is an interesting solution because it is close to the usual well accepted command used in mechanical watches.
  • the watch described has the disadvantage of requiring, next to the crown, other control members and of lacking means making it possible to synchronize the two displays.
  • a watch comprising analog and digital displays receiving minute signals from the same time base is further described in your patent application GB-A-2 042 773.
  • a crown allows this correction mode to be selected in this watch giving three the possibility, either to modify each display separately in steps of whole minutes using a button, and therefore to synchronize it, or to set the time of the two displays simultaneously by correcting them by the same number of minutes.
  • the crown does not fulfill its usual function and, on the other hand, synchronization between the displays can only be obtained if the analog display moves by whole minutes.
  • a watch according to the invention will include at least one indicator for the current minutes and one for the current hours, these two pieces of information can also be displayed in digital form, and that synchronization can be carried out. at least for the indication of the minutes.
  • the watch will preferably be provided with a bidirectional stepping motor and counting means capable of counting and counting down in order to allow modification of the time information of the two groups in both directions.
  • FIG. 1 is shown an example of watch 1 according to the present invention.
  • This watch includes an analog display with two hands 2, a digital display 3 with four characters and a control crown 4 which can move according to two degrees of freedom.
  • One of the hands 2 on the analog display indicates the hours and the other the timers.
  • the minute hand advances by fraction of a minute. To simplify the description, we will assume that it jumps every 30 seconds, the generalization to other cases being obvious.
  • the time setting of the analog display 2 is done electronically by the crown 4, forwards or backwards, thanks to the use of a motor which can rotate in both directions.
  • the digital display 3 indicates, in the example given, either the day and the date, or the hours and the minutes, or else it indicates nothing by remaining white in a synchronization position, but the present invention is not limited not just these functions.
  • the two characters on the left of display 3 are provided to display the numbers and letters necessary to indicate the days of the week.
  • the two characters on the right only display numbers.
  • the selection of the operating modes of the watch and the corrections of the digital display 3, forwards and backwards, are also made using the crown 4.
  • the two positions and the two degrees of freedom of the crown 4 are shown in Figure 1.
  • the reference 4 ' shows the crown in its normal or pushed axial position. A pull on the crown puts it in the pulled position 4 "Position 4" is not stable because a return spring tends to permanently return the crown to its normal position 4 '. Whatever the axial position of the crown, it can be rotated in both directions around an axis 6. The rotation corresponds to the first degree of freedom and the traction to the second degree of freedom of the crown.
  • These two degrees of freedom are represented respectively by the symbols 5 and 5 'in FIG. 1.
  • the crown 4 controls a mechanism, shown in plan in FIG. 2a and at the end, from the plane AA ′, in FIG. 2b.
  • This mechanism operates contacts for detecting movements of the crown.
  • the crown 4 fixed to one end of the axis 6.
  • This axis passes through the wall 10 of a watch case, which is connected to an electrical ground point 21.
  • On the axis 6 are wedged two insulating cams 12 and 13 of elongated shape, for example elliptical.
  • the major axes of the ellipses form an angle of about 45 ° between them.
  • At the other end of the axis 6 is a metal disc 14.
  • the cams 12, 13 and the disc 14 occupy positions 12 ', 13' and 14 'respectively.
  • contact blades, referenced 17, 18 and 19 are fixed by one of their ends to a metal plate 15, electrically connected to the ground point 21 and integral with the watch case.
  • the blades 17 and 18 can each move in a plane perpendicular to the axis 6 and the blade 19 in a plane parallel to the same axis.
  • the rotation of the elongated cams 12 and 13 by the crown 4 makes it possible to move the blades 17 and 18.
  • the cams also have a width sufficient for them to act in the same way in the pulled or pushed position of the crown.
  • the blade 19 is armed so as to come to press permanently on the disc 14, by putting it to electrical ground, and to exert on the axis 6 a restoring force tending to maintain the crown 4 in its normal or pushed position e 4 '.
  • Three conductive reference plates 22, 23 and 24 are fixed on an insulating plate 16, integral with the watch case. In the rest position, or not deformed, the contact blades 17, 18 come to touch the other ends respectively of the plates 22 and 23. A blade and the corresponding plate therefore form a contact, which will bear the reference of the blade.
  • the rotation of the cams 12 and 13, causing the blades to move, has the consequence of opening and closing the contacts 17 and 18. For a 360 ° rotation of the crown 4, each contact works twice.
  • the angular offset different from 90 ° existing between the cams 12 and 13 has the effect of introducing a phase shift in the operation of the contacts 17 and 18.
  • This phase shift is different depending on the direction of rotation of the cams, therefore of the crown 4. It thus constitutes a parameter representative of the first degree of freedom of this crown.
  • the working frequency of the contacts 17 and 18 makes it possible to measure the speed of rotation of the crown, the angle of rotation of which is determined by the number of contact closings.
  • the blade 20 On the metal plate 24 is fixed a blade 20 which can move in the same plane as the blade 19.
  • the blade 20 In the pushed position 4 ′ of the crown, the blade 20 remains free.
  • the disc 14 In the pulled-out position 4 'from the crown, the disc 14 comes into position 14'. It then drives the blades 19 and 20 respectively in positions 19 'and 20'. In this position of the crown, the disc 14 therefore touches the blade 20.
  • the assembly constitutes a contact which will be designated by the reference 20. The state of this contact therefore constitutes a parameter representative of the second degree of freedom of the crown 4.
  • the functions that a watch may indicate and the possibilities for correcting the information displayed define the operating modes of the watch.
  • the transition from one mode to another is obtained using the control elements of the watch.
  • FIG. 3 represents the different modes in which the watch taken as an example can be found.
  • the rectangles indicate the information appearing on the digital display and the circles symbolize the commands.
  • a line XX ' divides Figure 3 in two.
  • On the left part of this figure are grouped the functions F 1 , F 2 and F 3 of the watch and on the right part the corrections C 1 , C 2 , C 3 and C 4 .
  • the watch can therefore be found in seven different modes.
  • F 1 corresponds to the calendar function, the day D appearing on the two characters on the left and the date D on the two digits on the right of the digital display 3.
  • F 2 corresponds to the time function, the hours H being displayed on the left and the minutes M on the right.
  • F 3 is the synchronization function of the analog display on the digital display.
  • the digital display does not indicate any information to highlight the analog display. The passage from one function to another is done, for reasons of simplicity of the circuits, in a given order by turning the crown 4 in one direction or the other, but the order of scrolling of the functions could obviously depend on the direction of rotation of the crown.
  • the transition from a function to the corresponding correction mode is done by pulling on the crown 4 followed by a relaxation, as shown in FIG. 3.
  • This maneuver thus makes it possible to pass from the function F 1 in correction mode C 1 .
  • this mode only the two characters on the left appear indicating a day of the week.
  • a rotation of the crown allows you to change the day of the week by scrolling the days one after the other.
  • the order of day scrolling depends on the direction of rotation of the crown to allow rapid correction.
  • the transition from mode C 1 to the following correction mode C 2 is also carried out using a pull on the crown. Only the two figures on the right then appear, indicating the date which can be corrected by rotating the crown 4. Depending on the direction of rotation of the crown, the number corresponding to the date can be increased or decreased.
  • the next pull on the crown returns the watch to its starting mode F j .
  • correction mode C 3 in which the digital display 3 simultaneously indicates hours H and minutes M.
  • mode F 2 we can, for example example, synchronize the hours and minutes in synchronization mode by known means.
  • the hourly pulses are blocked in mode C 3 and the seconds counter of the watch circuit is reset to zero.
  • the rotation of the crown 4 then makes it possible to correct the hour and minute hour indication by jumps of whole minutes, simultaneously on the digital 3 and analog 2 displays, of the same value.
  • the correction corresponds to an advance or a delay of the watch.
  • the digital display 3 is at the exact time but the analog display 2 can possibly deviate from it by an integer number of minutes. In this case it is necessary to pass to the synchronization function F 3 then by a pull on the crown 4, in the correction mode C 4 . In this mode the time pulses are not blocked, but they only control the digital display 3 which continues to indicate the exact time H, M, while the hands 2 of the analog display remain stationary.
  • modes F 2 , C 3 from mode C 4 all these modes indicating the hours and minutes, it is possible, for example, to flash H and M alternately in mode C 4 by known means.
  • mode C 4 the rotation of the crown 4, in one direction or the other, has the effect of advancing or retreating the hands 2 by jumps of whole minutes, the number of jumps being proportional to the angle of rotation .
  • This maneuver allows the two displays to be synchronized or in phase by making them indicate the same time information.
  • a pull on the crown 4 then returns the watch to the mode F 3 then a rotation of the crown makes it possible to pass to the normal operating mode F j .
  • the return to the function F 1 could also take place automatically after a certain delay, for example 16 seconds, after the last intervention in any correction mode.
  • FIG. 4 The block diagram of a watch according to the invention is shown in FIG. 4.
  • the blocks drawn in solid lines in this figure represent known circuits and those drawn in dotted lines of circuits having specific functions, necessary for the present invention. These latter circuits will be described in detail later in this request. All circuits are supplied from a battery, not shown.
  • the diagram in FIG. 4 comprises an encoder circuit 30 for the movements of the crown 4.
  • a first and a second input of the circuit 30 respectively receive the signals coming from the contacts 17 and 18, represented in FIGS. 2a and 2b. These signals are used to define the direction of rotation of the crown.
  • the signal generated by the contact 20 in FIGS. 2, in response to a pull on the crown 4, is applied to a third input of the circuit 30.
  • This circuit produces, as a function of the input signals, output signals encoded CD, SC1, SC2 and ST, representative of the movements of the crown according to its two degrees of freedom.
  • the signal CD is a logic signal which is at the low logic level for one direction of rotation of the crown and at the high logic level for the other direction of rotation.
  • the signal SC1 contains a number of pulses proportional to the angle of rotation of the crown, whatever its direction of rotation.
  • the signal SC2 is obtained from the signal SC1 by suppressing one pulse out of two.
  • the signal ST contains an impulse for each pulling of the crown, the relaxation of the latter producing no effect.
  • the output signals SC2 and ST of circuit 30 drive the inputs of a mode selector circuit 31 providing at its output logic signals F ' 1 , F' 2 , F ' 3 , C' 1 , C ' 2 , C' 3 , C ' 4 .
  • These output signals make it possible to define seven different states corresponding to the seven modes in which the watch is likely to be found.
  • a particular case of correspondence between the modes and the logical states of the signals is shown in table 32 of FIG. 4.
  • each mode corresponds to a high logic level of an output signal, the other signals remaining at the low level.
  • Mode F 1 thus corresponds to a high logic level only of signal F ' 1
  • mode F 2 corresponds to a high logic level of signal F' 2 ... etc.
  • mode C 4 corresponds a high logic level of the signal C ' 4 .
  • the circuits 30 and 31 form the selection part of the diagram in FIG. 4.
  • the time part of this diagram comprises, for its part, a quartz oscillator 35, providing at its output a standard or reference signal of 32,768 Hz for example.
  • This reference signal drives a first frequency divider 36 which delivers two output signals, the first of 8 Hz and the second of 1 Hz.
  • An AND 37 gate with two inputs receives on its first input the signal of 1 Hz and delivers at its output a signal of 1 Hz also when the second input is at high logic level.
  • the output signal from the AND gate 37 drives a second frequency divider or second counter 38 having a reset input R and two outputs, the first delivering a signal of 1/30 Hz and the second a signal of 1 / 60 Hz.
  • These signals are formed by pulses, the first comprising two pulses per minute and the second one pulse per minute.
  • the signal C ' 3 of the circuit 31 is applied to the input R of the frequency divider 38 and to the input of an inverter 39, the output of which is connected to the second input of the AND gate 37.
  • the signal C ' 3 When the watch is in the correction mode C 3 , the signal C ' 3 is at the high logic level. The output of the inverter 39 is then at the low logic level, which has the effect of blocking the AND gate 37 which no longer allows the 1 Hz signal from the frequency divider 36 to pass. The high logic level of the signal C ' 3 also resets the frequency divider 38 to zero. The blocking of the 1 Hz signal and the resetting of the frequency divider 38 by the signal C ' 3 makes it possible to set the watch to the time and to start it exactly at a time signal passing from mode C 3 to mode F 2 , in which the signal C ' 3 is at the low logic level, by means of a pull on the crown 4.
  • the 1/30 Hz signal from the frequency divider 38 drives the first input of an AND gate 71 with two inputs.
  • the second input of this door is connected to the output of an inverter 70 whose input is controlled by the signal C'4.
  • the signal C ' 4 being at the high logic level, this door blocks the signal 1/30 Hz.
  • circuits 30, 31, 37, 39, 70 and 71 form a circuit referenced 200 which fulfills the functions of mode selection and correction of the information of the watch.
  • a motor control circuit 40 having seven inputs and three outputs, receives on its first input the signal of 1/30 Hz, coming from the AND gate 71, and on its second input the signal of 8 Hz, coming from the first divider of frequency 36. The following three inputs respectively receive the signals CD, SC1 and SC2, generated by the circuit 30. Finally, the last two inputs of the circuit 40 are attacked by the signals C ' 3 and C' 4 produced by the circuit 31.
  • the signals 8 t , B 2 , B 3 appearing on the outputs of the circuit 40 which will be described in detail below, attack the two coils of a two-phase bidirectional stepping motor 41.
  • it could just as easily attack a bidirectional single-phase motor.
  • the motor 41 finally drives, via a gear (not shown), the hands 2 of the analog display of the watch.
  • a gear not shown
  • Each step of the motor 41 advances, in the example chosen, the hands 2 by 1/2 minute. It is obvious that another reduction ratio of the gear would make it possible to advance the hands by 1 / n minute with each jump of the motor, which would require attacking the first input of circuit 40 by a signal of frequency n / 60 Hz.
  • each pulse of the signal of frequency 1/30 Hz turns the motor 41 of a step always in the direct direction, it that is to say by advancing the hands 2, whatever the level of the CD signal.
  • the correction mode C 3 the signal C ' 3 being at the high logic level, the circuit 40 becomes sensitive to the signal CD and the motor turns in the direct or reverse direction depending on whether the signal CD is at the low or high logic level .
  • the signal SC1 comes, in circuit 40, in place of the signal 1/30 Hz which is no longer present, the signal of 1 Hz being blocked by the AND gate 37.
  • the signal C'4 is at the high level. This has the effect of blocking the 1/30 Hz signal via the AND gate 71 and of allowing circuit 40 to react only to the signal SC2.
  • Each pulse of the signal SC2 triggers the generation, within the circuit 40, of a second pulse, causing the motor 41 to take two steps very close to each other so that the hands 2 give the impression of move in whole minutes, in one direction or in the opposite direction.
  • the circuit 40 must generate, by means well known to those skilled in the art, n-1 additional pulses so as to move the hands by one minute. whole in a very short time.
  • the minute signal that is to say from 1/60 Hz, coming from the second frequency divider 38, is applied to the first input of a front counting circuit. / rear 42 having 6 inputs and 4 outputs.
  • the second input receives the signal CD, the logic level of which determines the counting mode of circuit 42, forward when the level is low and back when it is high.
  • the correction signal SC2 is applied to the third input.
  • the last three inputs taken in ascending order of their numbering, respectively receive the signals C ' l , C'y and C' 3 .
  • the counting circuit 42 which will be described in detail below, comprises four counters, the first for the minutes, the second for the hours, the third for the days and the fourth for the date.
  • the circuit 42 counts the minute pulses.
  • the first counter then provides on the first output of the counting circuit 42 a multiple signal SM containing j binary signals whose logic states define a number between 0 and 59 corresponding to the number of minutes elapsed since the start of counting.
  • the second counter provides on the second output ur, multiple signal SH giving the number of hours
  • the third counter provides a multiple signal SJ on the third output giving a number corresponding to the day of the week.
  • the fourth counter produces on the fourth output a multiple signal SD giving the date.
  • correction mode C 1 the signal C 'is at the high logic level. This makes it possible to add or subtract, in the third counter of the circuit 42, a certain number of pulses produced by the correction signal SC2 in order to correct the day of the week. Similarly in mode C 2 , the signal SC2 makes it possible to correct the date contained in the fourth counter. Finally in mode C 3 the minute pulses being blocked, the correction signal is applied to the first input of circuit 42. This makes it possible to correct the hour and minute indication in steps of 1 minute contained in the first and second counters .
  • a display selector circuit 43 shown in FIG. 4, is used to direct the information corresponding to each operating mode of the watch to display 3. .
  • Circuit 43 has ten inputs and two outputs. The first four inputs, taken in ascending order of their numbering, respectively receive the multiple signals SM, SH, SJ and SD of circuit 42. The next six inputs, also considered in ascending order, respectively receive the signals F ' 1 , F ' 2 , C' 1 , C ' 2 , C' 3 and C ' 4 of circuit 31. Circuit 43 provides a multiple signal x (J; H) on its first output and a multiple signal y (D; M) on its second output. Depending on the mode in which the watch is located, the signal x is identical to the multiple signal SJ or the multiple signal SH and the signal y to the multiple signal SH or the multiple signal SM.
  • the high logic level of the signal F ' means that the signal x corresponds to the signal SJ and the signal y to the signal SD.
  • the signal x contains the information of the signal SH and the signal y that of the signal SM.
  • the circuit 43 not being controlled by the signal F ' 3 , the signals x and y do not contain any information.
  • the signals x (J; H) and y (D; M) coming from the circuit 43 drive the inputs of a conventional decoder circuit 44 which in turn controls the digital display 3, for example with liquid crystal.
  • the characters X display the information contained in the signal x and the characters Y those contained in the signal y.
  • circuits and components appearing in the block diagram of FIG. 4 are of the conventional type and well known with the exception of circuits 30, 31, 40, 42 and 43. These latter circuits fulfilling functions related to the present invention, they will be now described in detail.
  • the diagram of the encoder circuit 30 is shown in FIG. 5. It includes a circuit 50 with two inputs and three outputs, an OR gate 51 with two inputs, a frequency divider by two 52 and a contact bounce circuit 53.
  • the first input of circuit 50 receives the signal from contact 17 and the second input that of contact 18.
  • the output S of circuit 50 provides the signal CD whose logic level depends on the direction of rotation of the crown 4.
  • the output U of this circuit provides pulses when the crown rotates in a first direction, and no pulses when the crown rotates in a second direction, opposite to the first.
  • the output D provides pulses when the crown turns in the second direction and no pulses when it rotates in the first direction.
  • the number of pulses is proportional to the angle of rotation of the crown.
  • FIG. 3 of one of these documents gives the complete diagram of the circuit in which the inputs 15 and 16, provided with anti-rebound circuits of the contacts, the output of the AND gate 41, the output of the inverter 37 and the output of the inverter 38 correspond respectively to the first and to the second input, to the output S, to the output U and to the output D of the circuit 50 of the present application.
  • the outputs U and D of circuit 50 are connected respectively to the first and to the second input of the OR gate 51, which supplies at its output the correction signal SC1.
  • the signal SC1 contains, when the circuit 50 is identical to that of the cited patent CH 632 894, a number of pulses equal to the number of closings and openings of the contacts 17 and 18, i.e. 8 pulses for a 360 ° rotation of the crown 4. This signal also attacks the frequency divider by two 52, the output of which delivers the correction signal SC2 containing one pulse out of two of the signal SC1.
  • the anti-rebound circuit 53 receives on its input the signal coming from contact 20 and delivers on its output the signal ST containing a pulse for each traction on the crown 4.
  • FIG. 6 represents the diagram of a possible embodiment of the mode selector circuit 31. It comprises two shift registers with three positions 55 and 56, each having an input CL and three outputs Q 1 , Q 2 and Q 3 , two shift registers with two positions 57 and 58, each having an input CL and two outputs Q, and Q 2 , seven doors AND with two inputs referenced 59 to 65 and an OR 66 door with three inputs.
  • the output Q 1 of the register 55 is connected to the first inputs of the AND gates 60 and 63.
  • the output Q 2 of the same register is connected to the first inputs of the AND gates 61 and 64.
  • the output Q 3 is connected to the first inputs of the gates ET 62 and 65.
  • the second inputs of AND gates 60 to 62 receive the signal ST.
  • the second inputs of AND gates 63, 64 and 65 are connected respectively to outputs Q 1 of registers 56, 57 and 58.
  • the outputs of AND gates 60, 61 and 62 are connected respectively to inputs CL of registers 56, 57 and 58.
  • the outputs of AND gates 63, 64 and 65 respectively supply the signals F ' 1 , F' 2 and F ' 3 .
  • the outputs Q 2 and Q 3 of the register 56 respectively supply the signals C ' 1 and C' 2 .
  • the outputs 0 2 of the registers 57 and 58 respectively supply the signals C ' 3 and C' 4 .
  • the first input of AND gate 59 receives the signal SC2, but the signal SC1 could also be used in place of the signal SC2. The output of this same gate attacks the input CL of the register 55.
  • the second input of the AND gate 59 receives the output signal of the OR gate 66 whose three inputs are controlled respectively by the signals F ' 1 , F ' 2 and F' 3 .
  • the high logic level of the signal F ', at the input of the OR gate 66 means that the second input of the AND gate 59 is also at the high logic level.
  • a first pulse of signal SC2 can then pass through this latter gate and control the input CL of register 55, which has the effect of passing its output Q 1 to the low logic level and its output Q 2 to the high logic level.
  • the two inputs of the AND gate 64 now being at the high logic level, the signal F ' 2 at the output of this gate also takes the same logic state.
  • the first pulse of signal SC2 therefore has the effect of passing signal F ' 1 to the low logic level and the signal F' 2 to the high logic level.
  • the signal F ' 2 also being present on an input of the OR gate 66, the second input of the AND gate 59 is always at the high logic level.
  • a second pulse of the signal SC2 can therefore reach the input CL of the register 55 and pass its output O2 to the low logic level and its output Q 3 to the high logic level.
  • the first input of the AND gate 64 thus being at the low logic level, the signal F ' 2 on its output takes the same logic state.
  • the two inputs of the AND gate 65 being on the other hand at the high logic level, there is at its output the same logic state on the signal F ' 3 .
  • the second pulse of the signal SC2 therefore has the effect of passing the signal F ' 2 to the low logic level and the signal F' 3 to the high logic level.
  • Analogous reasoning would show that a third pulse of the signal SC2 would bring the circuit into its initial state in which only the signal F ' 1 is at the high logic level.
  • a second pulse of the signal ST passes, for the same reasons, the output Q 2 of the register 56, as well as the signal C ' 1 , at the low logic level and the output Q 3 , as well as the signal C' 2 , at the level high logic.
  • the second input of the AND gate 59 is also at the low logic level. In the correction modes Ci and C 2, the latter gate therefore blocks the pulses of the signal SC2.
  • a third pulse of the signal ST returns the circuit to its initial state with a high logic state on the output Q 1 of the register 56.
  • FIG. 7 shows the diagram of a possible embodiment of the control circuit 40 of the motor 41.
  • This circuit comprises four AND gates referenced 72 to 76, with two inputs, two OR gates, referenced 77 and 78, with two inputs, an OR gate 79 with three inputs, a delay flip-flop 80 having two inputs denoted CL and D and an output Q and finally a drive circuit 81 of the motor having two inputs denoted CL and C / D and four outputs denoted Q , B 1 , B 2 and B 3 .
  • the signal 1/30 Hz from the output of the AND gate 71 attacks the first input of the OR gate 77 and the second input of the latter gate receives the signal supplied by the output of the AND gate 72.
  • the first inputs of the gates AND 72 and 73 are connected together and are controlled by the signal C ' 4 .
  • the second input of AND gate 72 receives the signal SC2.
  • the second input of AND gate 73 is connected to output Q of flip-flop 80.
  • the first and second inputs of AND gate 74 receive signals SC1 and C ' 3 respectively .
  • the output of the latter gate is connected to the first input of the OR gate 79.
  • the output of the OR gate 77 and the output of the AND gate 73 are connected respectively to the second and to the third input of the OR gate 79.
  • the output of this last gate is connected to the input CL of circuit 81.
  • the first inputs of AND gates 75 and 76 receive the signal CD generated by circuit 30.
  • the second inputs of these latter gates respectively receive signals C ' 3 and C ' 4 .
  • the first and second input of the OR gate 78 are connected respectively to the output of the AND gate 75 and to the output of the AND gate 76.
  • the C / D input of the circuit 81 is connected to the output of the OR gate 78 and the output Q of this same circuit is connected to the input D of the circuit 80.
  • the input CL of the circuit 80 receives the 8 Hz signal coming from the frequency divider 36, but any signal having a frequency of the same order of grandeur might also be suitable.
  • the drive circuit 81 located in FIG. 7 is intended to supply signals B 1 , B 2 , B 3 to the two coils, connected in series, of the two-phase motor 41 so as to rotate it one step at a time. response to each pulse applied to the CL input.
  • the signal B 1 is applied to a terminal of the first coil, the signal B 2 to a terminal of the second coil and the signal B 3 to the terminal common to the two coils.
  • One motor step corresponds to a 180 ° rotation of the rotor and it advances the minute hand of the analog display by 1/2 minute.
  • the rotor can therefore occupy two positions and each position corresponds to a logic state of the Q output.
  • the rotation takes place in one direction or the other depending on the logic state of the C / D input. It will be assumed that the motor turns in the direction which advances the hands 2 when the terminal C / D is at the low logic level.
  • FIG. 5 of this document gives an example of a diagram.
  • C k and Q of the flip-flop 34 and AR at the input of the inverter 29 correspond respectively to CL, Q and C / D of the circuit 81 of the present application.
  • the signal on the point common to the transistors T 5 and T 6 of the cited request corresponds to the signal B 1 of the present request.
  • the signal on the point common to the transistors T 1 and T 2 corresponds to the signal B 2 and that of the point common to the transistors T 3 and T4 to the signal B 3 .
  • the first corresponds to that where the signals C ' 3 and C' 4 are at the low logic level, causing the same logic state on one of the inputs of AND gates 72 to 76 and on the output of each of these gates.
  • This has the consequence of blocking the signals SC1, SC2 as well as the signal at the output Q of the flip-flop 80 respectively by the AND gates 74, 72 and 73 and of forcing a low logic level on the C / D input of the circuit 81 via AND gates 75, 76 and OR gate 78.
  • the low logic state of signal C ' 4 causes a high logic level at the output of inverter 70 as well as at the second input of AND gate 71 which thus lets pass the 1/30 Hz signal present on its first input.
  • This signal then passes through the OR gates 77 and 79, the other inputs all being at the low logic level, to come to control the CL input of the circuit 81.
  • the C / D input of the circuit 81 is therefore at the low logic level and the 1/30 Hz signal directly controls the CL input.
  • the second case is that where the signal C'3 is at the high logic level and the signal C ' 4 at the low logic level.
  • the second inputs of AND gates 74 and 75 are then at the high logic level, allowing the signal SC1 to reach the first input of the OR gate 79 and the CD signal to the C / D input of circuit 81 through the OR gate. 78.
  • the 1 Hz signal being blocked by the AND gate 37, the 1/30 Hz signal does not exist and only the SC1 signal arrives through the OR gate 79 on the CL input of circuit 81, making it possible to correct the analog display forward or backward.
  • the signal C ' 3 is at the low logic level and the signal C' 4 at the high logic level.
  • the signals 1 / 30 Hz and SC1 are blocked while the signal SC2 arrives on the second input of the OR gate 77, the signal at the output Q of the flip-flop 80 arrives on the third input of the OR gate 79 and finally that the signal CD arrives on the input C / D of circuit 81.
  • the signal SC2 thus arrives on the input CL of circuit 81 through the OR gates 77 and 79 and the output signal Q of flip-flop 80 arrives on the same input through OR gate 79. It will be assumed that the output Q of circuit 81 is at the low logic level if the minute hand is over a full minute and at the high logic level if this hand is between two minutes. The logic level of the output Q of the circuit 81, applied to the input D of the flip-flop 80 will be found, after half a period of the 8 Hz signal applied to its input CL, or 1/16 of a second later, on the exit Q of this rocker.
  • the minute hand is not on an entire minute and that the output Q of the flip-flop 80 is already at the high logical level.
  • the transition of the signal C ' 4 passing through the AND gates 73 and OR 79, will control the input CL of the circuit 81 and cause the motor 41 to advance by one step.
  • the minute hand will then indicate a full minute, the Q output of circuit 81 will go to the low logic state and, 1/16 of a second later, the Q output of flip-flop 80 will take the same logic state.
  • FIG. 8 represents a possible embodiment of the counting circuit 42.
  • This circuit includes a minute counter 85, an hour counter 86, a day counter 87 and a date counter 88, each counter having two inputs, noted CL and C / D, and two outputs, noted Q 1 and Q 2 , six AND gates with two inputs, referenced 89 to 94, and three OR gates with two inputs referenced 95 to 97.
  • the inputs CL of counters 85 to 88 receive the counting pulses, the direction of counting being determined by the logic level of the input C / D. It will be assumed that the content of the counter is incremented by each counting pulse if C / D is at the low logic level and decremented otherwise.
  • the counter output Q1 is multiple and contains the number of binary signals necessary to define the maximum content of each counter.
  • the output Q 1 of the hour counter 86 provides h 1 , h 2 , ... h k binary signals defining a number between 1 and 12 or between 1 and 24, all of these signals forming the signal multiple of hours SH.
  • the output Q 1 of the two-day counter 87 provides j 1 , j 2 , ... j l binary signals defining a number between 1 and 7, each number corresponding to a day of the week. All of these signals form the multiple signal of the days SJ.
  • the output Q 1 of the date counter 88 provides d 1 , d 2 , ... d m binary signals defining a number between 1 and 31, all of these signals forming the multiple signal of the date SD.
  • a counter once fully filled, generates a pulse on its output Q 2 .
  • the first input of OR gate 95 receives the 1/60 Hz signal from frequency divider 38 and the second input of this gate is connected to the output of AND gate 89.
  • the first input of AND gate 89 receives the signal C ' 3 and the second input of this gate receives the correction signal SC2.
  • the inputs C / D of the counters 85 and 86 are connected to the output of the AND gate 90 which receives on its first input the signal C'3 and on its second input the signal CD.
  • the output Q 2 of the counter 85 is connected to the input CL of the counter 86, the output Q 2 of which is connected to the first input of the OR gates 96 and 97.
  • the second input of the OR gate 96 is connected to the output of the AND gate 91, which receives on its first input the signal C ', and on its second input the correction signal SC2.
  • the second input of the OR gate 97 is connected to the output of the AND gate 94, which receives on its first input the signal C ' 2 and on its second input the correction signal SC2.
  • the output of the OR gate 96 is connected to the input CL of the counter 87, the output Q 2 of which remains free.
  • the output of the OR gate 97 is connected to the input CL of the counter 88, the output Q 2 of which also remains free.
  • the input C / D of the counter 87 is connected to the AND gate 92, which receives on its first input the signal C ', and on its second input the signal CD.
  • the input C / D of the counter 88 is connected to the output of the AND gate 93, which receives on its first input the signal C ' 2 and on its second input the signal CD.
  • the low logic level of the signals C ' 1 , C' 2 and C ' 3 in the first case causes a low logic level on the first input of the AND gates 89 to 94, therefore a logic level also low on the outputs of these gates, regardless of the logic level of the second input. This results in a low logic level on the C / D input of counters 85 to 88. Each counting pulse on the CL input thus increments their content.
  • the second inputs of the OR gates 95 to 97 are also at the low logic level. These doors therefore only transmit the signal present on their first input. Only the 1/60 Hz minute signal therefore reaches, via the OR gate 95, the CL input of the minute counter 85.
  • the content of this counter appears on the output Q 1 while on the output Q 2 appears a signal containing one pulse per hour, which is applied to the CL input of the hour meter 86.
  • the content of the counter 86 appears on the output Q 1 while the output 0 2 delivers a signal containing a pulse per 24 hours.
  • This last signal attacks, through OR gates 96 and 97, the CL input of the day counter 87 and the date counter 88.
  • the content of these counters appears on their output Q 1 .
  • the circuit 42 thus simply counts the minute pulses and provides the information relating to the hour, the day and the date.
  • the second case is that where the signal C ' 1 is at the high logic level and the signals C' 2 and C ' 3 at the low logic level.
  • the first input of AND gates 91 and 92 then being at the high logic level, at the output of these gates, the signals SC2 and CD appear respectively.
  • the signal SC2 then arrives through the OR gate 92 on the input CL of the day counter 87 and the signal CD on the input C / D of the same counter.
  • the pulses of the signal SC2 generated by the rotation of the crown 4 then make it possible to modify, more or less depending on the direction of rotation, the content of the day counter.
  • the third case it is the signal C ' 2 which is at the high logic level and the signals C' 1 and C ' 3 at the low logic level.
  • This case is similar to the previous ones, the first input of the AND gates 93 and 94 being at the high logic level, the signal SC2 arrives, through the OR gate 94, on the input CL of the date counter 88 and the signal CD on the 'C / D input of the same counter. The rotation of the crown 4 then makes it possible to modify the content of this counter.
  • the signal C ' 3 is at the high logic level and the signals C' 1 and C ' 2 at the low logic level.
  • the first input of the AND gates 89 and 90 being at the high logic level, the signal SC2 arrives on the input CL of the minute counter 85 through the OR gate 95 and the signal CD on the input C / D of the counters 85 and 86.
  • the pulses of the signal SC2, in response to the rotation of the crown 4, then make it possible to correct the time information by modifying the content of the counters 85 and 86.
  • FIG. 9 A possible form of the diagram of the display selector circuit 43 is shown in FIG. 9.
  • This circuit includes p all identical switching circuits, referenced 100 1 , 100 2 , ... 100p and q all identical switching circuits, references 101 1 , 101 2 , ... 101 q . These circuits each have seven inputs and one output and will be described in detail later.
  • the circuit 100 1 receives on its first input the signal j 1 , contained in the multiple signal SJ supplied by the circuit 42, on its second input the Signal h 1 , contained in the multiple signal SH, on the following 5 inputs, taken from the increasing order of their numbering, respectively the control signals F ' 1 , F' 2 , C ' 1 , C' 3 , C ' 4 and it delivers on its output the signal x.
  • the circuit 100 2 receives on its first two inputs the signals j 2 and h 2 , on the other inputs the same control signals as the circuit 100 1 and it delivers on its output the signal x 2 .
  • the signals x 1 , x 2 , ... x of this circuit define the multiple signal x (J; H).
  • circuit 101 1 receives on its first input the signal d 1 , on its second input the signal m 1 , on the five following inputs respectively the control signals F ' 1 , F' 2 , C ' 2 , C ' 3 , C' 4 and it outputs the signal y 1 at its output.
  • circuit 101 q can be said exactly the same as for circuit 100p provided that j is replaced by d, h by m, the index 1 by n, the index k by j and the index p by q .
  • the signals y 1 , y 2 , ... Y q of these circuits define the multiple signal y (D; M).
  • the selection circuits 100 1 to 100p will transmit on their respective output, i.e. signals j 1 ... j 1 , i.e. the signals h 1 ... h k .
  • the signal x 1 will be identical to the signal j 1
  • the signal x 2 to the signal j 2 etc.
  • the signal x (J; H) will be identical to the signal SJ.
  • the output signal x (J; H) will be identical to signal SH.
  • the selection circuits 101, to 101q operate in a similar fashion. If one of the signals F ' 1 or C' 2 is at the high logic level and the other control signals at the low logic level, the output signal y 1 will be identical to the signal d 1 , the signal y 2 to the signal d 2 etc. and finally the signal y (D; M) will be identical to the signal SD. Finally if it is one of the signals F ' 2 , C' 3 , C ' 4 which is at the high logic level and the other control signals at the low logic level, the signal y (D; M) will be identical to the signal SM.
  • FIG. 10a An exemplary embodiment of the switching circuit 100 1 is shown in FIG. 10a.
  • This circuit includes two AND gates 110 and 111 with two inputs, two OR gates 112 and 113 with two inputs and an OR gate 114 with three inputs.
  • the first input of the AND gate 110 receives the signal j 1 and the second input of this gate is connected to the output of the OR gate 112.
  • the first input of the OR gate 112 receives the signal F ' 1 and the second input of this door receives the signal C ' 1 .
  • the first input of AND gate 111 receives the signal h 1 and the second input of this gate is connected to the output of OR gate 114.
  • OR gate 114 The three inputs of OR gate 114, taken in ascending order of their numbering, receive signals F ' 2 , C' 3 and C ' 4 respectively . Finally the signal x 1 is taken on the output of the OR gate 113, one input of which is connected to the output of the AND gate 110 and the other input to the output of the AND gate 111.
  • the operation of the routing circuit 100, of FIG. 10a is as follows. If one of the signals F ', or C', is at the high logic level and the other control signals F ' 2 , C' 3 , C ' 4 at the low logic level, the output of the OR gate 112 will be at the level logic high and the output of OR gate 114 at logic low level.
  • the second input of the AND gate 111 being at the low logic level, this gate blocks the signal h 1 applied to its first input.
  • the second input of the AND gate 110 being on the other hand at the high logic level, it allows the signal j to pass, which is thus found at the output of the OR gate 113.
  • the signal x is therefore identical, in this case, at signal j 1 .
  • the structure of the switch circuit 101, shown in FIG. 10b is identical to that of the circuit 100 1 , the two circuits comprising the same doors interconnected in the same way.
  • the first input of the AND gate 110 receives the signal d 1 instead of j 1
  • the first input of the AND gate 111 receives the signal m 1 instead of h 1
  • the second input from OR gate 112 receives signal C ' 2 instead of C' 1 .
  • the other inputs of the OR gates 112 and 114 receive the same signals in the two circuits.
  • circuit 101 1 in FIG. 10b The operation of circuit 101 1 in FIG. 10b is also similar to that of circuit 100 1 . Taking into account the fact that different signals are applied to certain inputs of circuits 100, and 101 1 , the signal y 1 will be identical to the signal d 1 if one of the signals F ' 1 or C' 2 is at the high logic level and other control signals at the low logic level. Similarly, the signal y 1 will be identical to the signal m 1 if it is one of the signals F ' 2 , C' 3 , C ' 4 which is at the high logic level and the other control signals at the low logic level.
  • the hands of the analog display could be replaced by discs bearing marks.
  • digital display could be achieved using light-emitting diodes, electrochromic devices, etc. instead of liquid crystals.
  • the crown could have more than two axial positions in order to increase its control possibilities.
  • Other control elements for example push-buttons actuating contacts, capacitive keys, photoelectric sensors etc. could be used in place of or in conjunction with a crown.
  • the correction pulses could be taken from the frequency divider.
  • the digital display could have an indication of seconds; in this case, the watch could include means making it possible to align the minute hand with the seconds, preferably automatically when exiting synchronization mode.
  • the digital display and the analog display could both display the second, and in this case the synchronization mode could be reserved for aligning the second hand with the seconds of the digital display.
  • An additional synchronization mode could be provided to allow in addition to separately align the hour hand with the hours of the digital display. Many variations are possible.

Claims (6)

1. Elektronische Uhr, bestehend aus:
- einer Zeitbasis zur Erzeugung eines Standardfrequenzsignals:
- einer Schaltung zum Teilen der Frequenz des genannten Standardfrequenzsignals;
- Organen für die Anzeige einer ersten Informationsgruppe in analoger Form, wobei eines der genannten Organe die laufende Minute anzeigt;
- einem mit den genannten Anzeigeorganen mechanisch gekuppelten Schrittmotor;
- einer Steuerschaltung, um am Motor Antriebsimpulse anzulegen und die Verstellung der genannten Anzeigeorgane motorisch anzutreiben bei Erscheinen von von der Frequenzteilerschaltung gelieferten Impulsen und von Korrekturimpulsen;
- einer Zählerschaltung, die ebenfalls die Zeitimpulse der genannten Frequenzteilerschaltung empfängt, um einer zweiten Zeitinformationsgruppe zugeordnete zu liefern, wobei mindestens eine der Informationen dieser zweiten Gruppe auch bei der ersten Gruppe beteiligt ist;
- einer elektrooptischen Vorrichtung, die mit der genannten Zählerschaltung verbunden ist, um die Informationen der genannten zweiten Gruppe in numerischer Form anzuzeigen;
- manuellen Steuermitteln; und
- einer logische Wahl- und Korrekturschaltung, die bei Betätigen der genannten manuellen Steuermittel die Uhr in verschiedene Anzeigemodi versetzt, für die jeweils eine gewählte Zeitinformation über die genannnte elektrooptische Anzeigeeinheit angezeigt wird, in verschiedene Korrekturmodi, für die jeweils eine in numerischer Form angezeigte Information durch Anlegen von aus der logischen Schaltung kommenden Korrekturimpulsen an die genannte Zählschaltung korrigiert werden kann, wobei die genannte logische Schaltung ausserdem auch Korrekturimpulse am Steuerkreis des Motors anlegt, wenn die korrigierte Information beiden Gruppen gemeinsam ist, wobei die genannte gemeinsame Information die Anzeige der laufenden Minuten ist und das genannte Minutenanzeigeorgan normalerweise mit n Schritten pro Minute läuft, wobei n grösser als 1 ist, so dass die Anzeige in analoger Form und die Anzeige in numerischer Form dieser Information beide um einen selben Betrag geändert werden, und in einen zusätzlichen Synchronisationsmodus, in welchem die genannte gemeinsame Information durch die elektrooptische numerische Anzeigevorrichtung angezeigt wird und in welchem die genannte logische Schaltung bei einer Betätigung der genannten manuellen Steuermittel Korrekturimpulse einzig an die genannte Steuerschaltung des Motors anlegt um zu gestatten, die Anzeige in analoger Form in übereinstimmung mit der Anzeige in numerischer Form zu bringen, dadurch gekennzeichnet, dass die Steuerschaltung (40) des Motors (41) so wirkt, dass das genannte Anzeigeorgan der Minuten (2) beim Übergang auf den Synchronisationsmodus automatisch auf eine ganze Minute geführt wird und dass sie in diesem Modus n aufeinanderfolgende Antriebsimpulse erzeugt und an den Motor (41) anlegt, und zwar bei jedem Korrekturimpuls, den die genannte Steuerschaltung (40) von der genannten logischen Schaltung (200) empfängt.
2. Uhr gemäss Anspruch 1, dadurch gekennzeichnet, dass die genannte logische Schaltung (200) Mittel (70; 71) umfasst, um das Anlegen von Zeitimpulsen an die genannte Steuerschaltung (40) des Motors (41) im Synchronisationsmodus zu verhindern.
3. Uhr gemäss Anspruch 1, dadurch gekennzeichnet, dass die genannte Anzahl von n Schritten pro Minute gleich 2 ist.
4. Uhr gemäss einem der Ansprüche 1 oder 3, dadurch gekennzeichnet, dass die genannte erste und die genannte zweite Gruppe eine weitere Zeitinformation gemeinsam haben, wobei diese weitere Information die Anzeige der laufenden Stunden ist.
5. Uhr gemäss einem der vorstehenden Ansprüche, dadurch gekennzeichnet, dass der genannte Schrittmotor (41) ein zweiseitig drehender Motor ist und dass die genannten Zählmittel (42) aufwärts und abwärts zählen können, um eine Änderung der Zeitinformationen der beiden Gruppen in beiden Richtungen zu gestatten.
6. Uhr gemäss einem der vorstehenden Ansprüche, dadurch gekennzeichnet, dass die genannten manuellen Steuermittel aus einer drehbaren Krone (4) bestehen, die zwischen mindestens zwei axialen Positionen verstellbar ist und elektrische Kontakte (17; 18; 20) betätigt, die mit der genannten logischen Schaltung (200) verbunden sind.
EP84111882A 1983-10-25 1984-10-04 Uhr mit analogischer und numerischer Anzeige Expired EP0143279B1 (de)

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CH577283A CH653848GA3 (de) 1983-10-25 1983-10-25
CH5772/83 1983-10-25

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EP (1) EP0143279B1 (de)
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JPS60111984A (ja) 1985-06-18
CH653848GA3 (de) 1986-01-31
DE3469233D1 (en) 1988-03-17
JPH077077B2 (ja) 1995-01-30
HK21993A (en) 1993-03-19
EP0143279A1 (de) 1985-06-05
US4600316A (en) 1986-07-15

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