EP0267440B1 - Analog-Uhr mit zwei Motoren, die einen ewigen Tageszähler enthält - Google Patents
Analog-Uhr mit zwei Motoren, die einen ewigen Tageszähler enthält Download PDFInfo
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- EP0267440B1 EP0267440B1 EP87114859A EP87114859A EP0267440B1 EP 0267440 B1 EP0267440 B1 EP 0267440B1 EP 87114859 A EP87114859 A EP 87114859A EP 87114859 A EP87114859 A EP 87114859A EP 0267440 B1 EP0267440 B1 EP 0267440B1
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- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G19/00—Electric power supply circuits specially adapted for use in electronic time-pieces
- G04G19/10—Arrangements for supplying back-up power
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- G—PHYSICS
- G04—HOROLOGY
- G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
- G04C17/00—Indicating the time optically by electric means
- G04C17/005—Indicating the time optically by electric means by discs
- G04C17/0058—Indicating the time optically by electric means by discs with date indication
- G04C17/0066—Indicating the time optically by electric means by discs with date indication electromagnetically driven, e.g. intermittently
Definitions
- the present invention relates to an analog electronic watch comprising two motors, the first motor driving the time display and the second motor displaying the date. It relates more particularly to a watch further comprising a perpetual calendar circuit.
- This circuit includes day, month and year counters and supplies a signal representing the date to a control circuit which activates the second motor by advancing it by the number of steps necessary so that the indication of the date corresponds to the content of the day counter and therefore be in accordance with the indication of a perpetual calendar.
- Such watches are well known and an exemplary embodiment is described in US Pat. No. 4,300,222.
- the watch described in this document is provided with a perpetual calendar displaying the date and, possibly, the day of the week. If the calendar does not raise any criticism as long as the watch functions normally, on the other hand, after a change of battery, the counters putting themselves in states having no relation to the date, the calendar circuit is no longer able to provide correct signals.
- the counters and the date display must therefore be set, as well as, of course, the time of the watch.
- the correction operation of the date display is done conventionally.
- setting the meters is hardly achievable by the user, nor by a watchmaker who does not have adequate equipment.
- each counter in order to reduce the duration of operations, each counter must be corrected separately, which implies complex manipulations.
- to carry out this correction it is necessary to know the content of the counters. However, this information does not appear on the watch display.
- the battery change can only be carried out in the factory or in an after-sales service center, which constitutes a major constraint in the use of a watch which is otherwise very practical.
- the object of the invention is to overcome this drawback by proposing a watch whose perpetual calendar requires, after replacing the battery, only a correction of the date display using simple manipulation, which can be made by the wearer of the watch.
- An advantage of the present invention comes from the fact that after a battery change, provided that be made within one month from the date the watch stops, a conventional calendar watch is enough for the perpetual calendar circuit to function properly again.
- Another advantage of the invention is that it does not require memorizing, every 24 hours, the content of the day counter in the non-volatile memory, this making it possible to reduce the surface of this memory, to reduce its consumption and to increase its lifespan.
- FIGS. 1, 2 and 3 show the diagrams of an embodiment of the circuit of the watch according to the present invention, the references a, b, c ... m indicating the connection points between the conductors passing from one figure to another.
- timekeeping circuit 1 which provides a time base signal S1 to a first motor 2 which, by means of a control mechanism 3, causes a time display 4 comprising hands hours, minutes and seconds.
- the timepiece circuit 1 includes an oscillator 10 providing a signal of 32,768 Hz for example, frequency stabilized by a quartz resonator 11, an ET12 gate with two inputs, one input being connected to the output of the oscillator, a divider 13 whose input is connected to the output of the ET12 gate, an ET104 gate with two inputs, an input being connected to an output of the divider delivering a signal of 1 Hz, and a drive circuit 14 receiving carries ET104 the signal of 1 Hz and providing at its output the signal S1.
- the frequency divider 13 also has an e output which delivers a fast forward or catch-up signal S13 having a frequency of the order of 10 Hz, and a reset input R which makes it possible to reset the last stages of the divider, located after the stage providing the signal S13.
- This input R is connected to the output of an inverter 15 whose input is connected to the second input of the gate ET12.
- the first motor 2 is, for example, of the stepping type with a direction of rotation, or unidirectional. It drives, in the control mechanism 3, a first gear train, not shown, which advances the hands of the display 4. This same gear train also actuates a daily contact X, or first contact, closing it when switching the watch from one day to the next, conventional analog whose operation is as follows.
- the gate ET12 lets pass the signal from the oscillator 10 to the frequency divider 13.
- the reset input R of the divider being at the low logic level, this circuit provides the signal of 1 Hz to the input of the drive circuit 14 through the gate ET104 whose other input is supposed for the moment to be at the high logic level.
- the circuit 14 in turn supplies the time base signal S1 to the first motor 2.
- This motor drives, via the first gear train, the hands of the time display 4 and actuates, at the using the same gear train, contact X.
- the daily signal Sx produced by this contact goes, at midnight, from low logic level to high level and returns, a little later, to low logic level, state in which it remains until the start of the next day.
- the signal Sy is at the low logic level, which has the effect of blocking the gate ET12 and of resetting, through the inverter 15, the frequency divider 13 which receives no signal under these conditions. It is the same for engine 2, which remains at rest.
- the hands of the display 4 can then only be moved by the crown which, in this position, is linked to the gear train in order to allow the watch to be set precisely.
- the contact X is activated in the same way as when they are driven by the first motor.
- the watch also has a perpetual calendar which indicates the day of the month.
- This information is given by a date display 20, produced in a conventional manner using a disc carrying the numbers 1 to 31.
- the display 20 is separated from the display 4, but in reality the date appears in a window 21 of the time display.
- the display 20 also activates a date contact Z on the first of each month using, for example, a tooth 22 placed on the disc opposite the number 1.
- This contact provides a date signal Sz which passes at the high logical level at the beginning of the first of each month to return, a day later, to the low logical level, state in which it remains until the beginning of the following month.
- the jump to the date is carried out using a second unidirectional motor 23 which drives the display 20 via a second gear train 24.
- the motor 23, for its part, is activated by a signal S25 control unit supplied by a control circuit 25.
- This circuit 25 comprises an ET26 gate with three inputs, an OU27 gate with two inputs, one input of which is connected to the output of the gate ET26, and a drive circuit 28 connected to the output of the gate 27 and which provides its output the control signal S25.
- An input of the gate ET26 receives the catch-up signal S13, another input receives the date signal Sz, and the last input a monthly signal which will be defined later.
- the other input of gate OU27 receives the daily signal Sx.
- the watch also has a perpetual calendar circuit 30 comprising a day counter 31 of 5 bits counting by 31, a month counter 32 of 4 bits counting by 12 and a year counter 33 of 2 bits counting by 4.
- the entry of the counter 33 is connected to the output of the counter 32 and it is assumed for the moment that the input of the latter counter is directly connected to the output of the counter 31.
- the counter 31 receives on its counting input the si general daily Sx and provides on an output, at the start of each month, the monthly signal, referenced Sm, to counter 32 which, in turn, provides at the start of each year an annual signal Sa to counter 33.
- the signal Sx is applied at counter 31 through a door OU108 with two inputs, one input being connected to contact X while the other input is assumed for the moment to be at the low logic level.
- each counter On another output of each counter there appears a signal representative of its content, referenced S31 for the counter 31, S32 for the counter 32 and S33 for the counter 33.
- the counter 32 furthermore supplies a signal Smc indicating the short months of less than 31 days and the counter 33 a Sab signal indicating the leap year in a 4-year cycle.
- the circuit 30 further comprises a correction circuit 34 which receives the signals Smc and Sab.
- This circuit elaborates, from the signals Smc and Sab, a correction signal S34 for the counter 31, putting the content of this counter to 1 when the calendar changes from one short month to the next month. In this way the content of the counter 31 always remains in accordance with the indications of a perpetual calendar.
- the set of signals S31, S32, and S33 forms an 11-bit calendar signal representative of the date contained in the counters 31, 32 and 33.
- Each of these counters also includes an input E enabling them to be set, using a logic signal, respectively on a given day, month and year. However, this date setting can only be carried out in the factory.
- circuit 30 will not be described in detail since such circuits are well known and an exemplary embodiment is described in the cited reference.
- the monthly signal Sm is applied to the last input of the gate ET26 of the control circuit 25 through a gate OU106 with two inputs, one input receiving the signal Sm and the other input a logic signal assumed for the moment to be low. .
- the operation of the circuit 25 is as follows. Assuming that the date 20 and the calendar circuit 30 have been set to the date, the daily signal Sx, reaching midnight the entry of the attack circuit 28 through the gate OU27, will advance the date 20 by one day . The same signal will also increment the day counter 31 by one. If the date and the day counter indicate a date other than that of the last day of a month, the signals Sz and Sm will be respectively at the high logic level and at the low logic level. The catch-up signal S13, in this case, is blocked by means of the gate ET26 by the signal Sm. The date 20, having taken a step, will therefore remain in this position until the next contact X is closed.
- the signal Sx will make, at midnight, the date to 31 and the content of the day counter to 1.
- the signal Sm will then pass to the logic level high, level at which the signal Sz is located since the contact Z is closed in this position of the date.
- the catch-up signal S13 is assumed to be formed of pulses and to have a frequency of 8 Hz, for example. This signal can, under these conditions, pass through the gates ET26 and OU27 and reach the input of circuit 28. In response to each pulse of signal S13, circuit 28 produces a signal advancing the date by one day.
- the date indicating 31, a single pulse of the signal S13 is sufficient to change the date to 1 and bring it into line with the content of the counter 31.
- the contact Z is open and the signal Sz is at the low logic level.
- the date therefore remains in this position until the next daily signal Sx which will change the date 20 and the content of the counter 31 to 2.
- At these states of the date 20 and of the counter 31 correspond a high logic level of the signal Sz, the contact Z being closed, and a low logic level of the signal Sm.
- This last signal then has the effect of blocking the signal S13 by means of the gate ET26 until the content of the counter 31 has again reached the value 1.
- this contact also makes it possible, in the event of a malfunction of the date, to synchronize the date with the content of the day counter on the first of each month. Indeed, whatever the indication provided by the date 20 when the content of the counter 31 is equal to 1 and the monthly signal Sm at the high logic level, the AND gate 26 will allow the number of pulses of the catch-up signal S13 to pass necessary to quickly position the date on the first of the month.
- the drive circuit 28 produces at its output the control signal S25 as soon as a signal appears at the output of the gate OU27.
- the duration of the latter signal therefore does not influence the control signal.
- the control signal S25 may contain only a single pulse causing the motor 23 to rotate by one step.
- it is advantageous to move the date by causing the motor N not to respond to a control signal S25 formed by a series of N consecutive pulses. The triggering of a pulse of a series automatically causes the appearance of other im impulses of the series, so that the date can only move in whole days.
- the control circuit 25 can also be designed so that it generates the control signal S25, advancing the date of the number of days required at the end of a month by less than 31 days, from the information provided by the Smc and Sab signals, in place of those provided by the Sz signal.
- An embodiment of such a circuit is described, for example, in the cited document. Contact Z then becomes useless.
- this solution has the drawback of not allowing the date 20 to be synchronized, in the event of the latter malfunctioning, with the content of the counter 31 the first of each month.
- the circuits of the watch described are supplied with energy by a battery, not shown. After the initial setting of the watch to the time and date, it will continue to correctly indicate the time as long as the battery voltage remains above a critical threshold.
- the watch also comprises a first transmission circuit 40, a reprogrammable non-volatile memory 41, also called EEPROM, which keeps its content even in the absence of the supply voltage, a second transmission circuit 42, a voltage detection circuit 43, and an initialization circuit 100.
- a reprogrammable non-volatile memory 41 also called EEPROM
- Transmission circuits can, for example, be produced using transmission doors which are electronic components known per se, while non-volatile memory, with its interface circuits allowing the recording and reading of information, can advantageously be of FAMOS type also known per se.
- the use of such a memory in watchmaking is known and, for example, patent CH 534913 describes a logic circuit for frequency correction where the content of the non-volatile memory determines the running of a watch. It should however be noted that the surface occupied by a non-volatile memory with its interface elements on a watchmaking circuit is appreciable, that its consumption during writing and reading is not negligible and, above all, that the duration of the memorization decreases rapidly with the number of registrations and readings.
- the purpose of the non-volatile memory in the present invention is to save the content of the counters of the calendar circuit 30 after the battery has been exhausted.
- the most advantageous solution would be to transfer into this memory the content of the day counter 31 at the end of each day, the content of the month counter 32 at the end of each month and the content of the year counter 33 at the end of each year.
- the part of the non-volatile memory connected to the day counter would then work at too high a frequency to guarantee a sufficient lifetime of the watch.
- the purpose of the first transmission circuit 40 is to transfer the content of the counters 32 and 33 of the calendar circuit 30 into the non-volatile memory 41 in response to a transfer signal.
- the circuit 40 includes a first series of 4 transmission doors referenced 45. These doors are connected, on the one hand, to the output of the counter 32 to receive the 4-bit signal S32 and, on the other hand, at the entry of a first section 48 of 4 bits of the memory 41. These gates are controlled by the transfer signal which, in this case, is the monthly signal Sm.
- the second transmission circuit 42 has the same structure as the circuit 40. It thus also includes a first series of 4 transmission doors referenced 51. These doors are connected, on the one hand, to the output of section 48 of the memory 41 to receive the signal S32 and, on the other hand, to the input E of the counter 32.
- the circuit 43 which is a monostable flip-flop known per se, supplies a detection signal S43 indicating that the voltage across the terminals of the circuits is again at least equal to the critical threshold. This signal is taken as transfer signal for the second transmission circuit 42. So, at this instant, while the state of the counter 32 is undefined, this counter receives on its input E the signal S32 which existed at the time of the watch stopped on date D A.
- the circuit 40 also comprises a second series of 2 transmission doors 46 used to transmit, at the end of each year in response to the signal Sa, the content of the counter 33 in a second section 49 of 2 bits of the memory 41.
- the circuit 42 also comprises a second series of 2 transmission doors 52 connected, on the one hand, to the output of the section 49 and, on the other hand, to the input E of the counter 33, the signal S43 being taken as signal of transfer for these doors as for doors 51.
- the month counter 32 and the year counter 33 are reset, by the signal S43 and using the circuit 42, in the state they had when the watch stopped on the date DA, while the day counter 31 takes an undefined state.
- the date 20 keeps, of course, the position it had at date A.
- the day counter 31 In order for the watch calendar to show the correct date again, after replacing the battery, the day counter 31 must first be aligned with the date display 20, then the counter 31 and the display 20 manually set to the date of the date D R.
- the matching of the counter 31 with the display 20 is obtained automatically using the initialization circuit 100 after replacing the battery.
- This circuit also determines whether the new battery was inserted in the same month or the month following the stop of the watch and, in the latter case, increments the counter 32 by one unit so that its content corresponds to the correct month.
- the initialization circuit 100 by resetting the day counter 31 with the date display 20, plays a role analogous to that of an additional 5-bit section which the non-volatile memory 41 would have, and which, using transmission doors, would memorize the content of counter 31 when the watch stopped and transfer this information to this counter after changing the battery.
- Circuit 100 made up of conventional logic circuits, has the advantage over a 5-bit non-volatile memory of taking up less space, consuming less energy, and having no limitation in terms of service life. .
- the initialization circuit 100 does not intervene in the operation of the watch until the battery is replaced, the rest of the time it is in a waiting state.
- This circuit includes an ET105 gate with two inputs, an OU118 gate with two inputs, a sequential circuit 119 producing logic control signals, and a discrimination circuit 120 which produces a discrimination signal S120 when the battery is replaced within one month. follows the watch stop.
- An input of the gate ET1 05 is connected to the output of the day counter 31 to receive the monthly signal Sm.
- the output of this gate is connected to an input of the gate OU118 whose output is connected to the counting input of the month counter 32.
- the other input of the gate ET105 receives from the circuit 119 the logic signal S102, and l 'other input of the gate OU118 a discrimination signal S120 of the circuit 120.
- the signal S102 is also applied to the other input of the gate ET104.
- the signal S102 is at the high logic level and the signal S120 at the low logic level. It follows that in this case the signal Sm passes through the gates 105 and 118 from the output of the counter 31 to the input of the counter 32, and the output signal of the divider 13 at the input of the driving circuit 14 through door 104, as previously assumed.
- the sequential circuit 119 contains a flip-flop RS101 whose input S for setting to the state is connected to the output of the circuit 43 to receive the detection signal S43, and the input R for resetting to zero is connected to the contact Z through an inverter 110 to receive a signal Sz, inverse of the date signal Sz.
- the output Q of the flip-flop 101 delivers a signal S101 which is applied to an input of a gate ET107 with two inputs, the other input of this door receiving the fast forward signal S13.
- the output of the gate ET107 delivers a signal S107 which is applied to the other input of the gate OU108 whose output, which delivers a signal S108, is connected to the input of the counter 31.
- the signal S101 is still applied to the another entry of the door OU106 and on the entry of a rocker rocker 111 responding to a falling edge of this signal.
- the output of circuit 111 is connected to an input of an OR gate 103 with two inputs through a delay circuit produced, for example, using two inverters connected in series referenced 112a and 112.
- the other input of gate OU103 receives the detection signal S43.
- the output of this door provides a signal S103 which is applied to an input of the day counter 31 allowing the content of this counter to be reset to 1.
- the circuit 119 comprises yet another flip-flop RS, referenced 102, the input S of which is connected to the output of the circuit 43 and the input R of the output of a monostable flip-flop 114.
- the positioning signal Sy is applied to the input of flip-flop 114 which responds to a rising edge of this signal.
- a gate ET116 with two inputs, having an input connected to the direct output Q of the flip-flop 102 and the other input to the output of the flip-flop 114, supplies at its output a signal S116. Finally the reverse output Q of the flip-flop 102 provides the signal S102 which has already been mentioned.
- the discrimination circuit 120 on its side, contains a memory register 109 which receives on an input the signal S31 and, on a clock input C K , the signal S101.
- the register stores the number representative of the content of the counter 31 at this time.
- the output of register 109 is connected to the input of a subtractor 113 which supplies a signal S113 representative of the difference between the number 33 and the number stored by the register.
- the signal S113 is applied to an input A of a comparator 115 with two inputs, the other input B receiving the signal S31.
- the compartment delivers a signal S115 which is at the low logic level when the number corresponding to the signal S113 is lower or equal to the number corresponding to signal S31, and to the high logic level otherwise.
- the circuit 120 also includes a gate ET117 with two inputs which receives the signals S115 and S116 and supplies the discrimination signal S120 to an input of the gate OU118.
- the display 20 After stopping the watch on date D A, the display 20 continues to indicate the date of this date and the non-volatile memory 41 to contain information relating to the month and to the year. The content of the day counter 31 is however permanently lost.
- the essential purpose of the initialization circuit 120 is to reset the counter 31 to the display 20 after replacing the battery on the date D R.
- the operation of this circuit is as follows.
- the circuit 43 Just after the installation of the new battery, the crown being in neutral position 16, the circuit 43 produces the detection signal S43 which contains a brief pulse.
- This signal by activating the transmission circuit 42, transfers the information relating to the month and the year from the non-volatile memory 41 into the counters for months 32 and years 33 which are thus restored to the state. where they were on date D A.
- the signal S43 passing through the gate OU103, also resets the day counter 31 to 1 for the first time. Finally, this signal sets flip-flops 101 and 102, state in which the Q outputs are at the high logic level.
- the high logic level of the signal S101 resulting from the setting of the flip-flop state 101, is found at the output of the gate OU106 and opens the gate ET26 to the signal S13 provided that the signal Sz is also at the logic level high , which occurs if the date 20 does not indicate the first of a month.
- This state of signal S101 also opens gate ET107 to signal S13 and register 109 to signal S31.
- the signal S102 is on the other hand at the low logic level, which has the effect of blocking the time base signal S1 by closing the gate ET104 at the output signal of the divider 13, and of preventing the signal Sm from reaching the input of counter 32 by blocking door ET105.
- the motor 2 and the counter 32 receive no signal while the signal S13, passing through the gates ET26 and OU27, activates the motor 23 so that the display 20 advances by N not, from the position corresponding to the DA stop date up to position 1 in which contact Z, when opening, switches signal Sz from high logic level to low logic level.
- the passage to the low logic level of the signal Sz, at the time of the opening of the contact Z, has the effect of stopping the passage of the signal S13 through the gate ET26 and of blocking the display 20 in the position where it indicates 1
- the signal Sz by crossing the inverter 110, also resets the flip-flop 101 to zero, which brings the signal S101 from the high logic level to the low logic level.
- This transition of the signal S101 causes the signal S13 to be blocked by the gate ET107, the storage of the value 1 + N in the register 109, the input Ck of which goes to the low logic level, and the production of a signal containing a brief pulse by the monostable flip-flop 111.
- This signal is however sufficiently delayed by the inverters 112a and 112b for the resetting of the counter to 1 after the storage of its 1 + N content in the register 109.
- the quantity 1 + N is transmitted to the input of the subtractor 113 which calculates the number 32-N corresponding to the date of the stop date DA of the watch.
- the signal S113 supplied by the subtractor, representative of the date thus calculated, is applied to the input A of the comparator 115.
- the crown After replacing the battery, the crown must be moved from the neutral position 16 to the correction position 16 '. This manipulation leads to the opening of the contact Y and the passage of the signal Sy from the high logic level to the low logic level. This has the effect of blocking the gate ET12 to the signal from the oscillator 10 and of resetting the last stages of the frequency divider 13.
- the watch must then be set to the date D R. This is obtained by turning the crown so as to activate the contact X which supplies the signal Sx, signal formed by a series of pulses. Each pulse, passing through door OU27, advances the display 20 by one day and, passing through door OU108, increments the day counter 31 by one unit. The display 20 and the counter 31 therefore remain in agreement. Contact X must be activated the number of times necessary for the display 20 to change from position 1 to the position corresponding to the date of the date D R. The content of the counter 31 then also corresponds to this date and this information is transmitted by the signal S31 on the input B of the comparator 115.
- the watch having been set to the time and date, it only remains to push the crown from the correction position 16 'into the neutral position 16.
- This manipulation passes the signal Sy from the low logic level to the high logic level.
- the high level of Sy opens the gate ET12 to the signal from the oscillator 10, and activates the monostable flip-flop 114 which, by producing a pulse on the input R of flip-flop 102, resets that -this to zero.
- a brief pulse is produced at the input of gate ET116 while the input R of flip-flop 102 is at the high logic level and its output Q not yet at the low logic level.
- This pulse passes through the gate ET117, to increment the counter 32 by one unit and set it to the correct month, only when the signal S115 is found at the high logic level, that is to say that the battery has been replaced. within a month of stopping the watch.
- the reset of the flip-flop 102 also causes the signal S102 to go from the low logic level to the high logic level. This has the effect, on the one hand, of opening the gate ET104 to the signal coming from the frequency divider 13, allowing the timekeeping circuit 1 to supply the time base signal S1, and, on the other hand, open door ET105 to the monthly signal Sm from counter 31.
- the watch which has just been described may advantageously comprise, in addition, a time zone device with magnetic positioning, known per se.
- the crown 16 must then be able to occupy a second correction position, not shown, in which it acts on part of the first gear train to move, by whole hours, only the hour hand and activate the contact X at each passage. of the hour hand by midnight.
- the date 20 is then moved an entire day and the counter 31 incremented by one.
- the Y contact remains closed, so that the watch continues to operate normally.
- the time zone device also makes it possible, after a battery change, to set the watch to the date much faster than using conventional time setting. If the watch includes a time zone device making it possible to move the hour hand in both directions, the second motor 23 would advantageously also be of the type with two directions of rotation, or bidirectional.
- the control mechanism 3 should then include means, not shown but known per se, for example contacts, associated with a circuit, and providing a logic signal for discriminating the direction of rotation of the crown on an input not shown of the circuit 28 , and on an input not shown of the counters 31, 32 and 33.
- this signal would correspond a rotation in front of the motor, advancing the date, and the incrementation of the counters, while at the other level logic would correspond to a backward rotation of the motor and the decrementation of the counters.
- the indication of the display 20 would remain, under these conditions, always in accordance with the content of the counter 31 to indicate the exact date, whatever the direction of rotation of the hour hand at the time of contact activation.
- X in response to the rotation of the crown 16 while it is in a correction position.
- the time setting of the watch instead of being mechanical, could be done electronically by signals produced by a time setting circuit, not shown but known per se, activating the first motor 2 in response to a rotation of the crown 16. To make this maneuver easier, it would be advantageous if the motor 2 was also of the bidirectional type.
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Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CH4122/86 | 1986-10-15 | ||
CH412286A CH665077GA3 (de) | 1986-10-15 | 1986-10-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0267440A1 EP0267440A1 (de) | 1988-05-18 |
EP0267440B1 true EP0267440B1 (de) | 1990-02-07 |
Family
ID=4270232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP87114859A Expired - Lifetime EP0267440B1 (de) | 1986-10-15 | 1987-10-12 | Analog-Uhr mit zwei Motoren, die einen ewigen Tageszähler enthält |
Country Status (7)
Country | Link |
---|---|
US (1) | US4775963A (de) |
EP (1) | EP0267440B1 (de) |
JP (1) | JPS63109390A (de) |
CH (1) | CH665077GA3 (de) |
DE (1) | DE3761713D1 (de) |
HK (1) | HK32093A (de) |
SG (1) | SG132092G (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5289452A (en) * | 1988-06-17 | 1994-02-22 | Seiko Epson Corporation | Multifunction electronic analog timepiece |
JP3019324B2 (ja) * | 1988-06-17 | 2000-03-13 | セイコーエプソン株式会社 | アナログ電子時計用ic及びアナログ電子時計 |
CH681677B5 (fr) * | 1991-02-05 | 1993-11-15 | Complications Sa | Procédé d'initialisation du calendrier perpétuel d'un chronographe analogique à quartz et chronographe à quartz pour sa mise en oeuvre. |
JPH0618680A (ja) * | 1992-07-02 | 1994-01-28 | Sony Corp | 時計装置 |
DE19861413B3 (de) * | 1997-12-26 | 2012-06-14 | Citizen Holdings Co., Ltd. | Elektronische Uhr mit einer Vorrichtung zum Einstellen von Kalenderdaten am Monatsende |
JP2900154B1 (ja) * | 1998-02-12 | 1999-06-02 | セイコーインスツルメンツ株式会社 | オートカレンダ付電子時計 |
EP2884349B1 (de) * | 2013-12-13 | 2020-07-01 | ETA SA Manufacture Horlogère Suisse | Verfahren zur Steuerung einer Analoganzeige, die in einem Uhrwerk eingebaut ist |
CN108333915B (zh) * | 2018-03-30 | 2023-05-23 | 宗仁科技(平潭)有限公司 | 时间信号赋值电路、减法计数器以及倒计时装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH534913A (fr) * | 1970-02-17 | 1972-08-15 | Centre Electron Horloger | Garde-temps |
JPS6013153B2 (ja) * | 1976-12-03 | 1985-04-05 | シチズン時計株式会社 | カレンダ−付電子時計 |
JPS5370866A (en) * | 1976-12-07 | 1978-06-23 | Seiko Instr & Electronics Ltd | Electronic watch |
CH613837B (fr) * | 1977-06-14 | Suisse Horlogerie | Montre electronique a affichage mecanique. | |
JPS5845589A (ja) * | 1981-09-11 | 1983-03-16 | Chino Works Ltd | 停電時の時計機能補償回路 |
DE3247910A1 (de) * | 1982-12-24 | 1984-06-28 | SWF-Spezialfabrik für Autozubehör Gustav Rau GmbH, 7120 Bietigheim-Bissingen | Schaltanordnung zur datenspeicherung in kraftfahrzeugen |
CH661833GA3 (de) * | 1985-12-18 | 1987-08-31 |
-
1986
- 1986-10-15 CH CH412286A patent/CH665077GA3/fr not_active IP Right Cessation
-
1987
- 1987-10-01 US US07/103,249 patent/US4775963A/en not_active Expired - Lifetime
- 1987-10-12 DE DE8787114859T patent/DE3761713D1/de not_active Expired - Lifetime
- 1987-10-12 EP EP87114859A patent/EP0267440B1/de not_active Expired - Lifetime
- 1987-10-15 JP JP62258494A patent/JPS63109390A/ja active Granted
-
1992
- 1992-12-26 SG SG1320/92A patent/SG132092G/en unknown
-
1993
- 1993-04-01 HK HK320/93A patent/HK32093A/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
HK32093A (en) | 1993-04-08 |
CH665077GA3 (de) | 1988-04-29 |
JPS63109390A (ja) | 1988-05-14 |
EP0267440A1 (de) | 1988-05-18 |
US4775963A (en) | 1988-10-04 |
SG132092G (en) | 1993-03-12 |
JPH0463351B2 (de) | 1992-10-09 |
DE3761713D1 (de) | 1990-03-15 |
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