EP0143279B1 - Watch with analogous and numerical display - Google Patents

Abstract

The invention provides an electronic watch having an analog display with time indicating hands, a digital display and control means including a crown adapted to act on contacts arranged so as to provide signals representing rotary and axial displacements of said crown to an electronic selection and correction circuit. Responding to movements of the crown, the electronic circuit determines the operating mode of the watch and modifies the indications given by the displays. In a special synchronizing mode the two displays are set to indicate the same information and the analog form thereof may be adjusted to coincide with the digital form.

Description

The present invention relates to electronic watches having an analog display and a digital display and provided with means for synchronizing the two displays when they indicate the same time information.

The simultaneous use of an analog display by hands, or by discs, and a digital display in a watch has rapidly spread in recent years. This type of watch has the advantage of providing an easy and conventional time reading with the hands and allowing access to many auxiliary functions, such as day, date, alarm time, time zones, timed hours, etc. on the digital display.

For certain functions, the information on the two displays is different and independent, such as the time read on the analog display and a timed time indicated by the digital display. For other functions, the two displays can indicate the same information or information depending on one another. For example, the day and date read on the digital display must be related to the time of the analog display so that the calendar can change state when the hands indicate midnight. Among the various functions of the watch, a function must thus make it possible to read and correct the time indicated by the hands independently of the time indicated by the digital display or vice versa. Even if this information is not explicitly used, it is necessary for the calendar function as well as, for example, for the time zone function.

When the same information is indicated on the two displays, the time for example, there must therefore be means of synchronization or phasing, making it possible to show, in this type of watch, the same time on the display analog and digital display. It is an initialization operation that must be repeated after each battery change.

Two versions of watches provided with an analog display and a digital display are, for example, described in patent US-A-4 246 602. In the first version the analog display is mechanically corrected by a crown, independently of digital display which continues to receive time signals. This procedure has at least the disadvantages of being imprecise, because of the play of gears, of requiring a bulky and expensive mechanism and of not allowing the crown to have other functions than that described. In the second version, the analog display is stopped using a switch and the digital display is corrected using contacts until there is coincidence between the two indications . The watch in this case no longer has a crown. Exact synchronization can be achieved with an analog hour display, minutes advancing by full minutes. On the other hand, if the minute hand moves by fraction of a minute, as happens in general, the accuracy of synchronization cannot be guaranteed, and we come back to the first drawback of the previous version.

Patent application GB-A-2,019,052, for its part, describes a watch with mixed analog-digital display provided with a crown making it possible to electronically correct, forwards and backwards, the two displays by leaps of whole minutes. This is an interesting solution because it is close to the usual well accepted command used in mechanical watches. However, the watch described has the disadvantage of requiring, next to the crown, other control members and of lacking means making it possible to synchronize the two displays.

Finally, a watch comprising analog and digital displays receiving minute signals from the same time base is further described in your patent application GB-A-2 042 773. A crown allows this correction mode to be selected in this watch giving three the possibility, either to modify each display separately in steps of whole minutes using a button, and therefore to synchronize it, or to set the time of the two displays simultaneously by correcting them by the same number of minutes. In this embodiment also, on the one hand, the crown does not fulfill its usual function and, on the other hand, synchronization between the displays can only be obtained if the analog display moves by whole minutes.

• - une base de temps pour produire un signal de fréquence standard;
• - un circuit pour diviser la fréquence du signal de fréquence standard;
• - des organes indicateurs pour afficher un premier groupe d'informations de temps sous forme analogique, un de ces organes affichant la minute courante;
• - un moteur pas à pas couplé mécaniquement aux organes indicateurs;
• - un circuit de commande pour appliquer des impulsions motrices au moteur et entraîner le déplacement des organes indicateurs en réponse à des impulsions de temps fournies par le circuit diviseur de fréquence et à des impulsions de correction;
• - un circuit de comptage recevant également des impulsions de temps du circuit diviseur de fréquence pour fournir des signaux représentatifs d'un second groupe d'informations de temps, l'une au moins des informations de ce second groupe faisant également partie du premier groupe;
• - un dispositif d'affichage électro-optique relié au circuit de comptage pour afficher les informations du second groupe sous forme numérique;
• - des moyens de commande manuelle; et
• - un circuit logique de sélection et de correction répondant à l'actionnement des moyens de commande manuelle pour placer la montre dans différents modes d'affichage pour chacun desquels une information de temps choisie est affichée par le dispositif d'affichage électro-optique, dans différents modes de correction pour chacun desquels une information affichée sous forme numérique peut être corrigée grâce à l'application par le circuit logique d'impulsions de correction au circuit de comptage, ce circuit logique appliquant également des impulsions de correction au circuit de commande du moteur lorsque l'information corrigée est celle qui est commune aux deux groupes, cette information commune étant l'indication des minutes courantes et l'organe indicateur des minutes avançant normalement de n pas par minutes, n étant strictement supérieur à 1, de manière à modifier d'une même quantité l'indication sous forme analogique et l'indication sous forme numérique de cette information, et dans un mode supplémentaire de synchronisation dans lequel l'information commune est affichée par le dispositif d'affichage électro-optique numérique et dans lequel le circuit logique répond à un actionnement des moyens de commande manuelle en appliquant des impulsions de correction seulement au circuit de commande du moteur pour permettre d'amener l'indication sous forme analogique en concordance avec l'indication sous forme numérique de cette information, est principalement remarquable par le fait que le circuit de commande du moteur est conçu pour amener l'organe indicateur des minutes automatiquement sur une minute entière lors du passage en mode de synchronisation et pour, dans ce mode, produire et appliquer au moteur n impulsions motrices successives, en réponse à chaque impulsion de correction que le circuit de commande reçoit du circuit logique.

To avoid these drawbacks, the electronic watch according to the invention comprising:

• - a time base for producing a standard frequency signal;
• - a circuit for dividing the frequency of the standard frequency signal;
• - indicator members for displaying a first group of time information in analog form, one of these members displaying the current minute;
• - a stepping motor mechanically coupled to the indicator members;
• a control circuit for applying driving pulses to the motor and driving the displacement of the indicator members in response to time pulses supplied by the frequency divider circuit and to correction pulses;
• a counting circuit also receiving time pulses from the frequency divider circuit to supply signals representative of a second group of time information, at least one of the information of this second group also forming part of the first group;
• - an electro-optical display device connected to the counting circuit for displaying the information of the second group in digital form;
• - manual control means; and
• a logic selection and correction circuit responding to the actuation of the manual control means for placing the watch in different display modes for each of which a selected time information is displayed by the electro-optical display device, in different correction modes for each of which information displayed in digital form can be corrected by the application by the logic circuit of correction pulses to the counting circuit, this logic circuit also applying correction pulses to the motor control circuit when the corrected information is that which is common to the two groups, this common information being the indication of the current minutes and the indicator body of the minutes advancing normally by n not by minutes, n being strictly greater than 1, so as to modify of the same quantity the indication in analog form and the indication in digital form of this information, and in u n additional synchronization mode in which the common information is displayed by the digital electro-optical display device and in which the logic circuit responds to an actuation of the manual control means by applying correction pulses only to the control circuit of the motor to allow the indication in analog form to be brought into line with the indication in digital form of this information, is mainly remarkable by the fact that the engine control circuit is designed to bring the minute indicator member automatically to a full minute during the transition to synchronization mode and to, in this mode, produce and apply to the motor n successive driving pulses, in response to each correction pulse that the control circuit receives from the logic circuit.

It is clear that, more often than not, a watch according to the invention will include at least one indicator for the current minutes and one for the current hours, these two pieces of information can also be displayed in digital form, and that synchronization can be carried out. at least for the indication of the minutes.

Furthermore, the watch will preferably be provided with a bidirectional stepping motor and counting means capable of counting and counting down in order to allow modification of the time information of the two groups in both directions.

• - la figure 1 représente une vue d'une montre pourvue d'un affichage analogique à aiguilles, d'un affichage numérique et d'une couronne de commande;
• - les figures 2a et 2b montrent en plan et en bout un exemple de mécanisme actionnant des contacts de détection des mouvements de la couronne;
• - la figure 3 est un diagramme montrant les différents modes de fonctionnement de la montre;
• - la figure 4 représente un exemple de schéma bloc du circuit de la montre;
• - la figure 5 représente un exemple de circuit codeur de mouvements commandé par les contacts de détection, fournissant à sa sortie des signaux représentatifs des mouvements de la couronne;
• - la figure 6 représente un exemple de circuit sélecteur de mode fournissant à sa sortie des signaux représentatifs des divers modes de fonctionnement de la montre en réponse aux signaux représentatifs des mouvements de la couronne;
• - la figure 7 représente un exemple de circuit de commande d'un moteur pas-à-pas biphasé à deux sens de rotation;
• - la figure 8 représente un exemple de circuit de comptage;
• - la figure 9 représente un exemple de circuit sélecteur d'affichages; enfin
• - les figures 10a et 10b donnent un exemple de circuits d'aiguillage utilisés dans le circuit sélecteur.

Other characteristics and advantages will appear during the description which follows of an exemplary embodiment of the invention, with reference to the appended drawing. On this drawing:

• - Figure 1 shows a view of a watch provided with an analog display with hands, a digital display and a control crown;
• - Figures 2a and 2b show in plan and at the end an example of a mechanism actuating contacts for detecting movements of the crown;
• - Figure 3 is a diagram showing the different modes of operation of the watch;
• - Figure 4 shows an example of a block diagram of the watch circuit;
• - Figure 5 shows an example of a motion encoder circuit controlled by the detection contacts, providing at its output signals representative of the movements of the crown;
• - Figure 6 shows an example of a mode selector circuit providing at its output signals representative of the various operating modes of the watch in response to signals representative of the movements of the crown;
• - Figure 7 shows an example of a control circuit of a two-phase stepper motor with two directions of rotation;
• - Figure 8 shows an example of counting circuit;
• - Figure 9 shows an example of display selector circuit; finally
• - Figures 10a and 10b give an example of switching circuits used in the selector circuit.

In Figure 1 is shown an example of watch 1 according to the present invention. This watch includes an analog display with two hands 2, a digital display 3 with four characters and a control crown 4 which can move according to two degrees of freedom.

One of the hands 2 on the analog display indicates the hours and the other the timers. The minute hand advances by fraction of a minute. To simplify the description, we will assume that it jumps every 30 seconds, the generalization to other cases being obvious. The time setting of the analog display 2 is done electronically by the crown 4, forwards or backwards, thanks to the use of a motor which can rotate in both directions.

The digital display 3 indicates, in the example given, either the day and the date, or the hours and the minutes, or else it indicates nothing by remaining white in a synchronization position, but the present invention is not limited not just these functions. The two characters on the left of display 3 are provided to display the numbers and letters necessary to indicate the days of the week. The two characters on the right only display numbers. The selection of the operating modes of the watch and the corrections of the digital display 3, forwards and backwards, are also made using the crown 4.

The two positions and the two degrees of freedom of the crown 4 are shown in Figure 1. The reference 4 'shows the crown in its normal or pushed axial position. A pull on the crown puts it in the pulled position 4 "Position 4" is not stable because a return spring tends to permanently return the crown to its normal position 4 '. Whatever the axial position of the crown, it can be rotated in both directions around an axis 6. The rotation corresponds to the first degree of freedom and the traction to the second degree of freedom of the crown. These two degrees of freedom are represented respectively by the symbols 5 and 5 'in FIG. 1.

The crown 4 controls a mechanism, shown in plan in FIG. 2a and at the end, from the plane AA ′, in FIG. 2b. This mechanism operates contacts for detecting movements of the crown. We distinguish in Figures 2a, 2b the crown 4, fixed to one end of the axis 6. This axis passes through the wall 10 of a watch case, which is connected to an electrical ground point 21. On the axis 6 are wedged two insulating cams 12 and 13 of elongated shape, for example elliptical. The major axes of the ellipses form an angle of about 45 ° between them. At the other end of the axis 6 is a metal disc 14. In the pulled position 4 "from the crown, the cams 12, 13 and the disc 14 occupy positions 12 ', 13' and 14 'respectively. contact blades, referenced 17, 18 and 19, are fixed by one of their ends to a metal plate 15, electrically connected to the ground point 21 and integral with the watch case. The blades 17 and 18 can each move in a plane perpendicular to the axis 6 and the blade 19 in a plane parallel to the same axis. The rotation of the elongated cams 12 and 13 by the crown 4 makes it possible to move the blades 17 and 18. The cams also have a width sufficient for them to act in the same way in the pulled or pushed position of the crown. The blade 19 is armed so as to come to press permanently on the disc 14, by putting it to electrical ground, and to exert on the axis 6 a restoring force tending to maintain the crown 4 in its normal or pushed position e 4 '. Three conductive reference plates 22, 23 and 24 are fixed on an insulating plate 16, integral with the watch case. In the rest position, or not deformed, the contact blades 17, 18 come to touch the other ends respectively of the plates 22 and 23. A blade and the corresponding plate therefore form a contact, which will bear the reference of the blade. The rotation of the cams 12 and 13, causing the blades to move, has the consequence of opening and closing the contacts 17 and 18. For a 360 ° rotation of the crown 4, each contact works twice. The angular offset different from 90 ° existing between the cams 12 and 13 has the effect of introducing a phase shift in the operation of the contacts 17 and 18. This phase shift is different depending on the direction of rotation of the cams, therefore of the crown 4. It thus constitutes a parameter representative of the first degree of freedom of this crown. The working frequency of the contacts 17 and 18 makes it possible to measure the speed of rotation of the crown, the angle of rotation of which is determined by the number of contact closings.

On the metal plate 24 is fixed a blade 20 which can move in the same plane as the blade 19. In the pushed position 4 ′ of the crown, the blade 20 remains free. In the pulled-out position 4 'from the crown, the disc 14 comes into position 14'. It then drives the blades 19 and 20 respectively in positions 19 'and 20'. In this position of the crown, the disc 14 therefore touches the blade 20. The assembly constitutes a contact which will be designated by the reference 20. The state of this contact therefore constitutes a parameter representative of the second degree of freedom of the crown 4.

The functions that a watch may indicate and the possibilities for correcting the information displayed define the operating modes of the watch. The transition from one mode to another is obtained using the control elements of the watch.

FIG. 3 represents the different modes in which the watch taken as an example can be found. In this figure, the rectangles indicate the information appearing on the digital display and the circles symbolize the commands. A line XX 'divides Figure 3 in two. On the left part of this figure are grouped the functions F ₁ , F ₂ and F ₃ of the watch and on the right part the corrections C ₁ , C ₂ , C ₃ and C ₄ . A square, symbolizing the analog display, also appears in the corrections that influence it. The watch can therefore be found in seven different modes. F ₁ corresponds to the calendar function, the day D appearing on the two characters on the left and the date D on the two digits on the right of the digital display 3. F ₂ corresponds to the time function, the hours H being displayed on the left and the minutes M on the right. Finally in F ₃ is the synchronization function of the analog display on the digital display. In this mode and in the example chosen, the digital display does not indicate any information to highlight the analog display. The passage from one function to another is done, for reasons of simplicity of the circuits, in a given order by turning the crown 4 in one direction or the other, but the order of scrolling of the functions could obviously depend on the direction of rotation of the crown.

The transition from a function to the corresponding correction mode is done by pulling on the crown 4 followed by a relaxation, as shown in FIG. 3. This maneuver thus makes it possible to pass from the function F ₁ in correction mode C ₁ . In this mode only the two characters on the left appear indicating a day of the week. A rotation of the crown allows you to change the day of the week by scrolling the days one after the other. The order of day scrolling depends on the direction of rotation of the crown to allow rapid correction. The transition from mode C ₁ to the following correction mode C ₂ is also carried out using a pull on the crown. Only the two figures on the right then appear, indicating the date which can be corrected by rotating the crown 4. Depending on the direction of rotation of the crown, the number corresponding to the date can be increased or decreased. Finally, the next pull on the crown returns the watch to its starting mode F _j . Similarly, starting from function F _2, we go to correction mode C ₃ in which the digital display 3 simultaneously indicates hours H and minutes M. To distinguish mode F ₂ from mode C _3, we can, for example example, synchronize the hours and minutes in synchronization mode by known means. The hourly pulses are blocked in mode C ₃ and the seconds counter of the watch circuit is reset to zero. The rotation of the crown 4 then makes it possible to correct the hour and minute hour indication by jumps of whole minutes, simultaneously on the digital 3 and analog 2 displays, of the same value. Depending on the direction of rotation of the crown, the correction corresponds to an advance or a delay of the watch. An exact time setting can thus be made in mode C ₃ since the watch is stopped for one round minute. If the two displays do not show the same time, for example after a battery change, the digital display 3 must be set to the correct time. The return to the function F ₂ is finally obtained by pulling on the crown 4.

At this stage, the digital display 3 is at the exact time but the analog display 2 can possibly deviate from it by an integer number of minutes. In this case it is necessary to pass to the synchronization function F ₃ then by a pull on the crown 4, in the correction mode C ₄ . In this mode the time pulses are not blocked, but they only control the digital display 3 which continues to indicate the exact time H, M, while the hands 2 of the analog display remain stationary. To distinguish modes F ₂ , C ₃ from mode C ₄ , all these modes indicating the hours and minutes, it is possible, for example, to flash H and M alternately in mode C ₄ by known means. In mode C ₄ the rotation of the crown 4, in one direction or the other, has the effect of advancing or retreating the hands 2 by jumps of whole minutes, the number of jumps being proportional to the angle of rotation . This maneuver allows the two displays to be synchronized or in phase by making them indicate the same time information. A pull on the crown 4 then returns the watch to the mode F ₃ then a rotation of the crown makes it possible to pass to the normal operating mode F _j . To simplify handling, the return to the function F ₁ could also take place automatically after a certain delay, for example 16 seconds, after the last intervention in any correction mode.

The block diagram of a watch according to the invention is shown in FIG. 4. The blocks drawn in solid lines in this figure represent known circuits and those drawn in dotted lines of circuits having specific functions, necessary for the present invention. These latter circuits will be described in detail later in this request. All circuits are supplied from a battery, not shown.

The diagram in FIG. 4 comprises an encoder circuit 30 for the movements of the crown 4. A first and a second input of the circuit 30 respectively receive the signals coming from the contacts 17 and 18, represented in FIGS. 2a and 2b. These signals are used to define the direction of rotation of the crown. The signal generated by the contact 20 in FIGS. 2, in response to a pull on the crown 4, is applied to a third input of the circuit 30. This circuit produces, as a function of the input signals, output signals encoded CD, SC1, SC2 and ST, representative of the movements of the crown according to its two degrees of freedom. The signal CD is a logic signal which is at the low logic level for one direction of rotation of the crown and at the high logic level for the other direction of rotation. The signal SC1 contains a number of pulses proportional to the angle of rotation of the crown, whatever its direction of rotation. The signal SC2 is obtained from the signal SC1 by suppressing one pulse out of two. Finally, the signal ST contains an impulse for each pulling of the crown, the relaxation of the latter producing no effect.

The output signals SC2 and ST of circuit 30 drive the inputs of a mode selector circuit 31 providing at its output logic signals F ' ₁ , F' ₂ , F ' ₃ , C' ₁ , C ' ₂ , C' ₃ , C ' ₄ . These output signals make it possible to define seven different states corresponding to the seven modes in which the watch is likely to be found. A particular case of correspondence between the modes and the logical states of the signals is shown in table 32 of FIG. 4. We see that, in this example, each mode corresponds to a high logic level of an output signal, the other signals remaining at the low level. Mode F ₁ thus corresponds to a high logic level only of signal F ' ₁ , similarly to mode F ₂ corresponds to a high logic level of signal F' ₂ ... etc. and in mode C ₄ corresponds a high logic level of the signal C ' ₄ .

The circuits 30 and 31 form the selection part of the diagram in FIG. 4. The time part of this diagram comprises, for its part, a quartz oscillator 35, providing at its output a standard or reference signal of 32,768 Hz for example. This reference signal drives a first frequency divider 36 which delivers two output signals, the first of 8 Hz and the second of 1 Hz. An AND 37 gate with two inputs receives on its first input the signal of 1 Hz and delivers at its output a signal of 1 Hz also when the second input is at high logic level. The output signal from the AND gate 37 drives a second frequency divider or second counter 38 having a reset input R and two outputs, the first delivering a signal of 1/30 Hz and the second a signal of 1 / 60 Hz. These signals are formed by pulses, the first comprising two pulses per minute and the second one pulse per minute. The signal C ' ₃ of the circuit 31 is applied to the input R of the frequency divider 38 and to the input of an inverter 39, the output of which is connected to the second input of the AND gate 37.

When the watch is in the correction mode C ₃ , the signal C ' ₃ is at the high logic level. The output of the inverter 39 is then at the low logic level, which has the effect of blocking the AND gate 37 which no longer allows the 1 Hz signal from the frequency divider 36 to pass. The high logic level of the signal C ' ₃ also resets the frequency divider 38 to zero. The blocking of the 1 Hz signal and the resetting of the frequency divider 38 by the signal C ' ₃ makes it possible to set the watch to the time and to start it exactly at a time signal passing from mode C ₃ to mode F ₂ , in which the signal C ' ₃ is at the low logic level, by means of a pull on the crown 4.

The 1/30 Hz signal from the frequency divider 38 drives the first input of an AND gate 71 with two inputs. The second input of this door is connected to the output of an inverter 70 whose input is controlled by the signal C'4. When the watch is in correction mode C ₄ , the signal C ' ₄ being at the high logic level, this door blocks the signal 1/30 Hz.

The circuits 30, 31, 37, 39, 70 and 71 form a circuit referenced 200 which fulfills the functions of mode selection and correction of the information of the watch.

A motor control circuit 40, having seven inputs and three outputs, receives on its first input the signal of 1/30 Hz, coming from the AND gate 71, and on its second input the signal of 8 Hz, coming from the first divider of frequency 36. The following three inputs respectively receive the signals CD, SC1 and SC2, generated by the circuit 30. Finally, the last two inputs of the circuit 40 are attacked by the signals C ' ₃ and C' ₄ produced by the circuit 31. The signals 8 _t , B ₂ , B ₃ appearing on the outputs of the circuit 40, which will be described in detail below, attack the two coils of a two-phase bidirectional stepping motor 41. Of course by modifying the circuit in a known manner 40, it could just as easily attack a bidirectional single-phase motor. The motor 41 finally drives, via a gear (not shown), the hands 2 of the analog display of the watch. Each step of the motor 41 advances, in the example chosen, the hands 2 by 1/2 minute. It is obvious that another reduction ratio of the gear would make it possible to advance the hands by 1 / n minute with each jump of the motor, which would require attacking the first input of circuit 40 by a signal of frequency n / 60 Hz.

When the watch is in the modes F ₁ , F ₂ , F ₃ , C ₁ or C ₂ , each pulse of the signal of frequency 1/30 Hz turns the motor 41 of a step always in the direct direction, it that is to say by advancing the hands 2, whatever the level of the CD signal. In the correction mode C ₃ , the signal C ' ₃ being at the high logic level, the circuit 40 becomes sensitive to the signal CD and the motor turns in the direct or reverse direction depending on whether the signal CD is at the low or high logic level . In this correction mode the signal SC1 comes, in circuit 40, in place of the signal 1/30 Hz which is no longer present, the signal of 1 Hz being blocked by the AND gate 37. This makes it possible to advance or quickly move back the hands 2 in jumps of 1/2 minute by turning the crown 4 in one direction or the other. In the correction mode C _4, the signal C'4 is at the high level. This has the effect of blocking the 1/30 Hz signal via the AND gate 71 and of allowing circuit 40 to react only to the signal SC2. Each pulse of the signal SC2 triggers the generation, within the circuit 40, of a second pulse, causing the motor 41 to take two steps very close to each other so that the hands 2 give the impression of move in whole minutes, in one direction or in the opposite direction. Of course if each step of the motor advances the needles by 1 / n minute, the circuit 40 must generate, by means well known to those skilled in the art, n-1 additional pulses so as to move the hands by one minute. whole in a very short time.

After the description of the circuits associated with the analog display, we will now examine those associated with the digital display 3 comprising a first group of two alphanumeric characters, designated by X, and a second group of two digital characters, designated by Y.

Still referring to FIG. 4, it can be seen that the minute signal, that is to say from 1/60 Hz, coming from the second frequency divider 38, is applied to the first input of a front counting circuit. / rear 42 having 6 inputs and 4 outputs. The second input receives the signal CD, the logic level of which determines the counting mode of circuit 42, forward when the level is low and back when it is high. The correction signal SC2 is applied to the third input. Finally, the last three inputs, taken in ascending order of their numbering, respectively receive the signals C ' _l , C'y and C' ₃ .

The counting circuit 42, which will be described in detail below, comprises four counters, the first for the minutes, the second for the hours, the third for the days and the fourth for the date. In the modes F ₁ , F ₂ and F ₃ , the circuit 42 counts the minute pulses. The first counter then provides on the first output of the counting circuit 42 a multiple signal SM containing j binary signals whose logic states define a number between 0 and 59 corresponding to the number of minutes elapsed since the start of counting. Similarly, the second counter provides on the second output ur, multiple signal SH giving the number of hours and the third counter provides a multiple signal SJ on the third output giving a number corresponding to the day of the week. Finally the fourth counter produces on the fourth output a multiple signal SD giving the date.

In correction mode C ₁ the signal C 'is at the high logic level. This makes it possible to add or subtract, in the third counter of the circuit 42, a certain number of pulses produced by the correction signal SC2 in order to correct the day of the week. Similarly in mode C ₂ , the signal SC2 makes it possible to correct the date contained in the fourth counter. Finally in mode C ₃ the minute pulses being blocked, the correction signal is applied to the first input of circuit 42. This makes it possible to correct the hour and minute indication in steps of 1 minute contained in the first and second counters .

Since the information contained in the watch taken as an example cannot all be displayed simultaneously, a display selector circuit 43, shown in FIG. 4, is used to direct the information corresponding to each operating mode of the watch to display 3. .

Circuit 43 has ten inputs and two outputs. The first four inputs, taken in ascending order of their numbering, respectively receive the multiple signals SM, SH, SJ and SD of circuit 42. The next six inputs, also considered in ascending order, respectively receive the signals F ' ₁ , F ' ₂ , C' ₁ , C ' ₂ , C' ₃ and C ' ₄ of circuit 31. Circuit 43 provides a multiple signal x (J; H) on its first output and a multiple signal y (D; M) on its second output. Depending on the mode in which the watch is located, the signal x is identical to the multiple signal SJ or the multiple signal SH and the signal y to the multiple signal SH or the multiple signal SM. Thus, for example, in mode F ₁ the high logic level of the signal F ', means that the signal x corresponds to the signal SJ and the signal y to the signal SD. Similarly in the correction mode C ₃ , the signal x contains the information of the signal SH and the signal y that of the signal SM. In the mode F ₃ it should be noted that the circuit 43 not being controlled by the signal F ' ₃ , the signals x and y do not contain any information.

The signals x (J; H) and y (D; M) coming from the circuit 43 drive the inputs of a conventional decoder circuit 44 which in turn controls the digital display 3, for example with liquid crystal. The characters X display the information contained in the signal x and the characters Y those contained in the signal y.

The circuits and components appearing in the block diagram of FIG. 4 are of the conventional type and well known with the exception of circuits 30, 31, 40, 42 and 43. These latter circuits fulfilling functions related to the present invention, they will be now described in detail.

The diagram of the encoder circuit 30 is shown in FIG. 5. It includes a circuit 50 with two inputs and three outputs, an OR gate 51 with two inputs, a frequency divider by two 52 and a contact bounce circuit 53. The first input of circuit 50 receives the signal from contact 17 and the second input that of contact 18. The output S of circuit 50 provides the signal CD whose logic level depends on the direction of rotation of the crown 4. The output U of this circuit provides pulses when the crown rotates in a first direction, and no pulses when the crown rotates in a second direction, opposite to the first. Finally the output D provides pulses when the crown turns in the second direction and no pulses when it rotates in the first direction. The number of pulses is proportional to the angle of rotation of the crown.

A circuit fulfilling the functions of circuit 50 of FIG. 5 has been described, for example, in patent CH 632,894 or in the corresponding patent US 4,379,642. FIG. 3 of one of these documents gives the complete diagram of the circuit in which the inputs 15 and 16, provided with anti-rebound circuits of the contacts, the output of the AND gate 41, the output of the inverter 37 and the output of the inverter 38 correspond respectively to the first and to the second input, to the output S, to the output U and to the output D of the circuit 50 of the present application.

The outputs U and D of circuit 50 are connected respectively to the first and to the second input of the OR gate 51, which supplies at its output the correction signal SC1. The signal SC1 contains, when the circuit 50 is identical to that of the cited patent CH 632 894, a number of pulses equal to the number of closings and openings of the contacts 17 and 18, i.e. 8 pulses for a 360 ° rotation of the crown 4. This signal also attacks the frequency divider by two 52, the output of which delivers the correction signal SC2 containing one pulse out of two of the signal SC1.

Finally, the anti-rebound circuit 53, for example of the type used in circuit 50, receives on its input the signal coming from contact 20 and delivers on its output the signal ST containing a pulse for each traction on the crown 4.

FIG. 6 represents the diagram of a possible embodiment of the mode selector circuit 31. It comprises two shift registers with three positions 55 and 56, each having an input CL and three outputs Q ₁ , Q ₂ and Q ₃ , two shift registers with two positions 57 and 58, each having an input CL and two outputs Q, and Q ₂ , seven doors AND with two inputs referenced 59 to 65 and an OR 66 door with three inputs.

The output Q ₁ of the register 55 is connected to the first inputs of the AND gates 60 and 63. The output Q ₂ of the same register is connected to the first inputs of the AND gates 61 and 64. Finally the output Q ₃ is connected to the first inputs of the gates ET 62 and 65. The second inputs of AND gates 60 to 62 receive the signal ST. The second inputs of AND gates 63, 64 and 65 are connected respectively to outputs Q ₁ of registers 56, 57 and 58. The outputs of AND gates 60, 61 and 62 are connected respectively to inputs CL of registers 56, 57 and 58. The outputs of AND gates 63, 64 and 65 respectively supply the signals F ' ₁ , F' ₂ and F ' ₃ . The outputs Q ₂ and Q ₃ of the register 56 respectively supply the signals C ' ₁ and C' ₂ . Likewise, the outputs 0 ₂ of the registers 57 and 58 respectively supply the signals C ' ₃ and C' ₄ . The first input of AND gate 59 receives the signal SC2, but the signal SC1 could also be used in place of the signal SC2. The output of this same gate attacks the input CL of the register 55. Finally, the second input of the AND gate 59 receives the output signal of the OR gate 66 whose three inputs are controlled respectively by the signals F ' ₁ , F ' ₂ and F' ₃ .

The operation of the circuit of FIG. 6 will now be described. Suppose that in an initial state taken just after powering up the watch circuit, the registers 55 to 58 are all put, by means not shown but known per se, in a state where only the outputs 0 ₁ are at high logic level. Under these conditions a high logic level is found on the first input of the AND gates 60, 64, 65 and on the two inputs of the AND gate 63. At the output of the latter gate the signal F ' ₁ is then at the logic level high, while the other output signals F ' ₂ , F' ₃ , C ' _i , C' ₂ , C ' ₃ and C' ₄ are at low logic level. The high logic level of the signal F ', at the input of the OR gate 66 means that the second input of the AND gate 59 is also at the high logic level. A first pulse of signal SC2 can then pass through this latter gate and control the input CL of register 55, which has the effect of passing its output Q ₁ to the low logic level and its output Q ₂ to the high logic level. The first input of the AND gate 63 passing to the low logic level, it is the same for the signal F ' ₁ on its output. On the other hand, the two inputs of the AND gate 64 now being at the high logic level, the signal F ' ₂ at the output of this gate also takes the same logic state. The first pulse of signal SC2 therefore has the effect of passing signal F ' ₁ to the low logic level and the signal F' ₂ to the high logic level. The signal F ' ₂ also being present on an input of the OR gate 66, the second input of the AND gate 59 is always at the high logic level. A second pulse of the signal SC2 can therefore reach the input CL of the register 55 and pass its output O2 to the low logic level and its output Q ₃ to the high logic level. The first input of the AND gate 64 thus being at the low logic level, the signal F ' ₂ on its output takes the same logic state. The two inputs of the AND gate 65 being on the other hand at the high logic level, there is at its output the same logic state on the signal F ' ₃ . The second pulse of the signal SC2 therefore has the effect of passing the signal F ' ₂ to the low logic level and the signal F' ₃ to the high logic level. Analogous reasoning would show that a third pulse of the signal SC2 would bring the circuit into its initial state in which only the signal F ' ₁ is at the high logic level.

Let us now examine the effect of a first pulse of the signal ST on the circuit of figure 6 when it is in its initial state. The first input of the AND gate 60 then being at the high logic level, it lets pass the pulse of the signal ST which comes to control the input CL of the register 56. This has the effect of passing the output Q ₁ of this register, as well as the signal F ' ₁ , at the low logic level and the output Q ₂ , as well as the signal C' ₁ , at the high logic level. The first pulse of the signal ST therefore changed the watch circuit from the function F, to the correction mode C _l . A second pulse of the signal ST passes, for the same reasons, the output Q ₂ of the register 56, as well as the signal C ' ₁ , at the low logic level and the output Q ₃ , as well as the signal C' ₂ , at the level high logic. After the first and second pulses of the signal ST, the signals F ' ₁ , F' ₂ and F ' ₃ being at the low logic level, the second input of the AND gate 59 is also at the low logic level. In the correction modes Ci and C _2, the latter gate therefore blocks the pulses of the signal SC2. A third pulse of the signal ST returns the circuit to its initial state with a high logic state on the output Q ₁ of the register 56. A similar reasoning would show that it is the signals C ' ₃ and F' ₂ which would pass successively to the high logic level at each pulse of the signal ST for a high logic level on the output Q ₂ of the register 55. Finally if it is the output Q ₃ of this register which is at the high logic level, these are the signals C ' ₄ and F' ₃ which will successively take a high logic level at each pulse of the ST signal. In the correction modes the pulses of signal SC2 have no effect on the circuit.

FIG. 7 shows the diagram of a possible embodiment of the control circuit 40 of the motor 41. This circuit comprises four AND gates referenced 72 to 76, with two inputs, two OR gates, referenced 77 and 78, with two inputs, an OR gate 79 with three inputs, a delay flip-flop 80 having two inputs denoted CL and D and an output Q and finally a drive circuit 81 of the motor having two inputs denoted CL and C / D and four outputs denoted Q , B ₁ , B ₂ and B ₃ .

The signal 1/30 Hz from the output of the AND gate 71 attacks the first input of the OR gate 77 and the second input of the latter gate receives the signal supplied by the output of the AND gate 72. The first inputs of the gates AND 72 and 73 are connected together and are controlled by the signal C ' ₄ . The second input of AND gate 72 receives the signal SC2. The second input of AND gate 73 is connected to output Q of flip-flop 80. The first and second inputs of AND gate 74 receive signals SC1 and C ' _{3 respectively} . The output of the latter gate is connected to the first input of the OR gate 79. The output of the OR gate 77 and the output of the AND gate 73 are connected respectively to the second and to the third input of the OR gate 79. The output of this last gate is connected to the input CL of circuit 81. The first inputs of AND gates 75 and 76 receive the signal CD generated by circuit 30. The second inputs of these latter gates respectively receive signals C ' ₃ and C ' ₄ . The first and second input of the OR gate 78 are connected respectively to the output of the AND gate 75 and to the output of the AND gate 76. The C / D input of the circuit 81 is connected to the output of the OR gate 78 and the output Q of this same circuit is connected to the input D of the circuit 80. Finally the input CL of the circuit 80 receives the 8 Hz signal coming from the frequency divider 36, but any signal having a frequency of the same order of grandeur might also be suitable.

The drive circuit 81 located in FIG. 7 is intended to supply signals B ₁ , B ₂ , B ₃ to the two coils, connected in series, of the two-phase motor 41 so as to rotate it one step at a time. response to each pulse applied to the CL input. The signal B ₁ is applied to a terminal of the first coil, the signal B ₂ to a terminal of the second coil and the signal B ₃ to the terminal common to the two coils. One motor step corresponds to a 180 ° rotation of the rotor and it advances the minute hand of the analog display by 1/2 minute. The rotor can therefore occupy two positions and each position corresponds to a logic state of the Q output. The rotation takes place in one direction or the other depending on the logic state of the C / D input. It will be assumed that the motor turns in the direction which advances the hands 2 when the terminal C / D is at the low logic level.

Such a circuit has been described in detail in patent application CH 918 / 82-8 and FIG. 5 of this document gives an example of a diagram. In this diagram C _k and Q of the flip-flop 34 and AR at the input of the inverter 29 correspond respectively to CL, Q and C / D of the circuit 81 of the present application. The signal on the point common to the transistors T ₅ and T ₆ of the cited request corresponds to the signal B ₁ of the present request. Similarly, the signal on the point common to the transistors T ₁ and T ₂ corresponds to the signal B ₂ and that of the point common to the transistors T ₃ and T4 to the signal B ₃ .

In the operation of the circuit 40 shown in FIG. 7, three cases must be distinguished. The first corresponds to that where the signals C ' ₃ and C' ₄ are at the low logic level, causing the same logic state on one of the inputs of AND gates 72 to 76 and on the output of each of these gates. This has the consequence of blocking the signals SC1, SC2 as well as the signal at the output Q of the flip-flop 80 respectively by the AND gates 74, 72 and 73 and of forcing a low logic level on the C / D input of the circuit 81 via AND gates 75, 76 and OR gate 78. The low logic state of signal C ' ₄ causes a high logic level at the output of inverter 70 as well as at the second input of AND gate 71 which thus lets pass the 1/30 Hz signal present on its first input. This signal then passes through the OR gates 77 and 79, the other inputs all being at the low logic level, to come to control the CL input of the circuit 81. In the first case of operation of the circuit 40 the C / D input of the circuit 81 is therefore at the low logic level and the 1/30 Hz signal directly controls the CL input.

The second case is that where the signal C'3 is at the high logic level and the signal C ' ₄ at the low logic level. The second inputs of AND gates 74 and 75 are then at the high logic level, allowing the signal SC1 to reach the first input of the OR gate 79 and the CD signal to the C / D input of circuit 81 through the OR gate. 78. The 1 Hz signal being blocked by the AND gate 37, the 1/30 Hz signal does not exist and only the SC1 signal arrives through the OR gate 79 on the CL input of circuit 81, making it possible to correct the analog display forward or backward.

Finally in the third case, the signal C ' ₃ is at the low logic level and the signal C' ₄ at the high logic level. This results in a low logic level on the second input of AND gates 71 and 74 and a high logic level on the first input of AND gates 72, 73 and on the second input of AND gate 76. As a result, the signals 1 / 30 Hz and SC1 are blocked while the signal SC2 arrives on the second input of the OR gate 77, the signal at the output Q of the flip-flop 80 arrives on the third input of the OR gate 79 and finally that the signal CD arrives on the input C / D of circuit 81. The signal SC2 thus arrives on the input CL of circuit 81 through the OR gates 77 and 79 and the output signal Q of flip-flop 80 arrives on the same input through OR gate 79. It will be assumed that the output Q of circuit 81 is at the low logic level if the minute hand is over a full minute and at the high logic level if this hand is between two minutes. The logic level of the output Q of the circuit 81, applied to the input D of the flip-flop 80 will be found, after half a period of the 8 Hz signal applied to its input CL, or 1/16 of a second later, on the exit Q of this rocker.

Suppose now, still in the third case, that at the time of the passage of the signal C ' ₄ from the low logic level to the high logic level, the minute hand is not on an entire minute and that the output Q of the flip-flop 80 is already at the high logical level. The transition of the signal C ' ₄ , passing through the AND gates 73 and OR 79, will control the input CL of the circuit 81 and cause the motor 41 to advance by one step. The minute hand will then indicate a full minute, the Q output of circuit 81 will go to the low logic state and, 1/16 of a second later, the Q output of flip-flop 80 will take the same logic state. On the other hand if the minute hand is already on a full minute and the output Q of flip-flop 80 at the low logic level at the moment when the signal C ' ₄ goes to the high logic level, no pulse will be created at the input CL of circuit 81 and motor 41 will remain at rest. Thus switching to correction mode C ₄ has the effect of putting the minute hand over a full minute if it does not already occupy this position.

Finally, let's examine the effect of a pulse of signal SC2 when the watch is in correction mode C ₄ . The minute hand having already passed over a full minute, a pulse of the signal SC2 will cause the motor 41 to advance or reverse, according to the direction of rotation of the crown 4. At the same time the circuit output Q 81 goes to low logic level and, 1/16 of a second later, the Q output of flip-flop 80 will take the same logic state. The transition from the output of this rocker will advance the motor by a second step, bringing the minute hand over a full minute. Thus each pulse of the signal SC2 has the effect of turning the motor by two successive steps very close together, giving the impression that the minute hand advances or decreases by whole minutes.

FIG. 8 represents a possible embodiment of the counting circuit 42. This circuit includes a minute counter 85, an hour counter 86, a day counter 87 and a date counter 88, each counter having two inputs, noted CL and C / D, and two outputs, noted Q ₁ and Q ₂ , six AND gates with two inputs, referenced 89 to 94, and three OR gates with two inputs referenced 95 to 97.

The inputs CL of counters 85 to 88 receive the counting pulses, the direction of counting being determined by the logic level of the input C / D. It will be assumed that the content of the counter is incremented by each counting pulse if C / D is at the low logic level and decremented otherwise. The counter output Q1 is multiple and contains the number of binary signals necessary to define the maximum content of each counter. Thus the output Q ₁ of the minute counter 85 provides m ₁ , m ₂ ... m _j binary signals making it possible to define any number between 0 and 59 minutes. We immediately see that in this case j = 6 and that the set of signals m ₁ , m ₂ , ... m _j defines the multiple signal of the minutes SM. Similarly, the output Q ₁ of the hour counter 86 provides h ₁ , h ₂ , ... h _k binary signals defining a number between 1 and 12 or between 1 and 24, all of these signals forming the signal multiple of hours SH. The output Q ₁ of the two-day counter 87 provides j ₁ , j ₂ , ... j _l binary signals defining a number between 1 and 7, each number corresponding to a day of the week. All of these signals form the multiple signal of the days SJ. Finally, the output Q ₁ of the date counter 88 provides d ₁ , d ₂ , ... d _m binary signals defining a number between 1 and 31, all of these signals forming the multiple signal of the date SD. A counter once fully filled, generates a pulse on its output Q ₂ .

The first input of OR gate 95 receives the 1/60 Hz signal from frequency divider 38 and the second input of this gate is connected to the output of AND gate 89. The first input of AND gate 89 receives the signal C ' ₃ and the second input of this gate receives the correction signal SC2. The inputs C / D of the counters 85 and 86 are connected to the output of the AND gate 90 which receives on its first input the signal C'3 and on its second input the signal CD. The output Q ₂ of the counter 85 is connected to the input CL of the counter 86, the output Q _{2 of which} is connected to the first input of the OR gates 96 and 97. The second input of the OR gate 96 is connected to the output of the AND gate 91, which receives on its first input the signal C ', and on its second input the correction signal SC2. The second input of the OR gate 97 is connected to the output of the AND gate 94, which receives on its first input the signal C ' ₂ and on its second input the correction signal SC2. The output of the OR gate 96 is connected to the input CL of the counter 87, the output Q _{2 of which} remains free. The output of the OR gate 97 is connected to the input CL of the counter 88, the output Q _{2 of which} also remains free. The input C / D of the counter 87 is connected to the AND gate 92, which receives on its first input the signal C ', and on its second input the signal CD.

Finally, the input C / D of the counter 88 is connected to the output of the AND gate 93, which receives on its first input the signal C ' ₂ and on its second input the signal CD.

In the operation of the circuit 42 shown in FIG. 8, four cases must be distinguished. The first corresponds to that where the signals C ' ₁ , C' ₂ and C ' ₃ are all at the low logic level. The other three correspond to the cases where one of the signals C ' ₁ , C' ₂ or C ' ₃ is at the high logic level.

The low logic level of the signals C ' ₁ , C' ₂ and C ' ₃ in the first case causes a low logic level on the first input of the AND gates 89 to 94, therefore a logic level also low on the outputs of these gates, regardless of the logic level of the second input. This results in a low logic level on the C / D input of counters 85 to 88. Each counting pulse on the CL input thus increments their content. The second inputs of the OR gates 95 to 97 are also at the low logic level. These doors therefore only transmit the signal present on their first input. Only the 1/60 Hz minute signal therefore reaches, via the OR gate 95, the CL input of the minute counter 85. The content of this counter appears on the output Q ₁ while on the output Q ₂ appears a signal containing one pulse per hour, which is applied to the CL input of the hour meter 86. The content of the counter 86 appears on the output Q ₁ while the output 0 ₂ delivers a signal containing a pulse per 24 hours. This last signal attacks, through OR gates 96 and 97, the CL input of the day counter 87 and the date counter 88. The content of these counters appears on their output Q ₁ . In the first case, the circuit 42 thus simply counts the minute pulses and provides the information relating to the hour, the day and the date.

The second case is that where the signal C ' ₁ is at the high logic level and the signals C' ₂ and C ' ₃ at the low logic level. The first input of AND gates 91 and 92 then being at the high logic level, at the output of these gates, the signals SC2 and CD appear respectively. The signal SC2 then arrives through the OR gate 92 on the input CL of the day counter 87 and the signal CD on the input C / D of the same counter. The pulses of the signal SC2 generated by the rotation of the crown 4 then make it possible to modify, more or less depending on the direction of rotation, the content of the day counter.

In the third case, it is the signal C ' ₂ which is at the high logic level and the signals C' ₁ and C ' ₃ at the low logic level. This case is similar to the previous ones, the first input of the AND gates 93 and 94 being at the high logic level, the signal SC2 arrives, through the OR gate 94, on the input CL of the date counter 88 and the signal CD on the 'C / D input of the same counter. The rotation of the crown 4 then makes it possible to modify the content of this counter.

Finally, in the fourth case of operation of the circuit 42, the signal C ' ₃ is at the high logic level and the signals C' ₁ and C ' ₂ at the low logic level. The first input of the AND gates 89 and 90 being at the high logic level, the signal SC2 arrives on the input CL of the minute counter 85 through the OR gate 95 and the signal CD on the input C / D of the counters 85 and 86. The pulses of the signal SC2, in response to the rotation of the crown 4, then make it possible to correct the time information by modifying the content of the counters 85 and 86.

A possible form of the diagram of the display selector circuit 43 is shown in FIG. 9. This circuit includes p all identical switching circuits, referenced 100 ₁ , 100 ₂ , ... 100p and q all identical switching circuits, references 101 ₁ , 101 ₂ , ... 101 _q . These circuits each have seven inputs and one output and will be described in detail later. The circuit 100 ₁ receives on its first input the signal j ₁ , contained in the multiple signal SJ supplied by the circuit 42, on its second input the Signal h ₁ , contained in the multiple signal SH, on the following 5 inputs, taken from the increasing order of their numbering, respectively the control signals F ' ₁ , F' ₂ , C ' ₁ , C' ₃ , C ' ₄ and it delivers on its output the signal x. The circuit 100 ₂ receives on its first two inputs the signals j ₂ and h ₂ , on the other inputs the same control signals as the circuit 100 ₁ and it delivers on its output the signal x ₂ . Finally, the circuit 100p, being equal to the higher of the two numbers 1 or k, receives on its first two inputs the signals j ₁ and h _k , on the other inputs the same control signals as the circuit 100 ₁ and it delivers on its output the signal xp. If for example 1 is greater than k then p = 1 and, since the signals h _{k + 1} to hp do not exist, the second inputs of the circuits 100 _{k + 1} to 100p will all be set to low logic level. The signals x ₁ , x ₂ , ... x of this circuit define the multiple signal x (J; H). Similarly, the circuit 101 ₁ receives on its first input the signal d ₁ , on its second input the signal m ₁ , on the five following inputs respectively the control signals F ' ₁ , F' ₂ , C ' ₂ , C ' ₃ , C' ₄ and it outputs the signal y ₁ at its output. Finally for circuit 101 _q can be said exactly the same as for circuit 100p provided that j is replaced by d, h by m, the index 1 by n, the index k by j and the index p by q . The signals y ₁ , y ₂ , ... _Y q of these circuits define the multiple signal y (D; M).

Depending on the logic state of the control signals F ' ₁ , F' ₂ C ' ₁ , C' ₃ , C ' ₄ , the selection circuits 100 ₁ to 100p will transmit on their respective output, i.e. signals j ₁ ... j ₁ , i.e. the signals h ₁ ... h _k . Thus in the case where one of the signals F ' ₁ or C' is at the high logic level and the other control signals at the low logic level, the signal x ₁ will be identical to the signal j ₁ , the signal x ₂ to the signal j ₂ etc. and finally the signal x (J; H) will be identical to the signal SJ. On the other hand if it is one of the signals F ' ₂ , C' ₃ , C ' ₄ which is at the high logic level and the other control signals at the low logic level, the output signal x (J; H) will be identical to signal SH. The selection circuits 101, to 101q operate in a similar fashion. If one of the signals F ' ₁ or C' ₂ is at the high logic level and the other control signals at the low logic level, the output signal y ₁ will be identical to the signal d ₁ , the signal y ₂ to the signal d ₂ etc. and finally the signal y (D; M) will be identical to the signal SD. Finally if it is one of the signals F ' ₂ , C' ₃ , C ' ₄ which is at the high logic level and the other control signals at the low logic level, the signal y (D; M) will be identical to the signal SM.

An exemplary embodiment of the switching circuit 100 ₁ is shown in FIG. 10a. This circuit includes two AND gates 110 and 111 with two inputs, two OR gates 112 and 113 with two inputs and an OR gate 114 with three inputs. The first input of the AND gate 110 receives the signal j ₁ and the second input of this gate is connected to the output of the OR gate 112. The first input of the OR gate 112 receives the signal F ' ₁ and the second input of this door receives the signal C ' ₁ . The first input of AND gate 111 receives the signal h ₁ and the second input of this gate is connected to the output of OR gate 114. The three inputs of OR gate 114, taken in ascending order of their numbering, receive signals F ' ₂ , C' ₃ and C ' _{4 respectively} . Finally the signal x ₁ is taken on the output of the OR gate 113, one input of which is connected to the output of the AND gate 110 and the other input to the output of the AND gate 111.

The operation of the routing circuit 100, of FIG. 10a is as follows. If one of the signals F ', or C', is at the high logic level and the other control signals F ' ₂ , C' ₃ , C ' ₄ at the low logic level, the output of the OR gate 112 will be at the level logic high and the output of OR gate 114 at logic low level. The second input of the AND gate 111 being at the low logic level, this gate blocks the signal h ₁ applied to its first input. The second input of the AND gate 110 being on the other hand at the high logic level, it allows the signal j to pass, which is thus found at the output of the OR gate 113. The signal x, is therefore identical, in this case, at signal j ₁ . If now it is one of the signals F ' ₂ , C' ₃ , C ' ₄ which is at the high logic level and the other control signals F' ₁ , C ', at the low logic level, then the output of the OR gate 112 will be at the low logic level and the output of OR gate 114 at the high logic level. In this case, it is the signal j, which is blocked and the signal x, becomes identical to the signal h ₁ .

The structure of the switch circuit 101, shown in FIG. 10b is identical to that of the circuit 100 ₁ , the two circuits comprising the same doors interconnected in the same way. On the other hand, in circuit 101 ₁ , the first input of the AND gate 110 receives the signal d ₁ instead of j ₁ , the first input of the AND gate 111 receives the signal m ₁ instead of h ₁ and the second input from OR gate 112 receives signal C ' ₂ instead of C' ₁ . The other inputs of the OR gates 112 and 114 receive the same signals in the two circuits.

The operation of circuit 101 ₁ in FIG. 10b is also similar to that of circuit 100 ₁ . Taking into account the fact that different signals are applied to certain inputs of circuits 100, and 101 ₁ , the signal y ₁ will be identical to the signal d ₁ if one of the signals F ' ₁ or C' ₂ is at the high logic level and other control signals at the low logic level. Similarly, the signal y ₁ will be identical to the signal m ₁ if it is one of the signals F ' ₂ , C' ₃ , C ' ₄ which is at the high logic level and the other control signals at the low logic level.

The present invention is not limited to the embodiment which has just been described. For example, the hands of the analog display could be replaced by discs bearing marks. Likewise, digital display could be achieved using light-emitting diodes, electrochromic devices, etc. instead of liquid crystals. The crown could have more than two axial positions in order to increase its control possibilities. Other control elements, for example push-buttons actuating contacts, capacitive keys, photoelectric sensors etc. could be used in place of or in conjunction with a crown. The correction pulses could be taken from the frequency divider. The digital display could have an indication of seconds; in this case, the watch could include means making it possible to align the minute hand with the seconds, preferably automatically when exiting synchronization mode. The digital display and the analog display could both display the second, and in this case the synchronization mode could be reserved for aligning the second hand with the seconds of the digital display. An additional synchronization mode could be provided to allow in addition to separately align the hour hand with the hours of the digital display. Many variations are possible.

Claims (6)

1. An electronic watch comprising:

- a time base arranged to provide a standard frequency signal;

- a divider circuit arranged to divide said standard frequency signal;

- indicating means arranged to display a first group of time information items in analog form one of said means displaying the present minute;

- a stepping motor mechanically coupled to said indicating means;

- a control circuit arranged to supply drive pulses to the motor so as to effect displacement of said indicating means in response to time pulses provided by the divider circuit as well as to correcting pulses;

- a counting circuit likewise receiving time pulses from the divider circuit thereby to provide signals representing a second group of time information items of which at least one information item is included in said first group; an electro-optic display coupled to said counting circuit in order to display the second group of time information in digital form;

- manual control means; and

- a selecting and correcting logic circuit responsive to operation of said manual control means thereby to place the watch in different display modes for each of which a selected time information is displayed by said electro-optic display means and in different correction modes for each of which an information item displayed in digital form may be corrected through application by said logic circuit of correcting pulses to the counting circuit, said logic circuit likewise applying correcting pulses to the motor control circuit whenever the information to be corrected is that common to both groups, said common information being the indication of present minutes and said means displaying the minutes normally advancing by n steps per minute, n being always greater than 1, so as to modify by a same amount the analog display and the digital display of said information, and in a supplementary synchronisation mode in which said common information is displayed by the electro-optic digital display and in which said logic circuit responds to an operation of said manual control means by applying correcting pulses only to the motor control circuit to enable bringing the analog display into coincidence with the digital display of said information, characterized by the fact that the control circuit (40) for the motor (41) is designed to bring said minutes display means (2) automatically onto a whole minute at the time of passing into the synchronisation mode and in this mode to generate and apply to the motor (41) n successive motor pulses in response to each correction pulse that said control circuit (40) receives from said logic circuit (200).

2. A watch according to claim 1, characterized by the fact that said logic circuit (200) comprises means (70; 71) for preventing application of time pulses to the control circuit (40) for the motor (41) when in the synchronisation mode.

3. A watch according to claim 1, characterized by the fact that said number n of steps per minute equals 2.

4. A watch according to either of claims 1 or 3, characterized by the fact that said first and second groups comprise a further common information item, such further common information item being the indication of present hours.

5. A watch according to any of the preceding claims, characterized by the fact that said stepping motor (41) is a bidirectional motor and that said counting means (42) are adapted to count up and down in order to enable modification of the time information of both groups in both directions.

6. A watch according to any of the preceding claims, characterized by the fact that said manual control means are formed by a rotatable crown (4) shiftable between at least two axial positions and actuating electrical contacts (17; 18; 20) coupled to said logic circuit (200).

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