EP0119280A1 - Décodeur à circuits intégrés de signaux radioélectriques d'identification de zones de trafic - Google Patents

Décodeur à circuits intégrés de signaux radioélectriques d'identification de zones de trafic Download PDF

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Publication number
EP0119280A1
EP0119280A1 EP83102412A EP83102412A EP0119280A1 EP 0119280 A1 EP0119280 A1 EP 0119280A1 EP 83102412 A EP83102412 A EP 83102412A EP 83102412 A EP83102412 A EP 83102412A EP 0119280 A1 EP0119280 A1 EP 0119280A1
Authority
EP
European Patent Office
Prior art keywords
output
input
comparator
frequency
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP83102412A
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German (de)
English (en)
Other versions
EP0119280B1 (fr
Inventor
Heinrich Dipl.-Ing. Pfeifer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Priority to DE8383102412T priority Critical patent/DE3364612D1/de
Priority to EP83102412A priority patent/EP0119280B1/fr
Priority to JP59045725A priority patent/JPS59175221A/ja
Publication of EP0119280A1 publication Critical patent/EP0119280A1/fr
Application granted granted Critical
Publication of EP0119280B1 publication Critical patent/EP0119280B1/fr
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/09—Arrangements for giving variable traffic instructions
    • G08G1/091—Traffic information broadcasting
    • G08G1/094—Hardware aspects; Signal processing or signal properties, e.g. frequency bands

Definitions

  • the invention relates to an integrated circuit for decoding traffic radio area identification signals, the frequency, the area frequency, of which is information about the area, the area identification signals being contained in the form of a carrier signal amplitude-modulated therewith in a received radio signal already demodulated in a conventional radio receiver, cf. . the preamble of claim 1.
  • the traffic radio signal contains area identification signals.
  • area identification signals the frequency of which is the information about the area as the area frequency, are quite low-frequency signals and are modulated onto the carrier signal by means of amplitude modulation, which has a frequency of 57 kHz in the known system, and are otherwise by ? possible frequency division derived from the carrier signal.
  • the block diagram of an integrated circuit for decoding traffic information signals according to the invention is shown in FIG. 1.
  • the demodulated radio signal ds which is obtained by means of a conventional radio receiver, is fed to the mixer stage ms, whose mixed signal frequency fm is greater than the largest range frequency fb.
  • 5 Hz fm 2 23:
  • the mixing stage ms the area identification signals modulated onto the carrier signal are converted to the mixed signal frequency fm.
  • the output of the mixer stage ms is via the analog low-pass filter af at the input of the analog / digital converter aw.
  • the output of the analog-digital converter aw is also at the first input of the multiplier m, the second input of which is at the output of the digital clamping circuit kl, which is downstream of the digital bandpass filter bp in terms of signal flow. It clamps positive or negative input signals to the positive or negative maximum value specified by their number of digits.
  • the analog-digital converter aw which must then be a delta-sigma converter, can directly follow the mixing stage ms, whereby then, however, the digital low-pass filter df must be arranged between the input of the digital bandpass filter bp and the output of the analog-digital converter aw.
  • the mixed signal is recovered by means of the digital bandpass, and by means of the digital clamping circuit kl amplitude normalized.
  • the area identification signals are then demodulated by means of the multiplier m.
  • each signal path in the signal flow direction consists of the digital resonance filter ra, rb, rf for the respective range frequency fb, the digital absolute value generator ba, bb, bf and the digital low-pass filter pa, pb, pf, the upper limit frequency of which is less than twice the smallest range frequency.
  • this lowest range frequency which is assigned to range A there, has a value of 23.75 Hz.
  • the three subcircuits arranged in signal path a, b, f have the function of a selective level measurement.
  • One of each of the outputs of the low-pass filters pa, pb, pf is connected to an input of the multiple comparator vk, at the first maximum output mx1 of which a signal occurs via the signal path which carries the largest signal, i.e. a digital word for the number of the signal path with the largest signal value appears at the first maximum output mx1.
  • a signal appears at the second maximum output mx2 about the number of the signal path that carries the second largest signal.
  • D T r first or second maximum output mx1, mx2 is located at the control input of the first or second electronic multiple switch s1, s2, the inputs of which are each connected to an output of the low-pass filters pa, pb, pf.
  • the two multiple switches s1, s2 thus have as many inputs as there are signal paths, and from the output signals to the maximum outputs mxl, mx2, they are switched to the signal path that carries the largest or the second largest signal value.
  • the output of the first multiple switch s1 is on the one hand via the first constant multiplier m1 at the minuend input of the first comparator k1, to the subtrahend input of which the output of the multiple adder ad is connected. Its inputs are located at the output of one of the low passes pa, pb, pf.
  • the output of the first multiple changeover switch s1 is also via the second constant multiplier m2 at the minuend input of the second comparator k2, to the subtrahend input of which the output of the second multiple changeover switch s2 is connected.
  • the second comparator k2 and the second comparator m2 determine whether the amplitude of the first maximum signal multiplied by a constant factor is greater than the second maximum signal. By means of these constants provided in the second constant multiplier m2 as the one multiplication factor, the external channel spacing can be determined.
  • the level of the first maximum signal is compared in a comparable manner with the sum of the signal values of the other signal paths, which is a signal-to-noise ratio measurement.
  • the delay element vg is located at the first maximum output mx1 of the multiple comparator k and at the output thereof the minuend input of the third comparator k3, the subtrahend input of which is connected to the first maximum output mx1.
  • the minute-equal-subtrahend output of the third comparator k3 is via the inverter it Reset input er of the counter z, the counter input of which is supplied with the clock signal t and the counter outputs of which are connected to the minuend input of the fourth comparator k4, the subtrahend input of which is supplied the constant k serving as threshold value.
  • the output of the digital bandpass bp is followed by the further absolute value generator bw, which is followed by the further digital low-pass filter pw, the upper limit frequency of which is equal to that of the low-pass filters pa, pb, pf and the output of which via the third or fourth constant multiplier m3, m4 is at the subtrahend input of the fifth or the sixth comparator k5, k6, whose respective minuend input is connected to the output of the first multiple switch s1.
  • the minuend-larger-subtrahend output of the fifth comparator k5 and the minuend-smaller-subtrahend output of the sixth comparator k6 are each connected to one of the two inputs of the first AND gate u1.
  • the degree of modulation of the area identification signals is monitored by means of the last-mentioned subcircuits bw, pw, m3, m4, k5, k6, u1, because noise manifests itself as an increased degree of modulation and, on the other hand, an unmodulated carrier likewise frequently occurs as a disturbance.
  • the first maximum signal is compared with the amplitude of the mixed signal with respect to an upper and a lower threshold, which are predetermined by the constants of the third and fourth constant multipliers m3, m4.
  • the second AND gate u2 Of the four inputs of the second AND gate u2, one is located at the respective minuend-greater-subtrahend output of the first comparator k1, the second comparator k2 and the fourth comparator k4 and at the output of the first AND gate u1.
  • the first maximum output mx1 of the multiple comparator vk is located at the parallel input of the multiple AND gate vu, the output of which is the area signal output ba of the integrated circuit, and the output of the second AND gate u2 is located at all points of the second parallel input of the multiple AND -Gatters vu.
  • the mixer stage ms which consists of the unit amplifier v1 and the electronic switch s, the control signal of which is the mixed signal fm.
  • the unit amplifier v1 has the gain 1 and outputs at its output like a conventional analog amplifier an output signal rotated by 180 ° with respect to its input signal.
  • the radio signal ds which is also located at the input of the unit amplifier v1 is switched through directly to the output of the switch s, once and once in its form rotated by 180 °, that is to say inverted.
  • the mixed signal fm is a square wave signal.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Circuits Of Receivers In General (AREA)
EP83102412A 1983-03-11 1983-03-11 Décodeur à circuits intégrés de signaux radioélectriques d'identification de zones de trafic Expired EP0119280B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE8383102412T DE3364612D1 (en) 1983-03-11 1983-03-11 Integrated circuit for decoding radio broadcast traffic area identification signals
EP83102412A EP0119280B1 (fr) 1983-03-11 1983-03-11 Décodeur à circuits intégrés de signaux radioélectriques d'identification de zones de trafic
JP59045725A JPS59175221A (ja) 1983-03-11 1984-03-12 交通情報の地域ト−ン信号用デコ−ダ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP83102412A EP0119280B1 (fr) 1983-03-11 1983-03-11 Décodeur à circuits intégrés de signaux radioélectriques d'identification de zones de trafic

Publications (2)

Publication Number Publication Date
EP0119280A1 true EP0119280A1 (fr) 1984-09-26
EP0119280B1 EP0119280B1 (fr) 1986-07-23

Family

ID=8190338

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83102412A Expired EP0119280B1 (fr) 1983-03-11 1983-03-11 Décodeur à circuits intégrés de signaux radioélectriques d'identification de zones de trafic

Country Status (3)

Country Link
EP (1) EP0119280B1 (fr)
JP (1) JPS59175221A (fr)
DE (1) DE3364612D1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4969209A (en) * 1987-07-27 1990-11-06 Prs Corporation Broadcast receiver capable of selecting stations based upon geographical location and program format

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2719618A1 (de) * 1977-05-03 1978-11-09 Koerting Radio Werke Gmbh Schaltungsanordnung an einem integrierten pll-decoder
DE2916171A1 (de) * 1979-04-21 1980-10-30 Licentia Gmbh Ueberlagerungsempfaenger

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2719618A1 (de) * 1977-05-03 1978-11-09 Koerting Radio Werke Gmbh Schaltungsanordnung an einem integrierten pll-decoder
DE2916171A1 (de) * 1979-04-21 1980-10-30 Licentia Gmbh Ueberlagerungsempfaenger

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GRUNDIG TECHNISCHE INFORMATIONEN, Heft 4/5, 1980, Seiten 255-259, Regensburg, DE. *
RADIOMENTOR ELECTRONIC, Band 44, Nr. 12, Dezember 1978, Seiten 480-481, München, DE. *

Also Published As

Publication number Publication date
EP0119280B1 (fr) 1986-07-23
DE3364612D1 (en) 1986-08-28
JPS59175221A (ja) 1984-10-04

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