EP0162943B1 - Circuit intégré pour décoder le signal d'identification des communiqués pour le trafic radio - Google Patents

Circuit intégré pour décoder le signal d'identification des communiqués pour le trafic radio Download PDF

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Publication number
EP0162943B1
EP0162943B1 EP84106270A EP84106270A EP0162943B1 EP 0162943 B1 EP0162943 B1 EP 0162943B1 EP 84106270 A EP84106270 A EP 84106270A EP 84106270 A EP84106270 A EP 84106270A EP 0162943 B1 EP0162943 B1 EP 0162943B1
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EP
European Patent Office
Prior art keywords
signal
frequency
digital
output
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP84106270A
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German (de)
English (en)
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EP0162943A1 (fr
Inventor
Heinrich Dipl.-Ing. Pfeifer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
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Deutsche ITT Industries GmbH
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Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE8484106270T priority Critical patent/DE3467648D1/de
Priority to EP84106270A priority patent/EP0162943B1/fr
Priority to US06/736,633 priority patent/US4633517A/en
Priority to JP60115520A priority patent/JPS60264128A/ja
Publication of EP0162943A1 publication Critical patent/EP0162943A1/fr
Application granted granted Critical
Publication of EP0162943B1 publication Critical patent/EP0162943B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/09—Arrangements for giving variable traffic instructions
    • G08G1/091—Traffic information broadcasting
    • G08G1/094—Hardware aspects; Signal processing or signal properties, e.g. frequency bands

Definitions

  • the invention relates to an integrated circuit for decoding traffic announcement signals whose frequency, the announcement frequency, is the information for a traffic announcement and which are contained in the form of a carrier signal amplitude-modulated therewith in a broadcast signal received and already demodulated with a conventional radio receiver, cf. the preamble of claim 1.
  • the demodulated radio signal ds which is obtained by means of a conventional radio receiver, is fed to the mixer stage ms, whose mixed signal frequency fm is greater than the sum of the announcement frequency fa and its carrier frequency. In relation to the system described in the two journals mentioned at the beginning, this means that the mixed signal frequency should be greater than 57.125 kHz.
  • the announcement identification signal modulated onto the carrier signal is converted into a low-frequency position.
  • the output of the mixer stage ms is via the analog low-pass filter af at the input of the analog-digital converter aw, to which the clock signal ft is fed.
  • the upper cut-off frequency of the low-pass filter af is at most equal to half the frequency of the scanning signal from the analog-digital converter aw, and its output is at the input of the digital absolute value generator br. This forms the amount of the input signal defined in the mathematical sense, i.e. its output signal is always positive and corresponds to the respective pure numerical value for both positive and negative input signals; both the number - -7 and the number + thus become + 7.
  • the digital signal x is generated in the baseband position, and this is for the announcement frequency fa or the frequency fb, fc deviating therefrom by at most + 1% or -1% with the first, second or third signal path a, b, c connected.
  • These consist in the signal flow direction of the digital resonance filter ra, rb, rc for the corresponding frequency fa, fb, fc as their resonance frequency, the digital absolute value generator ba, bb, bc and the digital low pass pa, pb, pc.
  • Its respective upper cut-off frequency is less than twice the announcement frequency fa, and the three resonance filters ra, rb, rc have the same bandwidth and the same resonance magnification, as illustrated in FIG. 2.
  • the magnitude generator br is the series connection of the first and the second further digital low-pass filter p1, p2, whose respective upper cut-off frequency is equal to that of the digital low-pass filters pa, pb, pc or the frequency corresponding to the settling time constant of the resonance filters ra, rb, rc is.
  • the constant multiplier m1 and m2 in a parallel branch.
  • the first signal path a leads to the respective minuend input m of the first, second, third and fourth comparators k1, k2, k3, k4, of which the Subtrahend input s of the first and second comparators k1, k2 at the output of the first and second constant multipliers m1, m2 and subtrahend input s of the third and fourth comparators k3, k4 at the output of the second and third signal paths b, c lies.
  • the minuend-larger subtrahend output m> s of the first comparator k1 is located at the S input of the RS memory flip-flop ff, from whose Q output the binary announcement identification signal dk is to be taken, and the respective minuend-smaller subtrahend output m ⁇ s of the second, third and fourth comparators k2, k3, k4 is located above the OR gate og at the R input of the RS flip-flop ff.
  • the constant d1, d2 of the respective constant multiplier m 1, m2 is in each case less than one and equal to the nominal degree of modulation of the announcement characteristic signal or equal to a predeterminable fraction of the nominal degree of modulation.
  • FIG. 3 shows that the arrangement according to the invention can also be used with a plurality of broadcasting frequencies, as is the case, for example, for a standard customary in the USA.
  • the 'three signal paths a, b, c, the comparators k1 ... k4 assigned to them and the RS memory flip-flop ff are to be provided twice, each with a corresponding frequency rating.
  • the common circuit part is then also dimensioned with regard to the highest occurring announcement frequency.
  • the course of the resonance curves of the then six resonance filters is shown in FIG. 3, the resonance frequency of which is fa1, fb1, fc1; fa2, fb2, fc2 are designated.
  • the carrier amplitude, to which the announcement signal is modulated is measured by means of the magnitude generator br, which performs a full-wave rectification, comparable to a rectifier bridge for analog signals.
  • the announcement frequency is demodulated.
  • the three signal paths a, b, c serve as a selective level meter, the signal path a measuring the announcement frequency and the two signal paths b, c detecting closely adjacent interference signals. Only when there is an input signal on the three signal paths with a frequency between the intersections x, y of the resonance curve of the resonance filter ra with the respective resonance curve of the other two resonance filters is the output signal on signal path a greater than that on the other two signal paths b, c. By comparison using the comparators k3, k4 it is then determined and recorded whether the frequency of the input signal is in the range between x and y.
  • the RS memory flip-flop ff is set by means of the comparator k1 if the output signal on the signal path a is greater than the output signal of the magnitude generator br, which is filtered by the low-pass filters p 1, p2 and multiplied by the factor d 1.
  • the flip-flop ff is reset by means of the comparators k2 ... k4 and the OR gate og in each case when one of the output signals of the signal paths b, c is greater than that of the signal path a or this output signal is smaller than that by means of the low-pass filters p1 , p2 filtered and multiplied by the factor d2 output signal of the magnitude br.
  • a circuit hysteresis can therefore be set with the factor d2.
  • the invention can be implemented particularly advantageously in the form of integrated semiconductor circuits. Since it works exclusively, at least as far as the subcircuits behind the analog-digital converter aw are concerned, according to digital circuit principles, the semiconductor circuit families customary for digital signal processing can be used, of which in particular the so-called MOS-integrated circuits can be used, i.e. integrated insulating layer field effect transistor circuits. Furthermore, there is the advantage that the inventive design with regard to the resonance frequencies of the resonance filters that are adjacent in the one percent range achieves very good interference suppression and reliable announcement frequency detection. Such a narrow resonance frequency measurement with analog resonance filters would only be achievable with considerable effort.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Circuits Of Receivers In General (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Claims (2)

1. Circuit intégré pour le décodage de signaux d'identification de message dont la fréquence, dite fréquence de message (fa), est l'information caractérisant un message de radioguidage et qui sont contenus, sous la forme d'une onde porteuse modulée en amplitude par ceux-ci, dans un signal radiodiffusé (ds) reçu et démodulé par un récepteur radio courant, caractérisé en ce que:
- un signal numérique en bande de base (x) est obtenu à partir du signal radiodiffusé démodulé (ds) par démodulation additionnelle et conversion analogique-numérique;
- le signal numérique (x) est appliqué à un premier, à un deuxième et à un troisième trajet de signal (a, b, c), d'une part, pour chaque fréquence de tonalité de message (fa; fa1, fa2) et, d'autre part, pour des fréquences (fb, fc; fb1, fb2; fc1, fc2) différant respectivement de la fréquence de la tonalité de message de + 1 % et -1 % au plus, chacun de ces trajets de signal étant constitué, dans le sens de progression du signal, d'un filtre accordé numérique (ra, rb, rc) accordé sur la fréquence correspondante (fa, fb, fc; fa1, fb1, fc1; fa2, fb2, fc2), un étage de valeur absolue numérique (ba, bb, bc) et un filtre passe-bas numérique (pa, pb, pc) ayant une fréquence de coupure supérieure inférieure à deux fois la fréquence de message (fa), les trois filtres accordés (ra, rb, rc), ayant la même largeur de bande et le même facteur de résonance;
- le signal numérique (x) est appliqué à un agencement en série d'un premier et d'un deuxième filtre passe-bas numérique additionnel (p 1, p2) ayant des fréquences de coupure supérieures respectivement égales à celle du filtre passe-bas numérique (pa, pb, pc) et à la fréquence correspondant à la constante de temps de transition des filtres accordés (ra, rb, rc);
- le premier trajet de signal (a) conduit à l'entrée de terme principal (m) de premier, deuxième, troisième et quatrième comparateurs numériques (k1, k2, k3, k4) parmi lesquels l'entrée de terme à soustraire (s) du premier comparateur (k1) est connectée, par un premier multiplicateur par une constante (m1), à à la sortie du deuxième filtre passe-bas additionnel (p2) et celle du deuxième comparateur (k2) est connecté à la sortie du deuxième filtre passe-bas additionnel (p2) par l'intermédiaire d'un deuxième multiplicateur par une constante (m2), tandis que les entrées de terme à soustraire (s) des troisième et quatrième comparateurs (k3, k4) sont respectivement connectées aux sorties du deuxième trajet de signal (b) et du troisième trajet de signal (c);
- la sortie de terme principal supérieur au terme à soustraire (m > s) du premier comparateur (k1) est couplée à l'entrée S d'une bascule RS (ff) fournissant le signal de message binaire (dk) sur sa sortie Q;
- les sorties de terme principal inférieur au terme à soustraire (m<s) des deuxième, troisième et quatrième comparateurs (k2, k3, k4) sont couplées, par une porte OU (og) à l'entrée R de la bascule RS (ff), et
- les constantes (d 1, d2) des multiplicateurs par une constante (m 1, m2) sont chacune inférieure à un et, l'une, égale au facteur de modulation nominal du signal d'identification de message, tandis que l'autre est égale à une fraction préréglable du facteur de modulation nominal.
2. Circuit intégré selon la revendication 1, caractérisé en ce que, pour la démodulation additionnelle et la conversion analogique-numérique:
- le signal radiodiffusé démodulé (ds) est fourni à un mélangeur (ms) auquel est appliquée la fréquence (fm) d'un oscillateur local, supérieure à la somme de la fréquence de message (fa) et de sa fréquence porteuse, et
- la sortie du mélangeur (ms) est couplée à l'entrée d'un convertisseur analogique-numérique (aw) par l'intermédiaire d'un filtre passe-bas analogique (af) ayant une fréquence de coupure supérieure égale au plus à la moitié de la fréquence du signal d'échantillonnage (ft) du convertisseur analogique-numérique (aw), dont la sortie est connectée à l'entrée d'un étage de valeur absolue numérique additionnel (br).
EP84106270A 1984-06-01 1984-06-01 Circuit intégré pour décoder le signal d'identification des communiqués pour le trafic radio Expired EP0162943B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE8484106270T DE3467648D1 (en) 1984-06-01 1984-06-01 Integrated circuit for decoding traffic radio announcement identification signals
EP84106270A EP0162943B1 (fr) 1984-06-01 1984-06-01 Circuit intégré pour décoder le signal d'identification des communiqués pour le trafic radio
US06/736,633 US4633517A (en) 1984-06-01 1985-05-21 Circuit for decoding traffic information message tone signals
JP60115520A JPS60264128A (ja) 1984-06-01 1985-05-30 トラフイツク情報メツセージトーン信号のデコード用回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP84106270A EP0162943B1 (fr) 1984-06-01 1984-06-01 Circuit intégré pour décoder le signal d'identification des communiqués pour le trafic radio

Publications (2)

Publication Number Publication Date
EP0162943A1 EP0162943A1 (fr) 1985-12-04
EP0162943B1 true EP0162943B1 (fr) 1987-11-19

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EP84106270A Expired EP0162943B1 (fr) 1984-06-01 1984-06-01 Circuit intégré pour décoder le signal d'identification des communiqués pour le trafic radio

Country Status (4)

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US (1) US4633517A (fr)
EP (1) EP0162943B1 (fr)
JP (1) JPS60264128A (fr)
DE (1) DE3467648D1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3709523A1 (de) * 1987-03-23 1988-10-13 Bosch Gmbh Robert Rundfunkempfaenger mit mindestens einem verkehrsfunkdecoder
US5007069A (en) * 1987-11-13 1991-04-09 Talkie Tooter Inc. Decoding of signals using cophase and differentiating signal detection
US4962457A (en) * 1988-10-25 1990-10-09 The University Of Michigan Intelligent vehicle-highway system
US5164904A (en) * 1990-07-26 1992-11-17 Farradyne Systems, Inc. In-vehicle traffic congestion information system
JP3258171B2 (ja) * 1994-06-08 2002-02-18 パイオニア株式会社 Ｐｔｙバースト信号の検出方法
US5900825A (en) * 1996-08-01 1999-05-04 Manitto Technologies, Inc. System and method for communicating location and direction specific information to a vehicle
US7908080B2 (en) 2004-12-31 2011-03-15 Google Inc. Transportation routing

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3007907A1 (de) * 1980-03-01 1981-09-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Digitaler empfaenger
JPS5765025A (en) * 1980-10-08 1982-04-20 Pioneer Electronic Corp Receiver for traffic informatin
DE3121034C2 (de) * 1981-05-27 1987-01-02 Blaupunkt-Werke Gmbh, 3200 Hildesheim UKW-Empfänger
DE3233829A1 (de) * 1982-09-11 1984-03-15 Blaupunkt-Werke Gmbh, 3200 Hildesheim Verfahren zur demodulation amplitudenmodilierter eingangssignale und schaltungsanordnung hierfuer
US4561115A (en) * 1984-03-08 1985-12-24 Itt Industries, Inc. Decoder for traffic information regional tone signals

Also Published As

Publication number Publication date
US4633517A (en) 1986-12-30
EP0162943A1 (fr) 1985-12-04
JPS60264128A (ja) 1985-12-27
DE3467648D1 (en) 1987-12-23
JPH0423966B2 (fr) 1992-04-23

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