EP0119280A1 - Integrated circuit for decoding radio broadcast traffic area identification signals - Google Patents

Integrated circuit for decoding radio broadcast traffic area identification signals Download PDF

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Publication number
EP0119280A1
EP0119280A1 EP83102412A EP83102412A EP0119280A1 EP 0119280 A1 EP0119280 A1 EP 0119280A1 EP 83102412 A EP83102412 A EP 83102412A EP 83102412 A EP83102412 A EP 83102412A EP 0119280 A1 EP0119280 A1 EP 0119280A1
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EP
European Patent Office
Prior art keywords
output
input
comparator
frequency
digital
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EP83102412A
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German (de)
French (fr)
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EP0119280B1 (en
Inventor
Heinrich Dipl.-Ing. Pfeifer
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TDK Micronas GmbH
ITT Inc
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Deutsche ITT Industries GmbH
ITT Industries Inc
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Priority to EP83102412A priority Critical patent/EP0119280B1/en
Priority to DE8383102412T priority patent/DE3364612D1/en
Priority to JP59045725A priority patent/JPS59175221A/en
Publication of EP0119280A1 publication Critical patent/EP0119280A1/en
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Publication of EP0119280B1 publication Critical patent/EP0119280B1/en
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/09—Arrangements for giving variable traffic instructions
    • G08G1/091—Traffic information broadcasting
    • G08G1/094—Hardware aspects; Signal processing or signal properties, e.g. frequency bands

Definitions

  • the invention relates to an integrated circuit for decoding traffic radio area identification signals, the frequency, the area frequency, of which is information about the area, the area identification signals being contained in the form of a carrier signal amplitude-modulated therewith in a received radio signal already demodulated in a conventional radio receiver, cf. . the preamble of claim 1.
  • the traffic radio signal contains area identification signals.
  • area identification signals the frequency of which is the information about the area as the area frequency, are quite low-frequency signals and are modulated onto the carrier signal by means of amplitude modulation, which has a frequency of 57 kHz in the known system, and are otherwise by ? possible frequency division derived from the carrier signal.
  • the block diagram of an integrated circuit for decoding traffic information signals according to the invention is shown in FIG. 1.
  • the demodulated radio signal ds which is obtained by means of a conventional radio receiver, is fed to the mixer stage ms, whose mixed signal frequency fm is greater than the largest range frequency fb.
  • 5 Hz fm 2 23:
  • the mixing stage ms the area identification signals modulated onto the carrier signal are converted to the mixed signal frequency fm.
  • the output of the mixer stage ms is via the analog low-pass filter af at the input of the analog / digital converter aw.
  • the output of the analog-digital converter aw is also at the first input of the multiplier m, the second input of which is at the output of the digital clamping circuit kl, which is downstream of the digital bandpass filter bp in terms of signal flow. It clamps positive or negative input signals to the positive or negative maximum value specified by their number of digits.
  • the analog-digital converter aw which must then be a delta-sigma converter, can directly follow the mixing stage ms, whereby then, however, the digital low-pass filter df must be arranged between the input of the digital bandpass filter bp and the output of the analog-digital converter aw.
  • the mixed signal is recovered by means of the digital bandpass, and by means of the digital clamping circuit kl amplitude normalized.
  • the area identification signals are then demodulated by means of the multiplier m.
  • each signal path in the signal flow direction consists of the digital resonance filter ra, rb, rf for the respective range frequency fb, the digital absolute value generator ba, bb, bf and the digital low-pass filter pa, pb, pf, the upper limit frequency of which is less than twice the smallest range frequency.
  • this lowest range frequency which is assigned to range A there, has a value of 23.75 Hz.
  • the three subcircuits arranged in signal path a, b, f have the function of a selective level measurement.
  • One of each of the outputs of the low-pass filters pa, pb, pf is connected to an input of the multiple comparator vk, at the first maximum output mx1 of which a signal occurs via the signal path which carries the largest signal, i.e. a digital word for the number of the signal path with the largest signal value appears at the first maximum output mx1.
  • a signal appears at the second maximum output mx2 about the number of the signal path that carries the second largest signal.
  • D T r first or second maximum output mx1, mx2 is located at the control input of the first or second electronic multiple switch s1, s2, the inputs of which are each connected to an output of the low-pass filters pa, pb, pf.
  • the two multiple switches s1, s2 thus have as many inputs as there are signal paths, and from the output signals to the maximum outputs mxl, mx2, they are switched to the signal path that carries the largest or the second largest signal value.
  • the output of the first multiple switch s1 is on the one hand via the first constant multiplier m1 at the minuend input of the first comparator k1, to the subtrahend input of which the output of the multiple adder ad is connected. Its inputs are located at the output of one of the low passes pa, pb, pf.
  • the output of the first multiple changeover switch s1 is also via the second constant multiplier m2 at the minuend input of the second comparator k2, to the subtrahend input of which the output of the second multiple changeover switch s2 is connected.
  • the second comparator k2 and the second comparator m2 determine whether the amplitude of the first maximum signal multiplied by a constant factor is greater than the second maximum signal. By means of these constants provided in the second constant multiplier m2 as the one multiplication factor, the external channel spacing can be determined.
  • the level of the first maximum signal is compared in a comparable manner with the sum of the signal values of the other signal paths, which is a signal-to-noise ratio measurement.
  • the delay element vg is located at the first maximum output mx1 of the multiple comparator k and at the output thereof the minuend input of the third comparator k3, the subtrahend input of which is connected to the first maximum output mx1.
  • the minute-equal-subtrahend output of the third comparator k3 is via the inverter it Reset input er of the counter z, the counter input of which is supplied with the clock signal t and the counter outputs of which are connected to the minuend input of the fourth comparator k4, the subtrahend input of which is supplied the constant k serving as threshold value.
  • the output of the digital bandpass bp is followed by the further absolute value generator bw, which is followed by the further digital low-pass filter pw, the upper limit frequency of which is equal to that of the low-pass filters pa, pb, pf and the output of which via the third or fourth constant multiplier m3, m4 is at the subtrahend input of the fifth or the sixth comparator k5, k6, whose respective minuend input is connected to the output of the first multiple switch s1.
  • the minuend-larger-subtrahend output of the fifth comparator k5 and the minuend-smaller-subtrahend output of the sixth comparator k6 are each connected to one of the two inputs of the first AND gate u1.
  • the degree of modulation of the area identification signals is monitored by means of the last-mentioned subcircuits bw, pw, m3, m4, k5, k6, u1, because noise manifests itself as an increased degree of modulation and, on the other hand, an unmodulated carrier likewise frequently occurs as a disturbance.
  • the first maximum signal is compared with the amplitude of the mixed signal with respect to an upper and a lower threshold, which are predetermined by the constants of the third and fourth constant multipliers m3, m4.
  • the second AND gate u2 Of the four inputs of the second AND gate u2, one is located at the respective minuend-greater-subtrahend output of the first comparator k1, the second comparator k2 and the fourth comparator k4 and at the output of the first AND gate u1.
  • the first maximum output mx1 of the multiple comparator vk is located at the parallel input of the multiple AND gate vu, the output of which is the area signal output ba of the integrated circuit, and the output of the second AND gate u2 is located at all points of the second parallel input of the multiple AND -Gatters vu.
  • the mixer stage ms which consists of the unit amplifier v1 and the electronic switch s, the control signal of which is the mixed signal fm.
  • the unit amplifier v1 has the gain 1 and outputs at its output like a conventional analog amplifier an output signal rotated by 180 ° with respect to its input signal.
  • the radio signal ds which is also located at the input of the unit amplifier v1 is switched through directly to the output of the switch s, once and once in its form rotated by 180 °, that is to say inverted.
  • the mixed signal fm is a square wave signal.

Abstract

1. Integrated Circuit for decoding traffic information regional tone signals whose frequency, the regional tone frequency, is the information on the region, the regional tone signals being contained in the form of a carrier amplitude-modulated therewith in a received broadcast signal which has already been demodulated in a conventional radio receiver (ds), characterized by the following features : - The demodulated broadcast signal (ds) is fed to a mixer (ms) whose local-oscillator frequency (fm) is higher than the highest regional tone frequency ; - the output of the mixer (ms) is coupled to the input of an analog-to-digital converter (aw) through an analog low-pass filter (af) whose upper cutoff frequency is not higher than half the sampling frequency (fa) of the analog-to-digital converter (aw) ; - the output of the analog-to-digital converter (aw) is coupled to the input of a digital band-pass filter (bp) whose mid-frequency (fc) is equal to the difference between the carrier frequency (ft) and local-oscillator frequency (fm), and to the first input of a multiplier (m) having its second input connected to the output of a digital clamping circuit (kl) whose input is connected to the output of the digital band-pass filter (bp), and which clamps positive and negative input signals to the positive and negative maximum values, respectively, which are determined by the numbers of digits of said input signals ; - the multiplier (m) is followed by several signal paths (a, b, f), one for each regional tone frequency, each of which consists of a digital resonance filter (ra, rb, rf) followed by a digital absolue value former (ba, bb, bf) and a digital low-pass filter (pa, pb, pf) whose upper cutoff frequency is smaller than twice the smallest regional tone frequency ; - each of the low-pass filters (pa, pb, pf) has one its outputs connected to one of the inputs of a multiple comparator (vk) whose first and second maximum outputs (mx1, mx2) are connected to the control inputs of a first electronic multiple switch (s1) and a second electronic multiple switch (s2), respectively ; - of each of the inputs of the first and second electronic multiple switches (s1, s2) one is connected to one of the outputs of one of the low-pass filter (pa, pb, pf) ; - the first maximum switch (s1) is connected to the input with the first maximum value by the first maximum output (mx1), and the second multiple switch (s2) is connected to the input with the second maximum value by the second maximum output (mx2) ; - the output of the first multiple switch (s1) is coupled through a first constant multiplier (m1) to the minuend input of a first comparator (k1) having its substrahend input connected to the output of a multiple adder (ad) which has one of each of its inputs connected to the output of one of the low-pass filters (pa, pb, pf), an through a second constant multiplier (m2) to the minuend input of a second comparator (k2) having its subtrahend input connected to the output of the second multiple switch (s2) ; - the first maximum output (mx1) of the multiple comparator (vk) is connected to a delay element (vg) which feeds the minuend input of a third comparator (k3) having its subtrahend input connected to the first maximum output (mx1) ; - the minuend-equal-to-subtrahend output of the third comparator (k3) is coupled through an inverter (it) to the reset input (er) of a counter (z) whose count input is fed with a clock signal (t) and whose outputs are connected to the minuend input of a fourth comparator (k4) whose subtrahend input is fed with a constant (k) serving as a threshold value ; - the digital band-pass filter (bp) is followed by an addional digital absolute-value former (bw) followed, in turn, by an additional digital low-pass filter (pw) whose upper cutoff frequency is equal to that of the low-pass filter (pa, pb, pf), and whose output is coupled through third and fourth constant multipliers (m3, m4) to the subtrahend inputs of a fifth comparator (k5) and a sixth comparator (k6), respectively, which have their minuend inputs connected to the output of the first multiple switch (s1) ; - the minuend-greater-than-subtrahend output of the fifth comparator (k5) and the minuend-smaller-than-subtrahend output of the sixth comparator (k6) are each connected to one of the two inputs of a first AND gate (u1) ; - the four inputs of the second AND gate (u2) are connected, respectively, to the minuend-greater-than-subtrahend outputs of the first comparator (k1), the second comparator (k2), and the fourth comparator (k4), and to the output of the first AND gate (u1), and - the first maximum output (mx1) of the multiple comparator (vk) is connected to the first parallel input of a multiple AND gate (vu) whose output is the regional-tone-signal output (sa) of the integrated circuit, and the output of the second AND gate (u2) is connected to all terminals of the second parallel input of the multiple AND gate (vu).

Description

Die Erfindung betrifft eine integrierte Schaltung zur Decodierung von Verkehrsfunk -Bereichskennsignalen, deren Frequenz, die Bereichsfrequenz, die Information über den Bereich ist, wobei die Bereichskennsignale in Form eines damit amplitudenmodulierten Trägersignals in einem empfangenen und in einem üblichen Rundfunkempfänger bereits demodulierten Rundfunksignal enthalten sind, vgl. den Oberbegriff des Anspruchs 1.The invention relates to an integrated circuit for decoding traffic radio area identification signals, the frequency, the area frequency, of which is information about the area, the area identification signals being contained in the form of a carrier signal amplitude-modulated therewith in a received radio signal already demodulated in a conventional radio receiver, cf. . the preamble of claim 1.

In der Zeitschrift "Funkschau", 1974, Seiten 535 bis 538 ist das derzeit in Deutschland und weiteren europäischen Ländern verwendete System zur übermittlung von Verkehrsdurchsagen an Rundfunkhörer beschrieben, wobei unter anderem vorgesehen ist, das Gebiet eines Staates in mehrere Verkehrsfunk-Sendebereich3 dadurch aufzuteilen, daß das Verkehrsfunksignal Bereichskennsignale enthält. Diese Bereichskennsignale, deren Frequenz als Bereichsfrequenz die Information über den Bereich ist, sind recht niederfrequente Signale und mittels Amplitudenmodulation dem Trägersignal, das beim bekannten System eine Frequenz von 57 kHz hat, aufmoduliert und werden im übrigen durch ganz- ?ahlige Frequenzteilung aus dem Trägersignal abgeleitet.In the magazine "Funkschau", 1974, pages 535 to 538, the system currently used in Germany and other European countries for the transmission of traffic announcements to radio listeners is described, it being provided, among other things, to divide the area of a state into several traffic radio broadcasting areas 3, that the traffic radio signal contains area identification signals. These area identification signals, the frequency of which is the information about the area as the area frequency, are quite low-frequency signals and are modulated onto the carrier signal by means of amplitude modulation, which has a frequency of 57 kHz in the known system, and are otherwise by ? possible frequency division derived from the carrier signal.

Wie der Zeitschrift Rundfunktechnische Mitteilungen" 1974, Seiten 193 bis 202, worin dieses Verkehrsfunk-System ebenfalls ausführlich beschrieben ist, entnommen werden kann, wurden die Systemparameter seinerzeit so gewählt, daß die für den Verkehrsfunk erforderlichen empfängerseitigen Decoderschaltungen mit den üblichen, analoge Signale verarbeitenden Empfängerschaltungen kompatibel sind und insbesondere keine gegenseitige Störung auftritt. Die bisher üblichen Decoderschaltungen sind daher ebenfalls Analogschaltungen.As can be seen from the magazine Rundfunk Technische Mitteilungen "1974, pages 193 to 202, in which this traffic radio system is also described in detail, the system parameters were chosen in such a way that the receivers required for traffic radio side decoder circuits are compatible with the usual analog signal processing receiver circuits and in particular no mutual interference occurs. The previously common decoder circuits are therefore also analog circuits.

Demgegenüber ist es Aufgabe der in den Ansprüchen gekennzeichneten Erfindung, eine integrierte Schaltung zur Decodierung von Verkehrsfunk-Bereichskennsignalen anzugeben, die nach den Prinzipien der Digitaltechnik arbeitet und somit weitgehend aus digitalen Teilschaltungen aufgebaut ist. Dabei soll die Ansprechzeit der Schaltung kleiner als eine Sekunde sein:und die Bereichserkennung soll unempfindlich gegenüber Rauschen sein. *z.B. 300 ms betragen,In contrast, it is an object of the invention characterized in the claims to provide an integrated circuit for decoding traffic area code signals, which operates according to the principles of digital technology and is thus largely constructed from digital subcircuits. The response time of the circuit should be less than one second: and the area detection should be insensitive to noise. * e.g. 300 ms,

Die Erfindung und ihre Vorteile werden nun anhand der Figuren der Zeichnung näher erläutert.

  • Fig. 1 zeigt in Form eines Blockschaltbilds den Aufbau eines Ausführungsbeispiels der Erfindung,
  • Fig. 2 zeigt den geringfügig modifizierten Eingangsteil der Anordnung nach Fig. 1 und
  • Fig. 3 zeigt schematisch den Aufbau einer bei der Erfindung vorteilhaft verwendbaren Mischstufe.
The invention and its advantages will now be explained in more detail with reference to the figures of the drawing.
  • 1 shows in the form of a block diagram the structure of an embodiment of the invention,
  • Fig. 2 shows the slightly modified input part of the arrangement according to Fig. 1 and
  • 3 schematically shows the structure of a mixing stage which can advantageously be used in the invention.

Als Ausführungsbeispiel ist in Fig. 1 das Blockschaltbild einer integrierten Schaltung zur Decodierung von Verkehrsfunk-Bereichskennsignalen nach der Erfindung gezeigt. Das demodulierte Rundfunksignal ds, das mittels eines üblichen Rundfunkempfängers gewonnen wird, ist der Mischstufe ms zugeführt, deren Mischsignal-Frequenz fm größer als die größte Bereichsfrequenz fb ist. Bezogen auf das in den eingangs genannten beiden Zeitschriften bekannte System bedeutet dies, daß die Mischsignalfrequenz fm größer als die dem Bereich F zugeordnete Bereichsfrequenz 53,98 Hz ist. In einer realisierten Schaltung gilt für die Mischsignalfrequenz: fm = 223,5 Hz. Mittels der Mischstufe ms werden die dem Trägersignal aufmodulierten Bereichskennsignale auf die Mischsignalfrequenz fm umgesetzt.As an exemplary embodiment, the block diagram of an integrated circuit for decoding traffic information signals according to the invention is shown in FIG. 1. The demodulated radio signal ds, which is obtained by means of a conventional radio receiver, is fed to the mixer stage ms, whose mixed signal frequency fm is greater than the largest range frequency fb. In relation to the system known in the two magazines mentioned at the beginning, this means that the mixed signal frequency fm is greater than the range frequency associated with range F is 53.98 Hz. , 5 Hz fm = 2 23: In a realized circuit applies to the mixing signal frequency. Using the mixing stage ms, the area identification signals modulated onto the carrier signal are converted to the mixed signal frequency fm.

Der Ausgang der Mischstufe ms liegt über das analoge Tiefpaßfilter af am Eingang des Analog/Digital-Wandlers aw. Dabei ist die obere Grenzfrequenz des Tiefpaßfilters af höchstens gleich der halben Abtastfrequenz des Analog/ Digital-Wandlers aw. Sein Ausgang liegt am Eingang des digitalen Bandpasses bp, dessen Mittenfrequenz fc gleich der Differenz von Trägersignalfrequenz ft und Mischsignalfrequenz fm ist; es gilt also fc = ft - fm.The output of the mixer stage ms is via the analog low-pass filter af at the input of the analog / digital converter aw. The upper cut-off frequency of the low-pass filter af is at most equal to half the sampling frequency of the analog / digital converter aw. Its output is at the input of the digital bandpass filter bp, whose center frequency fc is equal to the difference between the carrier signal frequency ft and the mixed signal frequency fm; therefore fc = ft - fm.

Dor Ausgang des Analog Digital-Wandlers aw liegt ferner am ersten Eingang des Multiplizierers m, dessen zweiter Eingang am Ausgang der Digitalklemmschaltung kl liegt, die dem digitalen Bandpaß bp signalflußmäßig nachgeordnet ist. Sie klemmt positive bzw. negative Eingangssignale auf den durch ihre Stellenzahl vorgegebenen positiven bzw. negativen Maximalwert.The output of the analog-digital converter aw is also at the first input of the multiplier m, the second input of which is at the output of the digital clamping circuit kl, which is downstream of the digital bandpass filter bp in terms of signal flow. It clamps positive or negative input signals to the positive or negative maximum value specified by their number of digits.

An dieser Stelle sei bereits erwähnt, daß nach der in Fig. 2 ausschnittweise gezeigten Abwandlung der Anordnung nach Fig. 1 der Analog Digital-Wandlers aw,der dann ein Delta-Sigma-Wandler sein muß, direkt auf die Mischstufe ms folgen kann, wobei dann allerdings zwischen dem Eingang des digitalen Bandpasses bp und dem Ausgang des Analog-Digitalwandlers aw das digitale Tiefpaßfilter df anzuordnen ist.At this point it should be mentioned that after the modification of the arrangement according to FIG. 1 shown in detail in FIG. 2, the analog-digital converter aw, which must then be a delta-sigma converter, can directly follow the mixing stage ms, whereby then, however, the digital low-pass filter df must be arranged between the input of the digital bandpass filter bp and the output of the analog-digital converter aw.

Mittels des digitalen Bandpasses wird das Mischsignal zurückgewonnen, und mittels der Digitalklemmschaltung kl wird es amplitudennormiert. Mittels des Multiplizierers m werden dann die Bereichskennsignale demoduliert.The mixed signal is recovered by means of the digital bandpass, and by means of the digital clamping circuit kl amplitude normalized. The area identification signals are then demodulated by means of the multiplier m.

Am Ausgang des Multiplizierers m liegt für jede Bereichsfrequenz ein eigener Signalweg, wovon in Fig. 1 die Signalwege a, b, f gezeigt sind. Jeder Signalweg besteht in Signalflußrichtung aus dem digitalen Resonanzfilter ra, rb, rf für die jeweilige Bereichsfrequenz fb, dem digitalen Betragsbildner ba, bb, bf und dem digitalen Tiefpaß pa, pb, pf, dessen obere Grenzfrequenz kleiner als die doppelte kleinste Bereichsfrequenz ist. Bei dem eingangs geschilderten bekannten System hat diese niedrigste Bereichsfrequenz, die dort dem Bereich A zugeordnet ist, einen Wert von 23,75 Hz. Die in dem Signalweg a, b, f angeordneten drei Teilschaltungen haben die Funktion einer selektiven Pegelmessung.At the output of the multiplier m there is a separate signal path for each range frequency, of which the signal paths a, b, f are shown in FIG. 1. Each signal path in the signal flow direction consists of the digital resonance filter ra, rb, rf for the respective range frequency fb, the digital absolute value generator ba, bb, bf and the digital low-pass filter pa, pb, pf, the upper limit frequency of which is less than twice the smallest range frequency. In the known system described at the outset, this lowest range frequency, which is assigned to range A there, has a value of 23.75 Hz. The three subcircuits arranged in signal path a, b, f have the function of a selective level measurement.

Von den Ausgängen der Tiefpässe pa, pb, pf liegt jeweils einer an jeweils einem Eingang des Vielfachkomparators vk, an dessen erstem Maximum-Ausgang mx1 ein Signal über denjenigen Signalweg auftritt, der-das grösste Signal führt, d.h. also am ersten Maximum-Ausgang mx1 erscheint ein Digitalwort für die Nummer des Signalwegs mit dem grössten Signalwert. In gleicher Weise erscheint am zweiten Maximum-Ausgang mx2 ein Signal über die Nummer desjenigen Signalwegs, der das zweitgrösste Signal führt.One of each of the outputs of the low-pass filters pa, pb, pf is connected to an input of the multiple comparator vk, at the first maximum output mx1 of which a signal occurs via the signal path which carries the largest signal, i.e. a digital word for the number of the signal path with the largest signal value appears at the first maximum output mx1. In the same way, a signal appears at the second maximum output mx2 about the number of the signal path that carries the second largest signal.

DTr erste bzw. der zweite Maximum-Ausgang mx1, mx2 liegt am Steuereingang des ersten bzw. des zweiten elektronischen Vielfachumschalters s1, s2, von deren Eingängen jeweils einer an je einem Ausgang der Tiefpässe pa, pb, pf angeschlossen ist. Die beiden Vielfachumschalter s1, s2 haben also so viele Eingänge, wie Signalwege vorhanden sind, und von den Ausgangssignalen an den Maximum-Ausgängen mxl, mx2 werden sie auf denjenigen Signalweg geschaltet, der den grössten bzw. den zweitgrössten Signalwert führt.D T r first or second maximum output mx1, mx2 is located at the control input of the first or second electronic multiple switch s1, s2, the inputs of which are each connected to an output of the low-pass filters pa, pb, pf. The two multiple switches s1, s2 thus have as many inputs as there are signal paths, and from the output signals to the maximum outputs mxl, mx2, they are switched to the signal path that carries the largest or the second largest signal value.

Der Ausgang des ersten Vielfachumschalters s1 liegt einerseits über den ersten Konstanten-Multiplizierer m1 am Minuend-Eingang des ersten Komparators k1, an dessen Subtrahend-Eingang der Ausgang des Vielfachaddierers ad angeschlossen ist. Dessen Eingänge liegen jeweils am Ausgang eines der Tiefpässe pa, pb, pf. Der Ausgang des ersten Vielfachumschalters s1 liegt ferner über den zweiten onstanten-Multiplizierer m2 am Minuend-Eingang des zweiten Komparators k2, an dessen Subtrahend-Eingang der Ausgang des zweiten Vielfachumschalters s2 angeschlossen ist.The output of the first multiple switch s1 is on the one hand via the first constant multiplier m1 at the minuend input of the first comparator k1, to the subtrahend input of which the output of the multiple adder ad is connected. Its inputs are located at the output of one of the low passes pa, pb, pf. The output of the first multiple changeover switch s1 is also via the second constant multiplier m2 at the minuend input of the second comparator k2, to the subtrahend input of which the output of the second multiple changeover switch s2 is connected.

Mittels des zweiten Komparators k2 und des zweiten Kons ant-Miltiplizierers m2 wird festgestellt, ob die mit einem konstanten Faktor multiplizierte Amplitude des ersten Maximumsignals größer ist als das zweite Maximumsignal. Mittels dieser im zweiten Konstanten-Multiplizierer m2 als der eine Multiplikationsfaktor vorgesehenen Konstanten läßt sich also der Fremdkanalabstand festlegen.The second comparator k2 and the second comparator m2 determine whether the amplitude of the first maximum signal multiplied by a constant factor is greater than the second maximum signal. By means of these constants provided in the second constant multiplier m2 as the one multiplication factor, the external channel spacing can be determined.

Mittels des ersten Konstanten-Multiplizierers m1 und des ersten Komparators k1 wird in vergleichbarer Weise der Pegel des ersten Maximumsignals mit der Summe der Signalwerte der übrigen Signalwege verglichen, was eine Störabstandmessung ist.By means of the first constant multiplier m1 and the first comparator k1, the level of the first maximum signal is compared in a comparable manner with the sum of the signal values of the other signal paths, which is a signal-to-noise ratio measurement.

Am ersten Maximum-Ausgang mx1 des Vielfachkomparators k liegt das Verzögerungsglied vg und an dessen Ausgang der Minuend-Eingang des dritten Komparators k3, dessen Subtrahend-Eingang mit dem ersten Maximum-Ausgang mx1 verbunden ist. Der Minuend-gleich-Subtrahend-Ausganj des dritten Komparators k3 liegt über den Inverter it am Rücksetzeingang er des Zählers z, dessen Zähleingang das Taktsignal t zugeführt ist und dessen Zählerstandausgänge mit dem Minuend-Eingang des vierten Komparators k4 verbunden sind, dessen Subtrahend-Eingang die als Schwellwert dienende Konstante k zugeführt ist. Mit den eben erläuterten Teilschaltungen vg, k3, it, z, k4 wird am Minuend-größer-Subtrahend-Ausgang des vierten Komparators k4 ein Signal erzeugt, das nur dann auftritt, wenn das erste Maximumsignal für die durch die Frequenz des Taktsignals t und die Konstante k vorgegebene Zeit konstant war. Mittels dieser Teilschaltungen ist somit eine Zeitschwelle realisiert.The delay element vg is located at the first maximum output mx1 of the multiple comparator k and at the output thereof the minuend input of the third comparator k3, the subtrahend input of which is connected to the first maximum output mx1. The minute-equal-subtrahend output of the third comparator k3 is via the inverter it Reset input er of the counter z, the counter input of which is supplied with the clock signal t and the counter outputs of which are connected to the minuend input of the fourth comparator k4, the subtrahend input of which is supplied the constant k serving as threshold value. With the sub-circuits vg, k3, it, z, k4 just explained, a signal is generated at the minor-subtrahend output of the fourth comparator k4, which signal only occurs when the first maximum signal for the frequency of the clock signal t and the Constant k predetermined time was constant. A time threshold is thus realized by means of these subcircuits.

Dem Ausgang des digitalen Bandpasses bp ist der weitere Betragsbildner bw nachgeschaltet, dem der weitere digitale Tiefpaß pw folgt, dessen obere Grenzfrequenz gleich der der Tiefpässe pa, pb, pf ist und dessen Ausgang über den dritten bzw. den vierten Konstanten-Multiplizierer m3, m4 am Subtrahend-Eingang des fünften bzw. des sechsten Komparators k5, k6 liegt, deren jeweiliger Minuend-Eingang am Ausgang des ersten Vielfachumschalters s1 angeschlossen ist. Der Minuend-größer-Subtrahend-Ausgang des fünften Komparators k5 und der Minuend-kleiner-Subtrahend-Ausgang des sechsten Komparators k6 sind mit jeweils einem der beiden Eingänge des ersten UND-Gatters u1 verbunden. Mittels der zuletzt genannten Teilschaltungen bw, pw, m3, m4, k5, k6, u1 wird der Modulationsgrad der Bereichskennsignale überwacht, denn Rauschen äußert sich als vergrößerter Modulationsgrad, und andererseits tritt ein unmodulierter Träger ebenfalls häufig als Störung auf. Dabei wird das erste Maximalsignal mit der Amplitude des Mischsignals bezüglich einer oberen und einer unteren Schwelle, die durch die Konstanten des dritten bzw. vierten Konstanten-Multiplizierers m3, m4 vorgegeben sind, verglichen.The output of the digital bandpass bp is followed by the further absolute value generator bw, which is followed by the further digital low-pass filter pw, the upper limit frequency of which is equal to that of the low-pass filters pa, pb, pf and the output of which via the third or fourth constant multiplier m3, m4 is at the subtrahend input of the fifth or the sixth comparator k5, k6, whose respective minuend input is connected to the output of the first multiple switch s1. The minuend-larger-subtrahend output of the fifth comparator k5 and the minuend-smaller-subtrahend output of the sixth comparator k6 are each connected to one of the two inputs of the first AND gate u1. The degree of modulation of the area identification signals is monitored by means of the last-mentioned subcircuits bw, pw, m3, m4, k5, k6, u1, because noise manifests itself as an increased degree of modulation and, on the other hand, an unmodulated carrier likewise frequently occurs as a disturbance. The first maximum signal is compared with the amplitude of the mixed signal with respect to an upper and a lower threshold, which are predetermined by the constants of the third and fourth constant multipliers m3, m4.

Von den vier Eingängen des zweiten UND-Gatters u2 liegt jeweils einer am jeweiligen Minuend-größer-Subtrahend-Ausgang des ersten Komparators k1, des zweiten Komparators k2 und des vierten Komparators k4 sowie am Ausgang des ersten UND-Gatters u1. Der erste Maximum-Ausgang mx1 des Vielfachkomparators vk liegt am Paralleleingang des Vielfach-UND-Gatters vu, dessen Ausgang der Bereichssignalausgang ba der integrierten Schaltung ist, und der Ausgang des zweiten UND-Gatters u2 liegt an allen Stellen des zweiten Paralleleingangs des Vielfach-UND-Gatters vu. Somit werden mittels des zweiten UND-Gatters u2 die vier Uberwachungskriterien auf ihr gleichzeitiges Auftreten geprüft, und nur wenn diese Forderung erfüllt ist,wird die Nummer des zugeordneten Bereichs an den Bereichssignalausgang sa durchgeschaltet.Of the four inputs of the second AND gate u2, one is located at the respective minuend-greater-subtrahend output of the first comparator k1, the second comparator k2 and the fourth comparator k4 and at the output of the first AND gate u1. The first maximum output mx1 of the multiple comparator vk is located at the parallel input of the multiple AND gate vu, the output of which is the area signal output ba of the integrated circuit, and the output of the second AND gate u2 is located at all points of the second parallel input of the multiple AND -Gatters vu. Thus, the four monitoring criteria are checked for their simultaneous occurrence by means of the second AND gate u2, and the number of the assigned area is only connected to the area signal output sa if this requirement is met.

Zur sicheren Ermittlung des Bereichskennsignals werden also bei der Erfindung vier Qualitätskriterien vorgegeben und erst bei deren gemeinsamem Vorliegen das decodierte Signal freigegeben. Diese vier Kriterien sind nochmals kurz zusammengefaßt die folgenden: Fremdkanalabstand, Summenkanalabstand, Modulationsgradüberwachung und vorgebbare Zeitschwelle. Obwohl diese vier überwachungskriterien einen gewissen Schaltungsaufwand bedingen, ergibt sich doch, und das ist einer der Vorteile der Erfindung, insgesamt eine Reduzierung der Ansprechzeit der Gesamtschaltung, ohne die Decodiersicherheit zu verringern. Außerdem ergibt sich eine praktisch vollständige Stör- und Rauschsicherheit der Schaltung.In order to reliably determine the area identification signal, four quality criteria are specified in the invention and the decoded signal is only released when they are present together. These four criteria are briefly summarized as follows: Foreign channel distance, sum channel distance, modulation degree monitoring and predefinable time threshold. Although these four monitoring criteria require a certain amount of circuitry, there is, and this is one of the advantages of the invention, an overall reduction in the response time of the overall circuit without reducing the decoding reliability. In addition, the circuit is virtually completely immune to interference and noise.

Die Fig. 3 zeigt eine besonders vorteilhafte Ausgestaltung für die Mischstufe ms, die aus dem Einheitsverstärker v1 und dem elektronischen Umschalter s, dessen Steuersignal das Mischsignal fm ist, besteht. Der Einheitsverstärker v1 hat die Verstärkung 1 und gibt an seinem Ausgang wie ein üblicher Analogverstärker ein um 180° gegenüber seinem Eingangssignal gedrehtes Ausgangssignal ab. Mittels des Umschalters s wird das auch am Eingang des Einheitsverstärkers v1 liegende Rundfunksignal ds einmal direkt und einmal in seiner um 180° gedrehten, also invertierten, Form zum Ausgang des Umschalters s durchgeschaltet. In diesem Fall ist das Mischsignal fm ein Rechtecksignal.3 shows a particularly advantageous embodiment for the mixer stage ms, which consists of the unit amplifier v1 and the electronic switch s, the control signal of which is the mixed signal fm. The unit amplifier v1 has the gain 1 and outputs at its output like a conventional analog amplifier an output signal rotated by 180 ° with respect to its input signal. By means of the switch s, the radio signal ds, which is also located at the input of the unit amplifier v1, is switched through directly to the output of the switch s, once and once in its form rotated by 180 °, that is to say inverted. In this case, the mixed signal fm is a square wave signal.

Claims (3)

1. Integrierte Schaltung zur Decodierung von Verkehrsfunk-Bereichskennsignalen, deren Frequenz, die Bereichsfrequenz, die Information über den Bereich ist, wobei die Bereichskennsignale in Form eines damit amplitudenmodulierten Trägersignals in einem empfangenen und mit einem üblichen Rundfunkempfänger bereits demodulierten Rundfunksignal(ds) enthalten sind, gekennzeichnet durch folgende Merkmale: - das demodulierte Rundfunksignal (ds) ist einer Mischstufe (ms) zugeführt, deren Mischsignal-Frequenz (fm) - größer als die größte Bereichsfrequenz ist, - der Ausgang der Mischstufe (ms) liegt über ein analoges Tiefpaßfilter (af) am Eingang eines Analog/Digital-Wandlers (aw), wobei die obere Grenzfrequenz des analogen Tiefpaßfilters (af) höchstens gleich der halben Abtastfrequenz (fa) des Analog/Digital-Wandlers (aw) ist, - der Ausgang des Analog/Digital-Wandlers (aw) liegt am Eingang eines digitalen Bandpasses (bp), dessen Mittenfrequenz (fc) gleich der Differenz von Trägersignalfrequenz (ft) und Mischsignalfrequenz (fm) ist, und ferner am ersten Eingang eines Multiplizierers (m), dessen zweiter Eingang am Ausgang einer Digital-Klemmschaltung (kl) liegt, deren Eingang mit dem Ausgang des digitalen Bandpasses (bp) verbunden ist und die positive bzw. negative Eingangssignale auf den durch ihre Stellenzahl vorgegebenen positiven bzw. negativen Maximalwert klemmt, - am Ausgang des Multiplizierers (m) liegt für jede Bereichsfrequenz ein eigener Signalweg (a, b, f), der in Signalflußrichtung aus einem digitalen Resonanzfilter (ra, rb, rf) für die jeweilige Bereichsfrequenz, einem digitalen Betragsbildner (ba, bb, bf) und einem digitalen Tiefpaß (pa, pb, pf) besteht, dessen obere Grenzfrequenz kleiner als die doppelte kleinste Bereichsfrequenz ist, - von den Ausgängen der Tiefpässe (ph, pb, pf) liegt jeweils einer an jeweils einem Eingang eines Vielfachkomparators (vk); dessen erster Maximum-Ausgang (mx1) am Steuereingang eines ersten elektronischen Vielfachumschalters (s1) und dessen zweiter Maximum-Ausgang (mx2) am Steuereingang eines zweiten elektronischen Vielfachumschalters (f2) liegt, - von den Eingängen des ersten und des zweiten elektronischen Vielfachumschalters (s1, s2) liegt jeweils einer an je einem Ausgang der Tiefpässe (pa, pb, pf), - der erste bzw. der zweite Vielfachumschalter (s1, s2) wird vom ersten bzw. vom zweiten Maximum-Ausgang mx1, mx2) auf den Eingang mit dem ersten bzw. zweiten Maximalwert geschaltet, - der Ausgang des ersten Vielfachumschalters (s1) liegt einerseits über einen ersten Konstanten-Multiplizierer (m1) am Minuend-Eingang eines ersten Komparators (k1), an dessen Subtrahend-Eingang der Ausgang eines Vielfach-Addierers(ad) angeschlossen ist,von dessen Eingängen jeweils einer mit dem Ausgang eines der Tiefpässe (pa, pb, pf) verbunden ist, und andererseits über einen zweiten Konstanten-Multiplizierer (m2) am Minuend-Eingang eines zweiten Komparators (k2), an dessen Subtrahend-Eingang der Ausgang des zweiten Vielfach-Umschalters (s2) angeschlossen ist, - am ersten Maximum-Ausgang (mx1) des Vielfachkomparators (vk) liegt ein Verzögerungsglied (vg) und an dessen Ausgang der Minuend-Eingang eines dritten Komparators (k3), dessen Subtrahend-Eingang mit dem ersten Maximum-Ausgang (mx1) verbunden ist, - der Minuend-gleich-Subtrahehd-Ausgang des dritten Komparators (k3) liegt über einen Inverter (it) am Rücksetzeingang (er) eines Zählers (z),dessen Zähleingang ein Taktsignal (t) zugeführt ist und dessen Zählerstandausgänge mit dem Minuend-Eingang eines vierten Komparatorst(k4) verbunden sind, dessen Subtrahend-Eingang eine als Schwellwert dienende Konstante (k) zugeführt ist, - dem Ausgang des digitalen Bandpasses (bp) ist ein weiterer Betragsbildner (bw) nachgeschaltet, auf den ein weiterer digitaler Tiefpaß (pw) folgt, dessen - obere Grenzfrequenz gleich der der Tiefpässe (pa, pw, pf) ist und dessen Ausgang über einen dritten bzw. über einen vierten Konstanten-Multiplizierer (m3, m4) am Subtrahend-Eingang eines fünften bzw. eines sechsten Komparators (k5, k6) liegt, deren jeweiliger Minuend-Eingang am Ausgang des ersten Vielfach-Umschalters (s1) angeschlossen ist, - der Minuend-größer-Subtrahend-Ausgang des fünften Komparators (k5) und der Minuend-kleiner-Subtrahend-Ausgang des sechsten Komparators (k6) sind mit jeweils einem der beiden Eingänge eines ersten UND-Gatters (u1) verbunden, - von den vier Eingängen eines-zweiten UND-Gatters (u2) liegt jeweils einer am jeweiligen Minuend-größer-Subtrahend-Ausgang des ersten Komparators (k1), des zweiten Komparators (k2) und des vierten Komparators (k4) bzw. am Ausgang des ersten UND-Gatters (u1), und - der erste Maximum-Ausgang (mx1) des Vielfachkomparators (vk) liegt am ersten Paralleleingang eines Vielfach-UND-Gatters (vu), dessen Ausgang der Bereichssignalausgang (sa) der integrierten Schaltung ist, und der Ausgang des zweiten UND-Gatters (u2) liegt an allen Stellen des zweiten Paralleleingangs des Vielfach-UND-Gatters (vu). 1. Integrated circuit for decoding traffic radio area identification signals whose frequency, the area frequency, is the information about the area, the area identification signals being contained in the form of an amplitude-modulated carrier signal in a received radio signal (ds) already demodulated with a conventional radio receiver, characterized by the following features: the demodulated broadcast signal (ds) is fed to a mixing stage (ms), the mixed signal frequency (fm) of which is greater than the greatest range frequency, - The output of the mixer (ms) is via an analog low-pass filter (af) at the input of an analog / digital converter (aw), the upper limit frequency of the analog low-pass filter (af) being at most equal to half the sampling frequency (fa) of the analog / digital -Wandlers (aw) is - The output of the analog / digital converter (aw) is at the input of a digital bandpass (bp), whose center frequency (fc) is equal to the difference between carrier signal frequency (ft) and mixed signal frequency (fm), and also at the first input of a multiplier ( m), the second input of which is at the output of a digital clamping circuit (kl), the input of which is connected to the output of the digital bandpass (bp) and the positive or negative input signals are clamped to the positive or negative maximum value specified by their number of digits, - at the output of the multiplier (m) is for each B ereichsfrequenz a separate signal path (a, b, f) located in the signal flow of a digital resonance filter (ra, rb, rf) for the respective field frequency, a digital absolute value former (ba, bb , bf) and a digital low-pass filter (pa, pb, pf), the upper limit frequency of which is less than twice the smallest range frequency, - One of the outputs of the low-pass filters (ph, pb, pf) is connected to an input of a multiple comparator (vk); whose first maximum output (mx1) is at the control input of a first electronic multiple switch (s1) and the second maximum output (mx2) is at the control input of a second electronic multiple switch (f2), one of the inputs of the first and the second electronic multiple switch (s1, s2) is located at an output of the low-pass filters (pa, pb, pf), the first or the second multiple changeover switch (s1, s2) is switched from the first or the second maximum output mx1, mx2) to the input with the first or second maximum value, - The output of the first multiple switch (s1) is on the one hand via a first constant multiplier (m1) at the minuend input of a first comparator (k1), to the subtrahend input of which the output of a multiple adder (ad) is connected, of which Inputs one each is connected to the output of one of the low-pass filters (pa, pb, pf), and on the other hand via a second constant multiplier (m2) at the minuend input of a second comparator (k2), at the subtrahend input of which the output of the second Multiple switch (s2) is connected, - at the first maximum output (mx1) of the multiple comparator tors (vk) is a delay element (vg) and at its output the minuend input of a third comparator (k3), whose subtrahend input is connected to the first maximum output (mx1), - The Minuend-equal-Subtrahehd output of the third comparator (k3) is via an inverter (it) at the reset input (er) of a counter (z), the counter input of which is supplied with a clock signal (t) and the counter outputs of which are connected to the minuend input a fourth comparator t (k4), whose subtrahend input is supplied with a constant (k) serving as a threshold value, - The output of the digital bandpass (bp) is followed by a further amount generator (bw), followed by another digital low-pass filter (pw), the upper limit frequency of which is equal to that of the low-pass filters (pa, pw, pf) and whose output is via a third or via a fourth constant multiplier (m3, m4) is located at the subtrahend input of a fifth or a sixth comparator (k5, k6), the respective minuend input of which is connected to the output of the first multiple switch (s1), the minuend-larger-subtrahend output of the fifth comparator (k5) and the minuend-smaller-subtrahend output of the sixth comparator (k6) are each connected to one of the two inputs of a first AND gate (u1), - Of the four inputs of a second AND gate (u2), one is located at the respective minuend-larger-subtrahend output of the first comparator (k1), the second comparator (k2) and the fourth comparator (k4) or at the output the first AND gate (u1), and - The first maximum output (mx1) of the multiple comparator (vk) is at the first parallel input of a multiple AND gate (vu), the output of which is the area signal output (sa) of the integrated circuit, and the output of the second AND gate (u2) is located at all points of the second parallel input of the multiple AND gate (vu). 2. Decodierschaltung nach Anspruch 1, dadurch gekennzeichnet, daß das analoge Tiefpaßfilter (af) durch ein digitales Tiefpaßfilter (df) derart ersetzt ist, daß der Eingang des Analog-Digital-Wandlers (aw), der ein Sigma-Delta-Wandler ist, direkt am Ausgang der Mischstufe (ms) und der Eingang des digitalen Bandpasses (bp) direkt am Ausgang des digitalen Tiefpaßfilters (df) liegt.2. Decoding circuit according to claim 1, characterized in that the analog low-pass filter (af) is replaced by a digital low-pass filter (df) such that the input of the analog-digital converter (aw), which is a sigma-delta converter, directly at the output of the mixer (ms) and the input of the digital bandpass (bp) directly at the output of the digital low-pass filter (df). 3. Decodierschaltung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Mischstufe (ms) aus einem elektronischen Umschalters (s) und einem invertierenden Einheits-Verstärker (v1) besteht, dessen Ausgang mit dem einen Eingang des Umschalters (s) verbunden ist und dessen Eingang zusammen mit dem Eingang des;Einheits-Verstärkers (v1) das demodulierte Rundfunksignal (ds) zugeführt ist und dessen Steuereingang vom Mischsignal (fn), das ein Rechtecksignal ist, gespeist ist.3. Decoding circuit according to claim 1 or 2, characterized in that the mixer (ms) consists of an electronic switch (s) and an inverting unit amplifier (v1), the output of which is connected to one input of the switch (s) and the input of which, together with the input of the unit amplifier (v1), supplies the demodulated broadcast signal (ds) and whose control input is fed by the mixed signal (fn), which is a square-wave signal.
EP83102412A 1983-03-11 1983-03-11 Integrated circuit for decoding radio broadcast traffic area identification signals Expired EP0119280B1 (en)

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Application Number Priority Date Filing Date Title
EP83102412A EP0119280B1 (en) 1983-03-11 1983-03-11 Integrated circuit for decoding radio broadcast traffic area identification signals
DE8383102412T DE3364612D1 (en) 1983-03-11 1983-03-11 Integrated circuit for decoding radio broadcast traffic area identification signals
JP59045725A JPS59175221A (en) 1983-03-11 1984-03-12 Decoder circuit for traffic information district tone signal

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EP83102412A EP0119280B1 (en) 1983-03-11 1983-03-11 Integrated circuit for decoding radio broadcast traffic area identification signals

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EP0119280A1 true EP0119280A1 (en) 1984-09-26
EP0119280B1 EP0119280B1 (en) 1986-07-23

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US4969209A (en) * 1987-07-27 1990-11-06 Prs Corporation Broadcast receiver capable of selecting stations based upon geographical location and program format

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DE2719618A1 (en) * 1977-05-03 1978-11-09 Koerting Radio Werke Gmbh Phase-locked loop decoder with frequency indicating light signals - selectively indicates reception of stereo and traffic radio signals
DE2916171A1 (en) * 1979-04-21 1980-10-30 Licentia Gmbh Microprocessor controlled heterodyne receiver - has two mixers fed by tunable frequency selective front end input stage

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DE2719618A1 (en) * 1977-05-03 1978-11-09 Koerting Radio Werke Gmbh Phase-locked loop decoder with frequency indicating light signals - selectively indicates reception of stereo and traffic radio signals
DE2916171A1 (en) * 1979-04-21 1980-10-30 Licentia Gmbh Microprocessor controlled heterodyne receiver - has two mixers fed by tunable frequency selective front end input stage

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EP0119280B1 (en) 1986-07-23
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