Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/403—Bus networks with centralised control, e.g. polling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks

Definitions

• This invention relates to digital signal transmission systems for use in computers and the like. Particularly, the invention relates to a shared- bus digital balanced- line transmission system for use in communication between digital devices.
• Bus or backplane communication systems have typically comprised single wire, unipolar signal lines to which are coupled in parallel digital signal drivers and digital signal receivers.
• wired-OR and wired-AND capabilities through signal lines with common-coupled drives and receivers.
• Such bus systems present unique problems, since, in order to implement wired-OR and wired-AND functions, one of the states of each line must be passive to avoid contention between drivers coupled to the common line.
• single wire parallel bus configurations are subject to interference due to both radiated signals and conducted signals (RFI and EMI) which may create unacceptable spurious radiation.
• wired-OR and wired-AND functions have been provided either through open-collector active pull-down drivers or open-emitter active pull-up drivers coupled to the common line. In this manner one state is active while the other is passive, i.e., not subject to driver contention.
• open-collector active pull-down drivers or open-emitter active pull-up drivers coupled to the common line. In this manner one state is active while the other is passive, i.e., not subject to driver contention.
• driver contention open-collector active pull-down drivers
• OMPI are not to be confused with the present approach wherein there is differential activity with unipolar voltages, i.e., an active state and a passive state.
• Examples of prior art patents are U.S. Patent No. 4, 121, 118 to Miyazaki entitled “Bipolar Signal Generating Apparatus'* and U.S. Patent No. 3,671,671 to Watanabe entitled "Pulse Transmitting and Receiving System".
• the Wantanabe circuit employs only current-mode drivers and does not appear to be useful in a wired-OR or wired-AND configuration.
• a differential line transceiver bus system comprises a first driver coupled through an open-collector active pull down transistor to a second biased line, a second driver coupled through an open- emitter active pull up transistor to a first biased line, the second biased line being biased to a higher level than the first line, and the lines forming a parallel wire transmission system to a matched impedance.
• a differential receiver is coupled across the parallel lines to sense differential voltage on the lines. The receiver detects a change in polarity indicating an active state and a reverse in the change of polarity indicating a passive state.
• the two-state operation with active (pulled) and passive (biased) states on each line allows implementation of passive wired logic functions such as wired-OR and wired-AND. Two- wire operation enhances noise margin.
• FIG. 1 is a schematic diagram of a basic transceiver according to the invention.
• Fig. 2 is a schematic diagram of a parallel wire bus system according to the invention.
• Fig. 3 is a schematic diagram of a specific embodiment of a transceiver according to the invention.
• a transceiver 10 comprising a first voltage switch 12, a second voltage switch 14 and a differential line receiver 16 coupled to a first terminal 18 and second terminal 20.
• the first voltage switch 12 is coupled between a first voltage source +V 2 and a node of the first terminal 18, and the second voltage switch 14 is coupled between a second voltage source +V 1 a node of the second terminal 20.
• the voltage +V 2 ⁇ s typically more positive than the voltage +V, .
• Bias voltages for terminals 18 and 20 are selected such that switching of the voltage switches 12 and 14 causes a reversal in relative polarity between first terminal 18 and second terminal 20.
• the noninverting input of the differential receiver 16 is typically coupled to the first terminal 18.
• the inverting input of the receiver 16 is coupled typically to the second terminal 20.
• the differential receiver 16 has an output terminal 22 which provides an indication of the logic state defined by the relative voltages at first terminal 18 and second terminal 20.
• the first switch 12 and second switch 14 are ganged to operate in parallel, that is, switches 12 and 14 open and close simultaneously. In the open position, the voltages at first terminal 18 and second terminal 20 are set at an arbitrary level determined by external bias sources, as hereinafter explained. In a closed position, the first voltage switch 12 pulls the node of the first terminal 18 toward the voltage +V-,, and the second voltage switch 14 pulls the voltage at the node of second terminal 20 toward the voltage source +V..
• a bus network 24 having transceivers 10 according to the invention.
• the first terminals 18 are each coupled to a first bus line 26, and the second terminals 20 are each coupled to a second line 28.
• the first line 26 and second line 28 terminate at each end in an impedance matching network comprising first resistors 34, 36 coupled to a positive voltage +V, second resistors 30, 32 connected between said first and second lines 26, 28, and third resistors 38, 40 coupled to ground (or to another voltage reference lower than +V).
• the impedance of the impedance matching network is selected to match the impedance presented between the first terminal 18 and second terminal 20 of each transceiver 10.
• the impedance network forms the biasing network between voltage +V and a second voltage re erence level, typically ground, by forming a resistive divider.
• the receiver 16 may be a conventional differential- input line receiver whose inputs are coupled across the first line 26 and second line 28. The polarity of the output is selected generally to avoid inversion between the applied signal and the received signal terminals 18 and 20.
• the bias levels in the passive state of each line 26, 28 are selected to match the active voltage level at the terminals of the other line 28, 26.
• the first and second switches 12, 14 (Fig. 1) may be represented as a differential driver 42.
• the first switch 12 comprises a bipolar transistor, such as a Schottky transistor, having its collector electrode coupled through a current limiting resistor 44 to a high voltage +V 2» i ts emitter electrode coupled to a node of the first terminal 18, and its base electrode coupled to an input terminal 48.
• the second switch 14 is a bipolar transistor whose emitter electrode is coupled to a low voltage, typically ground (assuming NPN-type logic), whose collector electrode is coupled through a current limiting resistor 46 to a node of the second terminal 20 and whose base electrode is coupled to an input terminal 50.
• Input terminal 50 is driven in parallel with the input terminal 48 through a drive network (not shown).
• the circuit is operative in an active state and a passive state representing opposite logic levels.
• the receiver 16 senses relative polarity of the terminals 18 and 20 to indicate the binary state value.
• the current limiting resistors 44, 46 are selected to limit the bus current, to match the impedance of the bus, and to bias the voltage levels on the bus so that switching occurs between the differential bias levels.
• the transceiver 10 according to the invention is substantially immune to noise, having a relatively large noise margin due to the differential operation of the receiver circuit, it is capable of performing desirable wired-logic functions, and it is universally compatible with other transistor- transistor logic type devices at its output and input.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Dc Digital Transmission (AREA)

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• 1983
  • 1983-08-02 EP EP19830902728 patent/EP0116603A4/de not_active Withdrawn
  • 1983-08-02 WO PCT/US1983/001179 patent/WO1984000862A1/en not_active Application Discontinuation
  • 1983-08-02 JP JP50277983A patent/JPS59501391A/ja active Pending

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