WO1984000862A1 - Digital signal transmission and receiving apparatus - Google Patents

Digital signal transmission and receiving apparatus Download PDF

Info

Publication number
WO1984000862A1
WO1984000862A1 PCT/US1983/001179 US8301179W WO8400862A1 WO 1984000862 A1 WO1984000862 A1 WO 1984000862A1 US 8301179 W US8301179 W US 8301179W WO 8400862 A1 WO8400862 A1 WO 8400862A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus terminal
voltage
coupled
voltage switch
terminal
Prior art date
Application number
PCT/US1983/001179
Other languages
French (fr)
Inventor
Randolph B Haagens
Roy J Levy
David L Campbell
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of WO1984000862A1 publication Critical patent/WO1984000862A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks

Definitions

  • This invention relates to digital signal transmission systems for use in computers and the like. Particularly, the invention relates to a shared- bus digital balanced- line transmission system for use in communication between digital devices.
  • Bus or backplane communication systems have typically comprised single wire, unipolar signal lines to which are coupled in parallel digital signal drivers and digital signal receivers.
  • wired-OR and wired-AND capabilities through signal lines with common-coupled drives and receivers.
  • Such bus systems present unique problems, since, in order to implement wired-OR and wired-AND functions, one of the states of each line must be passive to avoid contention between drivers coupled to the common line.
  • single wire parallel bus configurations are subject to interference due to both radiated signals and conducted signals (RFI and EMI) which may create unacceptable spurious radiation.
  • wired-OR and wired-AND functions have been provided either through open-collector active pull-down drivers or open-emitter active pull-up drivers coupled to the common line. In this manner one state is active while the other is passive, i.e., not subject to driver contention.
  • open-collector active pull-down drivers or open-emitter active pull-up drivers coupled to the common line. In this manner one state is active while the other is passive, i.e., not subject to driver contention.
  • driver contention open-collector active pull-down drivers
  • OMPI are not to be confused with the present approach wherein there is differential activity with unipolar voltages, i.e., an active state and a passive state.
  • Examples of prior art patents are U.S. Patent No. 4, 121, 118 to Miyazaki entitled “Bipolar Signal Generating Apparatus'* and U.S. Patent No. 3,671,671 to Watanabe entitled "Pulse Transmitting and Receiving System".
  • the Wantanabe circuit employs only current-mode drivers and does not appear to be useful in a wired-OR or wired-AND configuration.
  • a differential line transceiver bus system comprises a first driver coupled through an open-collector active pull down transistor to a second biased line, a second driver coupled through an open- emitter active pull up transistor to a first biased line, the second biased line being biased to a higher level than the first line, and the lines forming a parallel wire transmission system to a matched impedance.
  • a differential receiver is coupled across the parallel lines to sense differential voltage on the lines. The receiver detects a change in polarity indicating an active state and a reverse in the change of polarity indicating a passive state.
  • the two-state operation with active (pulled) and passive (biased) states on each line allows implementation of passive wired logic functions such as wired-OR and wired-AND. Two- wire operation enhances noise margin.
  • FIG. 1 is a schematic diagram of a basic transceiver according to the invention.
  • Fig. 2 is a schematic diagram of a parallel wire bus system according to the invention.
  • Fig. 3 is a schematic diagram of a specific embodiment of a transceiver according to the invention.
  • a transceiver 10 comprising a first voltage switch 12, a second voltage switch 14 and a differential line receiver 16 coupled to a first terminal 18 and second terminal 20.
  • the first voltage switch 12 is coupled between a first voltage source +V 2 and a node of the first terminal 18, and the second voltage switch 14 is coupled between a second voltage source +V 1 a node of the second terminal 20.
  • the voltage +V 2 ⁇ s typically more positive than the voltage +V, .
  • Bias voltages for terminals 18 and 20 are selected such that switching of the voltage switches 12 and 14 causes a reversal in relative polarity between first terminal 18 and second terminal 20.
  • the noninverting input of the differential receiver 16 is typically coupled to the first terminal 18.
  • the inverting input of the receiver 16 is coupled typically to the second terminal 20.
  • the differential receiver 16 has an output terminal 22 which provides an indication of the logic state defined by the relative voltages at first terminal 18 and second terminal 20.
  • the first switch 12 and second switch 14 are ganged to operate in parallel, that is, switches 12 and 14 open and close simultaneously. In the open position, the voltages at first terminal 18 and second terminal 20 are set at an arbitrary level determined by external bias sources, as hereinafter explained. In a closed position, the first voltage switch 12 pulls the node of the first terminal 18 toward the voltage +V-,, and the second voltage switch 14 pulls the voltage at the node of second terminal 20 toward the voltage source +V..
  • a bus network 24 having transceivers 10 according to the invention.
  • the first terminals 18 are each coupled to a first bus line 26, and the second terminals 20 are each coupled to a second line 28.
  • the first line 26 and second line 28 terminate at each end in an impedance matching network comprising first resistors 34, 36 coupled to a positive voltage +V, second resistors 30, 32 connected between said first and second lines 26, 28, and third resistors 38, 40 coupled to ground (or to another voltage reference lower than +V).
  • the impedance of the impedance matching network is selected to match the impedance presented between the first terminal 18 and second terminal 20 of each transceiver 10.
  • the impedance network forms the biasing network between voltage +V and a second voltage re erence level, typically ground, by forming a resistive divider.
  • the receiver 16 may be a conventional differential- input line receiver whose inputs are coupled across the first line 26 and second line 28. The polarity of the output is selected generally to avoid inversion between the applied signal and the received signal terminals 18 and 20.
  • the bias levels in the passive state of each line 26, 28 are selected to match the active voltage level at the terminals of the other line 28, 26.
  • the first and second switches 12, 14 (Fig. 1) may be represented as a differential driver 42.
  • the first switch 12 comprises a bipolar transistor, such as a Schottky transistor, having its collector electrode coupled through a current limiting resistor 44 to a high voltage +V 2» i ts emitter electrode coupled to a node of the first terminal 18, and its base electrode coupled to an input terminal 48.
  • the second switch 14 is a bipolar transistor whose emitter electrode is coupled to a low voltage, typically ground (assuming NPN-type logic), whose collector electrode is coupled through a current limiting resistor 46 to a node of the second terminal 20 and whose base electrode is coupled to an input terminal 50.
  • Input terminal 50 is driven in parallel with the input terminal 48 through a drive network (not shown).
  • the circuit is operative in an active state and a passive state representing opposite logic levels.
  • the receiver 16 senses relative polarity of the terminals 18 and 20 to indicate the binary state value.
  • the current limiting resistors 44, 46 are selected to limit the bus current, to match the impedance of the bus, and to bias the voltage levels on the bus so that switching occurs between the differential bias levels.
  • the transceiver 10 according to the invention is substantially immune to noise, having a relatively large noise margin due to the differential operation of the receiver circuit, it is capable of performing desirable wired-logic functions, and it is universally compatible with other transistor- transistor logic type devices at its output and input.

Abstract

A differential line bus system includes differential transceivers (16) which are operative between active differential pull-up/pull down and passive differential biased-down and biased-up states on each of two bus lines (26, 28). Voltage-mode switching is employed. Two-wire, active-passive differential switching and detection is compatible with mutually incompatible wired-logic components, such as TTL open-collector and TTL open-emitter logic.

Description

DIGITAL SIGNAL TRANSMISSION AND RECEIVING APPARATUS
BACKGROUND OF THE INVENTION Field of Invention
This invention relates to digital signal transmission systems for use in computers and the like. Particularly, the invention relates to a shared- bus digital balanced- line transmission system for use in communication between digital devices.
Bus or backplane communication systems have typically comprised single wire, unipolar signal lines to which are coupled in parallel digital signal drivers and digital signal receivers. In specific applications it is desirable to provide wired-OR and wired-AND capabilities through signal lines with common-coupled drives and receivers. Such bus systems present unique problems, since, in order to implement wired-OR and wired-AND functions, one of the states of each line must be passive to avoid contention between drivers coupled to the common line.
In addition, single wire parallel bus configurations are subject to interference due to both radiated signals and conducted signals (RFI and EMI) which may create unacceptable spurious radiation.
What is needed is a bus transmission system which is substantially immune to spurious noise and which can work in universal applications where wired-OR and wired-AND functions are desirable features.
Description of the Prior Art
In the past, wired-OR and wired-AND functions have been provided either through open-collector active pull-down drivers or open-emitter active pull-up drivers coupled to the common line. In this manner one state is active while the other is passive, i.e., not subject to driver contention. However, such approaches are mutually incompatible and make system interfacing difficult.
A number of approaches are known for generating bipolar signals having relative positive and negative polarity. These approaches
OMPI are not to be confused with the present approach wherein there is differential activity with unipolar voltages, i.e., an active state and a passive state. Examples of prior art patents are U.S. Patent No. 4, 121, 118 to Miyazaki entitled "Bipolar Signal Generating Apparatus'* and U.S. Patent No. 3,671,671 to Watanabe entitled "Pulse Transmitting and Receiving System". The Wantanabe circuit, however, employs only current-mode drivers and does not appear to be useful in a wired-OR or wired-AND configuration.
SUMMARY OF THE INVENTION According to the invention, a differential line transceiver bus system comprises a first driver coupled through an open-collector active pull down transistor to a second biased line, a second driver coupled through an open- emitter active pull up transistor to a first biased line, the second biased line being biased to a higher level than the first line, and the lines forming a parallel wire transmission system to a matched impedance. A differential receiver is coupled across the parallel lines to sense differential voltage on the lines. The receiver detects a change in polarity indicating an active state and a reverse in the change of polarity indicating a passive state. The two-state operation with active (pulled) and passive (biased) states on each line allows implementation of passive wired logic functions such as wired-OR and wired-AND. Two- wire operation enhances noise margin.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a basic transceiver according to the invention.
Fig. 2 is a schematic diagram of a parallel wire bus system according to the invention.
Fig. 3 is a schematic diagram of a specific embodiment of a transceiver according to the invention.
OMPI
WIPO DESCRIPTION OF SPECIFIC EMBODIMENTS Referring to Fig. 1 , there is shown a simplified schematic diagram of a transceiver 10 comprising a first voltage switch 12, a second voltage switch 14 and a differential line receiver 16 coupled to a first terminal 18 and second terminal 20. Specifically, the first voltage switch 12 is coupled between a first voltage source +V2 and a node of the first terminal 18, and the second voltage switch 14 is coupled between a second voltage source +V 1 a node of the second terminal 20. The voltage +V2 ιs typically more positive than the voltage +V, . Bias voltages for terminals 18 and 20 are selected such that switching of the voltage switches 12 and 14 causes a reversal in relative polarity between first terminal 18 and second terminal 20.
The noninverting input of the differential receiver 16 is typically coupled to the first terminal 18. The inverting input of the receiver 16 is coupled typically to the second terminal 20. The differential receiver 16 has an output terminal 22 which provides an indication of the logic state defined by the relative voltages at first terminal 18 and second terminal 20. The first switch 12 and second switch 14 are ganged to operate in parallel, that is, switches 12 and 14 open and close simultaneously. In the open position, the voltages at first terminal 18 and second terminal 20 are set at an arbitrary level determined by external bias sources, as hereinafter explained. In a closed position, the first voltage switch 12 pulls the node of the first terminal 18 toward the voltage +V-,, and the second voltage switch 14 pulls the voltage at the node of second terminal 20 toward the voltage source +V..
Turning to Fig. 2, there is shown a bus network 24 having transceivers 10 according to the invention. The first terminals 18 are each coupled to a first bus line 26, and the second terminals 20 are each coupled to a second line 28. The first line 26 and second line 28 terminate at each end in an impedance matching network comprising first resistors 34, 36 coupled to a positive voltage +V, second resistors 30, 32 connected between said first and second lines 26, 28, and third resistors 38, 40 coupled to ground (or to another voltage reference lower than +V). The impedance of the impedance matching network is selected to match the impedance presented between the first terminal 18 and second terminal 20 of each transceiver 10. Matched impedances minimize signal reflections of the transmission line and of any spurious transmission line effects and maximize noise margins. The impedance network forms the biasing network between voltage +V and a second voltage re erence level, typically ground, by forming a resistive divider. The receiver 16 may be a conventional differential- input line receiver whose inputs are coupled across the first line 26 and second line 28. The polarity of the output is selected generally to avoid inversion between the applied signal and the received signal terminals 18 and 20. The bias levels in the passive state of each line 26, 28 are selected to match the active voltage level at the terminals of the other line 28, 26. The first and second switches 12, 14 (Fig. 1) may be represented as a differential driver 42.
Referring to Fig. 3, there is shown a specific embodiment of a transceiver 10 according to the invention wherein the first switch 12 comprises a bipolar transistor, such as a Schottky transistor, having its collector electrode coupled through a current limiting resistor 44 to a high voltage +V2» its emitter electrode coupled to a node of the first terminal 18, and its base electrode coupled to an input terminal 48. The second switch 14 is a bipolar transistor whose emitter electrode is coupled to a low voltage, typically ground (assuming NPN-type logic), whose collector electrode is coupled through a current limiting resistor 46 to a node of the second terminal 20 and whose base electrode is coupled to an input terminal 50. Input terminal 50 is driven in parallel with the input terminal 48 through a drive network (not shown). The circuit is operative in an active state and a passive state representing opposite logic levels. The receiver 16 senses relative polarity of the terminals 18 and 20 to indicate the binary state value. The current limiting resistors 44, 46 are selected to limit the bus current, to match the impedance of the bus, and to bias the voltage levels on the bus so that switching occurs between the differential bias levels.
The transceiver 10 according to the invention is substantially immune to noise, having a relatively large noise margin due to the differential operation of the receiver circuit, it is capable of performing desirable wired-logic functions, and it is universally compatible with other transistor- transistor logic type devices at its output and input.
The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art. For example, polarities of transistors may be reversed and other types of transistor switches may be utilized, such as MOS transistors and the like. It is therefore not intended that this invention be limited, except as indicated by the appended claims.

Claims

1. An apparatus for- conveying binary digital signals comprising: a first bus terminal, said first bus terminal for coupling to a first bias level having a line matching termination; a second bus terminal, said second bus terminal for coupling to a second bias level having a line matching termination, said first bias level being lower than said second bias level; a first voltage switch coupled to said first bus terminal and operative in a first state to pull actively said first bus terminal to a first logic level toward said second bias level and operative in a second state to allow said first bus terminal to be biased to said first bias level; and a second voltage switch coupled to said second bus terminal and operative in said first state to pull actively said second bus terminal toward said first bias level and operative in said second state to allow said second bus terminal to be biased to said second bias level.
2. The apparatus according to claim 1 further comprising: differential receiver means coupled to said first bus terminal and to said second bus terminal for sensing differential voltage between said first bus terminal and said second bus terminal.
3. The apparatus according to claim 1 or 2 wherein said first voltage switch and said second voltage switch each comprise a transistor switch and current limiting means.
4. The apparatus according to claim 3 wherein said current limiting means comprises a resistor.
5. The apparatus according to claim 1 or 2 wherein said first voltage switch comprises a transistor having an emitter electrode circuit coupled to said first bus terminal.
6. The apparatus according to claim 5 wherein said second voltage switch comprises a transistor having a collector electrode circuit coupled through current limiting means to said second bus terminal.
7. The apparatus according to claim 6 wherein said first voltage switch transistor has a collector electrode circuit including a current limiting resistor.
8. The apparatus according to claim 1 or 2 further comprising: an impedance matching network having a first resistor means coupled between said first bus terminal and said second bus terminal, a second resistor means coupled between said first bus terminal and a first voltage level, and a third resistor means coupled between said second bus terminal and a second voltage level, said first voltage level being less than said second voltage level.
9. The apparatus according to claim 8 wherein said first, second and third resistor means are selected for impedance matching of said first bus terminal and said second bus terminal.
10. The apparatus according to claim 9 wherein said first voltage switch and said second voltage switch each comprise a transistor switch and current limiting means, and wherein said current limiting means each comprise a resistor selected for impedance match with said impedance matching network.
PCT/US1983/001179 1982-08-09 1983-08-02 Digital signal transmission and receiving apparatus WO1984000862A1 (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171555A1 (en) * 1984-07-20 1986-02-19 Siemens Aktiengesellschaft Bus system with two signal conductors connected to transmission devices via two differential outputs
EP0237839A2 (en) * 1986-02-24 1987-09-23 Chrysler Corporation Serial data bus for intermodule data communications and method of data arbitration and collision detection on a data bus
US4888764A (en) * 1986-12-11 1989-12-19 Siemens Aktiengesellschaft Transmission-reception equipment for a bus system
EP0400908A2 (en) * 1989-05-31 1990-12-05 LUCAS INDUSTRIES public limited company Line Driver
EP0432582A1 (en) * 1989-12-11 1991-06-19 Mips Computer Systems, Inc. Differential bus with specified default value
EP0450871A2 (en) * 1990-03-30 1991-10-09 Xerox Corporation Interfaces for transmission lines
EP0537704A2 (en) * 1991-10-16 1993-04-21 The Furukawa Electric Co., Ltd. Multiplex transmission system
US5465255A (en) * 1991-10-16 1995-11-07 The Furukawa Electric Co., Ltd. Multiplex transmission system
EP0695060A1 (en) * 1994-07-27 1996-01-31 AT&T Corp. Backplane bus for differential signals
WO2003009554A1 (en) * 2001-07-18 2003-01-30 Telefonaktiebolaget L M Ericsson (Publ) Apparatus and method for bias compensation in differential transmission lines

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3381090A (en) * 1964-10-01 1968-04-30 Ibm Balanced line driver
US3497619A (en) * 1967-10-06 1970-02-24 Us Navy Digital data transmission system
US3671671A (en) * 1969-06-13 1972-06-20 Yokogawa Electric Works Ltd Pulse transmitting and receiving systems

Family Cites Families (1)

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Publication number Priority date Publication date Assignee Title
DE3015661A1 (en) * 1980-04-23 1981-10-29 Siemens AG, 1000 Berlin und 8000 München Binary code transmission over data bus - using high voltage on bus as indication of logic null state

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3381090A (en) * 1964-10-01 1968-04-30 Ibm Balanced line driver
US3497619A (en) * 1967-10-06 1970-02-24 Us Navy Digital data transmission system
US3671671A (en) * 1969-06-13 1972-06-20 Yokogawa Electric Works Ltd Pulse transmitting and receiving systems

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0116603A4 *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171555A1 (en) * 1984-07-20 1986-02-19 Siemens Aktiengesellschaft Bus system with two signal conductors connected to transmission devices via two differential outputs
EP0237839A2 (en) * 1986-02-24 1987-09-23 Chrysler Corporation Serial data bus for intermodule data communications and method of data arbitration and collision detection on a data bus
EP0237839A3 (en) * 1986-02-24 1989-09-27 Chrysler Motors Corporation Serial data bus for intermodule data communications and method of data arbitration and collision detection on a data bus
US4888764A (en) * 1986-12-11 1989-12-19 Siemens Aktiengesellschaft Transmission-reception equipment for a bus system
EP0400908A3 (en) * 1989-05-31 1991-09-25 LUCAS INDUSTRIES public limited company Line driver
EP0400908A2 (en) * 1989-05-31 1990-12-05 LUCAS INDUSTRIES public limited company Line Driver
EP0432582A1 (en) * 1989-12-11 1991-06-19 Mips Computer Systems, Inc. Differential bus with specified default value
EP0450871A2 (en) * 1990-03-30 1991-10-09 Xerox Corporation Interfaces for transmission lines
EP0450871A3 (en) * 1990-03-30 1994-10-05 Xerox Corporation Interfaces for transmission lines
EP0537704A2 (en) * 1991-10-16 1993-04-21 The Furukawa Electric Co., Ltd. Multiplex transmission system
EP0537704A3 (en) * 1991-10-16 1995-02-15 Furukawa Electric Co Ltd Multiplex transmission system
US5465255A (en) * 1991-10-16 1995-11-07 The Furukawa Electric Co., Ltd. Multiplex transmission system
EP0695060A1 (en) * 1994-07-27 1996-01-31 AT&T Corp. Backplane bus for differential signals
WO2003009554A1 (en) * 2001-07-18 2003-01-30 Telefonaktiebolaget L M Ericsson (Publ) Apparatus and method for bias compensation in differential transmission lines
US6980773B2 (en) 2001-07-18 2005-12-27 Telefonaktiebolaget L M Ericsson (Publ) Apparatus and method for bias compensation in line circuits

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Publication number Publication date
EP0116603A4 (en) 1984-11-22
JPS59501391A (en) 1984-08-02
EP0116603A1 (en) 1984-08-29

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