EP0097338A2 - Referenzspannungserzeugungsvorrichtung - Google Patents

Referenzspannungserzeugungsvorrichtung Download PDF

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Publication number
EP0097338A2
EP0097338A2 EP83105935A EP83105935A EP0097338A2 EP 0097338 A2 EP0097338 A2 EP 0097338A2 EP 83105935 A EP83105935 A EP 83105935A EP 83105935 A EP83105935 A EP 83105935A EP 0097338 A2 EP0097338 A2 EP 0097338A2
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EP
European Patent Office
Prior art keywords
mos transistor
gate
drain
source
semiconductor
Prior art date
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Application number
EP83105935A
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English (en)
French (fr)
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EP0097338A3 (de
Inventor
Shoichi Ohzeki
Toji Mukai
Nobuaki Miyakawa
Takahide Ikeda
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Hitachi Ltd
Minebea Power Semiconductor Device Inc
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Hitachi Ltd
Hitachi Haramachi Electronics Ltd
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Publication of EP0097338A2 publication Critical patent/EP0097338A2/de
Publication of EP0097338A3 publication Critical patent/EP0097338A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage

Definitions

  • This invention relates to a reference voltage generating device formed of semiconductors.
  • Sources of reference voltage used hitherto utilize, for example, a forward voltage drop V . of a P N junction diode, a reverse breakdown voltage (the zener voltage) V Z of such a junction diode and a threshold voltage V th of an insulated-gate field effect transistor. Further, an insulated-gate transistor of the type in which its threshold voltage V th is structurally equal to the hand gap has been proposed and fabricated already.
  • each of the prior art reference voltage sources of the types above described includes various factors causing variations of its output voltage depending on the conditions of its fabrication process and the factors of the process controlling the physical quantities.
  • a prior art reference voltage source of the hand gap type utilizes the threshold voltage difference between an N +- gate MOS transistor and a P +- gate MOS transistor, as disclosed in, for example, Japanese Patent Application Laid-Open No. 51-149780; IEEE, Vol. SC-15, No. 3 JUNE 1980, pp. 264-269; and DE-OS 2951835. Also, a reference voltage source utilizing the threshold voltage difference between an enhancement type MOS transistor and a depletion type MOS transistor is disclosed in a literature such as IEEE, 1978, pp. 50-51.
  • An N +- gate MOS transistor has a threshold voltage attributable to the doping of its gate layer with a pentavalent doner impurity, while a P +- gate MOS transistor has a threshold voltage attributable to the doping of its gate layer with a trivalent acceptor impurity.
  • the trivalent impurity has a large coefficient of diffusion into an oxide film and thus diffuses into the bulk layer directly beneath the gate through a thin oxide film such as a gate oxide film. Therefore, the threshold voltage V th of the P -gate MOS transistor determined depending on the impurity concentration of the bulk layer tends to vary, and the output voltage of the reference voltage source utilizing the P +- gate MOS transistor tends also to vary or fluctuate.
  • FIG. 1 shows the prior art structure of a P -gate MOS transistor and an N -gate MOS transistor fabricated according to the silicon gate process.
  • FIG. 2 shows, by way of example, the results of measurement of the threshold voltages V th of the P + -gate and N +- gate MOS transistors shown in FIG. 1 when the gate layer of the P +- gate MOS transistor was doped with an acceptor impurity such as boron, and the gate layer of the N -gate M OS transistor was doped with a doner impurity such as phosphorus.
  • the gate film thickness 500 ⁇ .
  • the values of the threshold voltage V th are substantially constant in the case of the N +- gate MOS transistor, while, on the other hand, the values of the threshold voltage Vt h are dispersed in the case of the P +- gate MOS transistor.
  • the acceptor impurity such as boron diffuses into the bulk layer though the gate oxide film thereby causing variations of the threshold voltage Vt h of the P + -gate MOS transistor.
  • the thickness of the gate oxide film must be made larger than hitherto or an insulator film such as a nitride film must additionally be disposed on the gate oxide film.
  • the thickness of the gate oxide film will be required to be smaller than hitherto, and in order to meet such a demand, a measure must be taken which can sufficiently suppress threshold voltage variations tending to occur more frequently due to the smaller thickness of the gate oxide film.
  • Another object of the present invention is to provide a reference voltage generating device generating a reference voltage which can be set at any desired level.
  • the reference voltage generating device of the present invention comprises an N-type semiconductor and an intrinsic semiconductor both of which are formed of the same semiconductive material, and means for deriving a voltage corresponding to the difference between the Fermi energy levels of these semiconductors.
  • the reference voltage generating device of the present invention comprises a semiconductor of a first conductivity type and a semiconductor of a second conductivity type both of which are formed of the same semiconductive material, means for deriving a voltage corresponding to the difference between the Fermi energy levels of these semiconductors, and means for amplifying the voltage.
  • Fig. 3(A) is a schematic sectional view showing the basic structure of the reference voltage generating device according to the present invention.
  • the basic structure includes a P-channel N +- gate MOS transistor 301 having a gate electrode 3011 provided by doping a polysilicon layer with phosphorus so that its impurity concentration is preferably in the order of 10 20 cm -3 to 10 21 cm -3 , and a P -channel intrinsic-gate MOS transistor 302 having a gate electrode 3021 provided by non-doping a polysilicon layer with any impurity.
  • Fig. 3(B) is a graph showing, by way of example, the results of measurement of the threshold voltages V th of these MOS transistor 301 and 302.
  • the numerals 3012 and 3022 designate S i 0 2 or like gate insulator layers.
  • the term "intrinsic" is used herein to indicate that the specific layer is not doped with any impurity, and the impurity concentration of that layer is preferably not higher than 10 14 cm -3 . It will be seen from Fig. 3(B) that the threshold voltages V th of both of the N +- gate MOS transistor 301 and the intrinsic-gate MOS transistor 302 are substantially constant in the same wafer.
  • the reference voltage generating device based on such a basic structure can be fabricated with little fabrication errors and can thus be utilized as a stable reference voltage source.
  • the threshold voltage V thn+ of the N +- gate MOS transistor 301 is given by
  • ⁇ S 2 ⁇ F .
  • the threshold voltage V thi of the MOS trans- sistor 302 is given by
  • ⁇ S 2 ⁇ F .
  • the threshold voltage difference is equal to the difference between the Fermi potentials of the semiconductors forming the gate electrodes of the MOS transistors 301 and 302.
  • Fig. 5(A) is a circuit diagram of a circuit generating a voltage corresponding to the difference between the threshold voltages of MOS transistors
  • Fig. 5(B) is a graph showing the V GS - I DS characteristic of the circuit shown in Fig. 5(A).
  • MOS FET's T N + and T i having different threshold voltages V thn + and V th i respectively but being substantially equal to each other in their mutual conductance ⁇ are each connected at the drain and gate in common to constitute so-called MOS diodes.
  • the symbol I o designates a constant cur- . rent source to which each MOS FET is connected, and V N + and V ip designate the drain voltages of the M OS FET's T N + and T i respectively. Since I o is expressed as the drain voltages V N+ and V i p of the MOS FET's T N + and T i are expressed as follows respectively:
  • the difference between the threshold voltages V thn + and V thi can be obtained by taking the difference between the drain voltages V N+ and V ip .
  • the constant current source I o may be a resistor having a sufficiently high resistance. Provided that the resistance characteristic is uniform, the constant current source I o may be a diffused resistor, a polycrystalline silicon resistor, a resistor made by ion implantation or a resistor utilizing a MOS transistor.
  • threshold voltages V th of silicon-gate MOS transistors or an N +- gate MOS transistor and an intrinsic-gate MOS transistor formed in the same wafer do not vary or fluctuate substantially, and a reference voltage generating circuit utilizing the threshold voltage difference between the N +- gate MOS transistor and the intrinsic-gate MOS transistor can provide a stable output voltage.
  • the level of the output voltage from such a reference voltage generating circuit is low compared with that of a reference voltage generating circuit utilizing the threshold voltage difference between a P +- gate MOS transistor and an N -gate MOS transistor.
  • the output voltage from the MOS transistor pair is amplified by the factor of n (n: an integer), that is, by providing n pairs of N +- gate MOS transistors and intrinsic-gate MOS transistors in the circuit to utilize the threshold voltage difference in each pair.
  • Fig. 6 is a circuit diagram showing the structure of an embodiment of the present invention adapted for amplifying the threshold voltage difference by the factor of 2 according to the basic idea of the present invention.
  • a P-channel MOS transistor 10 is connected at its source to the positive terminal 1 of a power source of the reference voltage generating circuit.
  • An N-channel N -gate MOS transistor 11 is connected at its drain and gate to the gate and drain respectively of the P-channel MOS transistor 10, and another N-channel N +- gate MOS transistor 12 is connected at its drain and gate to the drain and source respectively of the N-channel N +- gate MOS transistor 11 and at its source to the negative power supply terminal.
  • Another P-channel MOS transistor 20 is connected at its source to the positive power supply terminal 1 and at its gate to the gate of the P-channel MOS transistor 10.
  • An N-channel intrinsic-gate MOS transistor 21 is connected at its drain and gate to the drain of the P-channel MOS transistor 20, and another N-channel intrinsic-gate MOS transistor 22 is connected at its drain and gate to the drain and source respectively of the N-channel intrinsic-gate MOS transistor 21 and at its source to the negative power supply terminal.
  • V 1 be the drain-source voltage of the N-channel N +- gate MOS transistor 12 in the arrangement of the MOS transistors 10, 11 and 12.
  • Current I 1 flowing through this N-channel N +- gate MOS transistor 12 is given by where
  • the currents I 1 and I 2 are equal to each other.
  • the drain-source voltages V 1 and V 2 of the MOS transistors 12 and 22 are computed from the equations (13) and (14) as follows respectively:
  • the drain voltage difference (V 1 -V 2 ) between the N +- gate MOS transistors 11, 12 and the intrinsic-gate MOS transistors 21, 22 provides a voltage equal to the factor-of-2 amplified threshold voltage difference.
  • Fig. 7 is a circuit diagram showing the structure of another embodiment of the present invention adapted for amplifying the threshold voltage difference by the factor of n (n: an integer).
  • n an integer
  • diode-connected N-channel N + -gate MOS transistors are connected between N-channel N +- gate MOS transistors 11 and 12 to provide a total of n
  • diode-connected N-channel intrinsic-gate MOS transistors are connected between N-channel intrinsic-gate MOS transistors 21 and 22 to provide a total of n.
  • the difference between the drain-source voltages V 1 ' and V 2 ' of the N +- gate MOS transistor 12 and intrinsic-gate MOS transistor 22 is expressed as follows:
  • the threshold voltage difference between the N +- gate MOS transistor 11 and the intrinsic-gate MOS transistor 21 can be amplified by the factor of n.
  • the method shown in Fig. 7 can be used for providing a reference voltage which is n (n: an integer) times as high as the threshold voltage difference between the N + -gate MOS transistor 11 and the intrinsic-gate MOS transistor 21.
  • n an integer
  • the circuits of C MOS structure including P-channel MO S transistors acting as an active load combined with N-channel N +- gate MOS transistors and N-channel intrinsic-gate MOS transistors have been described with reference to Figs. 6 and 7, by way of example, it is apparent that such a reference voltage can be similarly generated by the combination of P-channel N -gate MOS transistors and P-channel intrinsic-gate MOS transistors. It is also apparent that single-channel MOS transistors only may be similarly effectively used.
  • Embodiments shown in Figs. 8 and 9 correspond to or are modifications of those shown in Figs. 6 and 7 respectively.
  • the modifications shown in Figs. 8 and 9 are adapted for amplifying the threshold voltage difference between an N-channel intrinsic-gate MOS transistor and an N-channel N +- gate MOS transistor by the factors of 2 and n respectively.
  • the individual MOS transistors are diode-connected in two stages, while, in the case of Fig. 9, they are diode-connected in n stages.
  • the numerals 110 in Fig. 8 and lln, 120 in Fig. 9 designate N-channel N + -gate MOS transistors
  • the numerals 210 in Fig. 8 and 21n, 220 in Fig. 9 designate N-channel intrinsic-gate MOS transistors.
  • the numerals 100 and 200 in each of Figs. 8 and 9 designate P-channel MOS transistors of current mirror arrangement as in the case of Figs. 6 and 7.
  • the MOS transistors 120 and 220 are connected at their drains to the sources of the MOS transistors 110 and 210 respectively, so that the MOS transistors 120 and 220 are not adversely affected by the drift that may occur in the MOS transistors 110 and 210. Therefore, this embodiment is advantageous in that the operating characteristic of the reference voltage generating circuit can be stabilized. The same applies also to the embodiment shown in Fig. 9.
  • the carrier in such a semiconductor is electrons n d ionized from a doner impurity N 3 and pairs of electrons and holes excited from the valence band.
  • N d can be computed from the probability of the number of electrons trapped at the doner level, and n can be computed from the number of electrons present in the conduction hand, as follows:
  • the temperature-dependent change of the differ- enc e (E FN - E Fi ) between the Fermi level of the N-type semiconductor and that of the intrinsic semiconductor is about 0.52 eV to 0.43 eV within the temperature range of 200 ⁇ K to 400 ⁇ K (-70°C to 130°C).
  • a reference voltage generating circuit of the band gap type is advantageous over a reference voltage generating circuit of the type utilizing the threshold.
  • voltage of a MOS transistor or the forward voltage drop of a diode in that the temperature-dependent change of its operating characteristic is less than that of the latter.
  • the temperature dependence of such a reference voltage generating cirduit becomes a matter of consideration when such a circuit is incorporated in, for example, a high-accuracy analog circuit.
  • Fig. 11 is a circuit diagram showing the structure of still another embodiment of the present invention. That is, Fig. 11 shows one form of the reference voltage generating circuit of the band gap type which is provided with the function of temperature compensation.
  • the numerals 1 to 22 designate the same parts as those appearing in Fig. 6 except the ground terminals of the N-channel MOS transistors 12 and 22.
  • a P-channel MOS transistor 30 is connected at its source to the positive power supply terminal 1.
  • An N-channel N +- gate MOS transistor 31 is connected at its drain and gate to the drain and gate of the P-channel MOS transistor 30 respectively.
  • An N-channel N +- gate MOS transistor 32 is connected at its drain to the drain of the P-channel MOS transistor 30 and at its gate to the source of the N +- gate MOS transistor 31.
  • An N-channel MOS transistor 33 is connected at its drain to the source of the N + -gate MOS transistor 32 and at its source to the negative power supply terminal.
  • a bias voltage input terminal . 35 is connected to the gate of the N-channel MOS transistor 33.
  • Another N-channel MOS transistor 40 is connected at its drain to the sources of the N +- gate and intrinsic-gate MOS transistors 12 and 22, at its gate to the bias voltage input terminal 35 and at its source to the negative power supply terminal.
  • the ratio between I 33 and I 40 is 1:2 when the ratio between ⁇ 33 and ⁇ 40 is selected to be 1:2.
  • the drain voltage V D1 appearing at the drain. of the N +- gate MOS transistor 12 provides the gate voltage of the P-channel MOS transistor 30 and N-channel MOS transistor 31, and the current I 1 flowing through the N-channel N +- gate MOS transistors 31, 32 and P-channel MOS transistor 30 is given by where ⁇ p , ⁇ n +; dimension ratios of respective P channel MOS transistor 30 and n gate transistors 31, 32. From these two equations (27) and (28), the drain voltage V D1 of the N +- gate MOS transistor 12 is computed as follows:
  • the current flowing through the N +- gate MOS transistor 12 is equal to that flowing through the intrinsic-gate MOS transistor 22, and the sum of these currents flows through the N-channel MOS transistor 40.
  • the relation between the current flowing through the N-channel MOS transistor 33 and that flowing through the N-channel MOS transistor 40 is selected to be 1:2 as described above, the currents flowing through the N +- gate MOS transistors 12 and 32 are equal to each other, and the drain voltage of the P-channel MOS transistor 30 is also equal to V D1 . That is, the input and output voltages of the circuit composed of the MOS transistors 30 to 33 are equal to each other, and such a relation establishes the most stable state.
  • Another P-channel MOS transistor 36 is connected at its source to the positive power supply terminal 1, at its gate to the drain of the N +- gate MOS transistor 31 and at its drain to the gate of the P -channel MOS transistor 10.
  • Another N-channel N +- gate M O S transistor 37 is connected at its drain and gate to the drain and gate of the P-channel MOS transistor 36 respectively.
  • Another N-channel N +- gate MOS transistor 38 is connected at its drain to the drain of the P-channel MOS transistor 36 and at its gate to the source of the N +- gate MOS transistor 37.
  • Another N-channel MOS transistor 39 is connected at its drain to the source of the N +- gate MOS transistor 38, at its gate to the bias voltage input terminal 35 and at its source to the negative power supply terminal.
  • the combination of the MOS transistors 36 to 39 operates in a manner similar to the operation of the aforementioned combination of the MOS transistors 30 to 33, and the current flowing through the N-channel MOS transistor 39 is equal to that flowing through the N-channel MOS transistor 33. Therefore, for the same reason described for the combination of the MOS transistors 30 to 33, the drain voltage of the P-channel MOS transistor 36 is equal to the drain-source voltage V D1 of the N +- gate MOS transistor 12.
  • the threshold voltage level of the N -gate MOS transistor 12 is lowered to reduce the gate voltage of the N -gate MOS transistor, and, at the same time, the on-state resistance of the P-channel MOS transistor 30 is decreased to raise the drain volage of the P-channel MOS transistor 30. Due to this rise in the drain voltage of the P-channel MOS transistor 30, the gate voltages of the P-channel MOS transistor 36 and N +- gate MOS transistor 37 having been stabilized at V D1 are raised to increase the on-state resistance of the P-channel MOS transistor 36, with the result that the drain voltage of the P-channel MOS transistor 36 drops by the amount corresponding to the temperature variation, and the resultant voltage variation is applied to the gate of the P-channel MOS transistor 10.
  • the value of ⁇ V thn+ of the N + -gate MOS transistor 12 increases to increase the drain voltage thereof.
  • the gate voltages of the N +- gate MOS transistor 31 and P-channel MOS transistors 30 are raised to increase the on-state resistance of the P-channel MOS transistor 30.
  • the drain voltage of the P-channel MOS transistor 30 drops to cause a corresponding drop of the gate voltages of the P-channel MOS transistor 30 and N +- gate MOS transistor 37 having been stabilized at V D1 .
  • the on-state resistance of the P-channel MOS transistor 36 decreases to raise the drain voltage thereof, and the on-state resistance of the P-channel MOS transistor 10 increases with the rise of the gate voltage of the P-channel MOS transistor 10. Consequently, the current flowing through the N +- gate MOS transistor 12 decreases, and its drain voltage drops to compensate the variation of V thn + attributable to the temperature drop.
  • Fig. 12 is a circuit diagram showing the structure of yet another embodiment of the present invention. That is, Fig. 12 shows another form of the reference voltage generating circuit which is provided with the function of temperature compensation and adapted for amplifying the threshold voltage difference by the factor of 2.
  • a gate bias voltage is applied from a bias voltage input terminal 350 to the gates of MOS transistors 330, 390 and 400, and the value of current flowing through the MOS transistor 400 is two times as large as that flowing through each of . the MOS transistors 330 and 390.
  • the structure shown in Fig. 12 is based on that shown in Fig. 8 and differs from that shown in Fig. 11.
  • the embodiment shown in Fig. 12 has a higher degree of freedom than that shown in Fig. 11 in regard to the function of temperature compensation. It is apparent that the principle of temperature compensation in Fig. 12 is similar to that described with reference to Fig. 11.
  • Fig. 13 is a graph showing the VGS-ID characteristics of MOS transistors to illustrate the function of temperature compensation in Fig. 12 from the aspect of the MOS characteristics.
  • the characteristic curve (A) represents the characteristic of an intrinsic-gate MOS transistor
  • the characteristic curve (B) represents the characteristic of an N +- gate MOS transistor
  • the characteristic curve (C) indicates how the characteristic of the N +- gate MOS transistor is shifted under influence of temperature.
  • the threshold voltage difference at a drain current I D1' that is, the voltage difference (V b - V a ) in Fig. 12 is ⁇ V 1 .
  • the characteristic of the N + -gate MOS transistor is shifted from the curve (B) to the curve (C) under influence of temperature, and the voltage difference (V b - V a ) increases to AV 2 from ⁇ V 1 . Since the threshold voltage level of the N +- gate MOS transistor is lowered under the above situation, more current can now flow therethrough, and the current value flowing through the N +- gate MOS transistor changes to I D2 from I D1 .
  • the threshold voltage difference is now practically determined by I Dl on the characteristic curve (A) and I D2 on the characteristic curve (C) so that the voltage difference (V b - V a ) approaches ⁇ V 1 representing the value of voltage appearing in the absence of any temperature variation.
  • Fig. 14 is a circuit diagram showing the structure of a further embodiment of the present invention.
  • the numerals 1 to 40 designate the same parts as those appearing in Fig. 11.
  • a P-channel MOS transistor 60 is connected at its source to the positive supply terminal 1 and at its gate to its drain.
  • An N-channel MOS transistor 61 is connected at its drain to the drain of the P-channel MOS transistor 60 and to the gate of the N-channel MOS transistor 33, at its gate to its drain and at its source to the negative power supply terminal.
  • Another P-channel MOS transistor 70 is connected at its source to the positive power supply terminal 1 and at its gate to the drain of the P -channel MOS transistor 20.
  • Another N-channel MOS- transistor 71 is connected at its drain to the drain of the P-channel MOS transistor 70, at its gate to the drain of the N-channel MOS transistor 61 and at its source to the negative power supply terminal.
  • the numeral 80 designates a reference voltage output terminal in this embodiment of the present invention.
  • the P-channel MOS transistor 60 and the N-channel MOS transistor 61 constitute a bias circuit.
  • Current I 60 flowing through the P-channel MOS transistor 60 in its saturation region is expressed as follows:
  • any desired bias voltage V B can be obtained by suitably selecting the dimension ratios of the P-channel MOS transistor 60 and N-channel MOS transistor 61.
  • the P-channel MOS transistor 70 and N-channel MOS transistor 71 constitute a buffer circuit, and the gate voltage of the P-channel MOS transistor 70 varying depending on the threshold voltage difference changes the on-state resistance of this MOS transistor 70 so that an output voltage corresponding to the gate voltage of the P-channel MOS transistor 70 is generated.
  • Fig. 15 is a circuit diagram showing the structure of a still further embodiment of the present invention in which the threshold voltage difference between an N + -gate MOS transistor and an intrinsic-gate MO S transistor is utilized to amplify it by the factor of n (n: an integer) to provide such a reference voltage.
  • n an integer
  • Fig. 15 can provide an output voltage which is n times (n: an integer) as high as the threshold voltage difference between an N + -gate MOS transistor and an intrinsic-gate MOS transistor.
  • a arbitrary reference voltage output corresponding to a given threshold voltage difference can be provided by a structure as shown in Fig. 16.
  • Fig. 16 is a circuit diagram showing the structure of a yet further embodiment of the present invention in which the threshold voltage difference between an N + -gate MOS transistor and an intrinsic-gate MOS transistor arranged in pair is utilized to obtain any desired reference voltage and in which the numerals 1 to 71 designate the same functional parts as those explained with reference to Fig. 14.
  • an operational amplifier 100 is connected at its plus input terminal to the drain of the P-channel MOS transistor 70.
  • a resistor R 1 is connected at one end thereof to the minus input terminal of the operational amplifier 100 and at the other end thereof to the negative power supply terminal.
  • Another resistor R 2 is connected at one end thereof to the minus input terminal of the operational amplifier 100 and at the other end thereof to the output terminal of the operational amplifier 100.
  • V in is the drain voltage of the P-channel MOS transistor 70.
  • the output voltage of the reference voltage source structure shown in Fig. 16 appears also across the positive power supply terminal 1 and the drain of the P-channel MOS transistor 70.
  • Figs. 17 and 18 are circuit diagrams showing the structure of other forms of the reference voltage source based on the structure of Fig. 9 and adapted for amplifying the threshold voltage difference by the factor of n (n: an integer). That is, the basis idea of connecting the drain of a succeeding MOS transistor to the source of a preceding MOS transistor as described with reference to the embodiment shown in Fig. 8, - which basic idea is also applied to the embodiment shown in Fig. 9 - is also applied to the embodiments shown in Figs. 17 and 18. Therefore, the embodiments shown in Figs. 17 and 18 are modifications of those shown in Figs. 11 and 16 respectively.
  • Fig. 19 is a graph showing the power supply voltage - output voltage characteristics of two trial-fabricated models of the reference voltage source of the present invention utilizing the threshold voltage difference.
  • a reference voltage source of the band gap type capable of generation of any desired stable reference voltage can be provided regardless of whether it is of a C MOS structure or of a single-channel MOS structure, so that an IC including a built-in on-chip reference voltage source capable of operation with high accuracy can be fabricated.
  • a stable reference voltage substantially free from voltage variations attributable to process variables can be fabricated by the usual fabrication process.
  • the reference voltage can be set at any desired level.

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EP83105935A 1982-06-18 1983-06-16 Referenzspannungserzeugungsvorrichtung Withdrawn EP0097338A3 (de)

Applications Claiming Priority (2)

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JP103756/82 1982-06-18
JP10375682A JPS58221418A (ja) 1982-06-18 1982-06-18 基準電圧発生装置

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EP0097338A2 true EP0097338A2 (de) 1984-01-04
EP0097338A3 EP0097338A3 (de) 1984-10-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0183185A3 (en) * 1984-11-22 1986-12-30 Cselt Centro Studi E Laboratori Telecomunicazioni S.P.A. Differential reference voltage generator for nmos single-supply integrated circuits

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900019026A (ko) * 1989-05-11 1990-12-22 김광호 반도체 장치의 기준전압 발생회로
JP4830088B2 (ja) * 2005-11-10 2011-12-07 学校法人日本大学 基準電圧発生回路

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JPS5539411A (en) * 1978-09-13 1980-03-19 Hitachi Ltd Reference voltage generator
CH657712A5 (de) * 1978-03-08 1986-09-15 Hitachi Ltd Referenzspannungserzeuger.
CH628462A5 (fr) * 1978-12-22 1982-02-26 Centre Electron Horloger Source de tension de reference.
US4206946A (en) * 1979-03-19 1980-06-10 General Motors Corporation Vehicle convertible seat and locking arrangement

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EP0183185A3 (en) * 1984-11-22 1986-12-30 Cselt Centro Studi E Laboratori Telecomunicazioni S.P.A. Differential reference voltage generator for nmos single-supply integrated circuits

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JPS58221418A (ja) 1983-12-23
EP0097338A3 (de) 1984-10-24

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