EP0097338A2

EP0097338A2 - Reference voltage generating device

Info

Publication number: EP0097338A2
Application number: EP83105935A
Authority: EP
Inventors: Shoichi Ohzeki; Toji Mukai; Nobuaki Miyakawa; Takahide Ikeda
Original assignee: Hitachi Ltd; Hitachi Haramachi Electronics Ltd
Current assignee: Hitachi Ltd; Hitachi Power Semiconductor Device Ltd
Priority date: 1982-06-18
Filing date: 1983-06-16
Publication date: 1984-01-04
Also published as: EP0097338A3; JPS58221418A

Abstract

A reference voltage generating device comprises a first MOS transistor whose gate electrode (3011) is formed of an N-type semiconductor of a semiconductive material and a second MOS transistor whose gate electrode (3021) is formed of an intrinsic semiconductor (3021) of the same semiconductor material. In the device, the voltage corresponding to the difference between the Fermi energy levels of the semiconductors (3011, 3021) is derived utilizing the threshold voltage difference (V_thi- V_thn +) between the first and second MOS transistors.

Description

This invention relates to a reference voltage generating device formed of semiconductors.
Sources of reference voltage used hitherto utilize, for example, a forward voltage drop V_. of a _PN junction diode, a reverse breakdown voltage (the zener voltage) V_Zof such a junction diode and a threshold voltage V_th of an insulated-gate field effect transistor. Further, an insulated-gate transistor of the type in which its threshold voltage V_th is structurally equal to the hand gap has been proposed and fabricated already. However, each of the prior art reference voltage sources of the types above described includes various factors causing variations of its output voltage depending on the conditions of its fabrication process and the factors of the process controlling the physical quantities.
A prior art reference voltage source of the hand gap type utilizes the threshold voltage difference between an N^+-gate MOS transistor and a P^+-gate MOS transistor, as disclosed in, for example, Japanese Patent Application Laid-Open No. 51-149780; IEEE, Vol. SC-15, No. 3 JUNE 1980, pp. 264-269; and DE-OS 2951835. Also, a reference voltage source utilizing the threshold voltage difference between an enhancement type MOS transistor and a depletion type MOS transistor is disclosed in a literature such as IEEE, 1978, pp. 50-51.
An N^+-gate MOS transistor has a threshold voltage attributable to the doping of its gate layer with a pentavalent doner impurity, while a P^+-gate MOS transistor has a threshold voltage attributable to the doping of its gate layer with a trivalent acceptor impurity.
Generally, the trivalent impurity has a large coefficient of diffusion into an oxide film and thus diffuses into the bulk layer directly beneath the gate through a thin oxide film such as a gate oxide film. Therefore, the threshold voltage V_th of the P -gate MOS transistor determined depending on the impurity concentration of the bulk layer tends to vary, and the output voltage of the reference voltage source utilizing the P^+-gate MOS transistor tends also to vary or fluctuate.
FIG. 1 shows the prior art structure of a P -gate MOS transistor and an N -gate MOS transistor fabricated according to the silicon gate process.
FIG. 2 shows, by way of example, the results of measurement of the threshold voltages V_th of the P⁺-gate and N^+-gate MOS transistors shown in FIG. 1 when the gate layer of the P^+-gate MOS transistor was doped with an acceptor impurity such as boron, and the gate layer of the N -gate _MOS transistor was doped with a doner impurity such as phosphorus. (The gate film thickness = 500 Å.) It will be seen in FIG. 2 that, according to the results of measurement on eight sampled chips in the same wafer, the values of the threshold voltage V_th are substantially constant in the case of the N^+-gate MOS transistor, while, on the other hand, the values of the threshold voltage Vt_h are dispersed in the case of the P^+-gate MOS transistor. This is considered to be attributable to the fact that, in the case of the P^+-gate MOS transistor, the acceptor impurity such as boron diffuses into the bulk layer though the gate oxide film thereby causing variations of the threshold voltage Vt_h of the P⁺-gate MOS transistor. To deal with such an undesirable situation, the thickness of the gate oxide film must be made larger than hitherto or an insulator film such as a nitride film must additionally be disposed on the gate oxide film.
However, such an additional layer cannot be provided by the same process forming the other circuit portions, and the resultant process alternation leads to an undesirable increase in the cost of fabrication. Further, in view of the future tendency toward fabrication of MOS transistors of finer patterns, the thickness of the gate oxide film will be required to be smaller than hitherto, and in order to meet such a demand, a measure must be taken which can sufficiently suppress threshold voltage variations tending to occur more frequently due to the smaller thickness of the gate oxide film.
It is therefore an object of the present invention to provide a reference voltage generating device which can generate a stable reference voltage substantially free from variations or fluctuations attributable to fabrication process variables in spite of the fact that it is fabricated according to the process customarily employed in this field of art.
Another object of the present invention is to provide a reference voltage generating device generating a reference voltage which can be set at any desired level.
It is the first feature of the reference voltage generating device of the present invention that it comprises an N-type semiconductor and an intrinsic semiconductor both of which are formed of the same semiconductive material, and means for deriving a voltage corresponding to the difference between the Fermi energy levels of these semiconductors.
It is the second feature of the reference voltage generating device of the present invention that it comprises a semiconductor of a first conductivity type and a semiconductor of a second conductivity type both of which are formed of the same semiconductive material, means for deriving a voltage corresponding to the difference between the Fermi energy levels of these semiconductors, and means for amplifying the voltage.
The present invention will now be described in detail with reference to the accompanying drawings, in which:

Fig. 1 shows the prior art structure of a p^+-gate MOS transistor and an N^+-gate MOS transistor fabricated according to the silicon gate process;
Fig. 2 is a graph showing, by way of example, the results of measurement of the threshold voltages of the P^+-gate and N^+-gate MOS transistors having the prior art structure shown in Fig. 1 when the gate layer of the P^+-gate MOS transistor is doped with boron, while the gate layer of the N^+-gate MOS transistor is doped with phosphorus;
Fig. 3(A) shows the basic structure of the reference voltage generating device according to the present invention including an N^+-gate MOS transistor whose gate layer is doped with phosphorus and an intrinsic-gate MOS transistor whose gate layer is non- doped;
Fig. 3(B) is a graph showing, by way of example, the results of measurement of the threshold voltages of the MOS transistors shown in Fig. 3(A);
Figs. 4(A) and 4(B) illustrate the state of energy and the state of charges respectively in a model composed of an N^+-type semiconductor, an insulator and an N-type semiconductor;
Fig. 5(A) is a circuit diagram showing the structure of the basic MOS diode circuit of the present invention for deriving the difference between the threshold voltages V_th of two MOS transistors having different threshold voltages V_th respectively;
_Fig. ₅(_B) is a graph showing the V_GS-I_DS characteristic of the circuit shown in Fig. 5(A);
Fig. 6 is a circuit diagram showing the structure of an embodiment of the present invention adapted for amplifying the threshold voltage difference by, . for example, the factor of 2 according to the basic idea of the present invention;
Fig. 7 is a circuit diagram showing the structure of another embodiment of the present invention adapted for amplifying the threshold voltage difference by the factor of n (n: an integer) in a manner similar to that shown in Fig. 6;
_Fig. 8 is a circuit diagram showing the structure of a modification of the embodiment shown in Fig. 6;
Fig. 9 is a circuit diagram showing the structure of a modification of the embodiment shown in Fig. _'.7;
Figs. 10 (A) and 10(B) are graphs illustrating the band structure and the Fermi level E_f respectively of an N-type semiconductor;
Fig. 11 is a circuit diagram showing the structure of still another embodiment of the present invention which is additionally provided with the function of temperature compensation;
Fig. 12 is a circuit diagram showing the structure of yet another embodiment of the present invention which is also provided with the function of temperature compensation and adapted for amplifying the threshold voltage difference by the factor of 2;
_Fig. 13 is a graph showing the VGS -I_D characteristics of MOS transistors;
Fig. 14 is a circuit diagram showing the structure of a further embodiment of the present invention;
Fig. 15 is a circuit diagram showing the structure of a still further embodiment of the present invention adapted for amplifying the threshold voltage difference by the factor of n (n: an integer);
Fig. 16 is a circuit diagram showing the structure of a yet further embodiment of the present invention adapted for amplifying the threshold voltage difference by the factor of any desired value;
Figs.. 17 and 18 are circuit diagrams showing the structure of modifications of the embodiments shown in Figs. 11 and 16, respectively; and
Fig. 19 is a graph showing the output voltage. characteristic of two models of the present invention relative to variations of the power supply voltage.

Referring now to the drawings, Fig. 3(A) is a schematic sectional view showing the basic structure of the reference voltage generating device according to the present invention.
Referring to Fig. 3(A), the basic structure includes a P-channel N^+- gate MOS transistor 301 having a gate electrode 3011 provided by doping a polysilicon layer with phosphorus so that its impurity concentration is preferably in the order of 10²⁰cm^-3 to 10²¹cm^-3, and a _P-channel intrinsic-gate MOS transistor 302 having a gate electrode 3021 provided by non-doping a polysilicon layer with any impurity. Fig. 3(B) is a graph showing, by way of example, the results of measurement of the threshold voltages V_th of these MOS transistor 301 and 302. The numerals 3012 and 3022 designate S _i0₂or like gate insulator layers. The term "intrinsic" is used herein to indicate that the specific layer is not doped with any impurity, and the impurity concentration of that layer is preferably not higher than 10¹⁴cm^-3. It will be seen from Fig. 3(B) that the threshold voltages V_th of both of the N^+- gate MOS transistor 301 and the intrinsic-gate MOS transistor 302 are substantially constant in the same wafer. The reference voltage generating device based on such a basic structure can be fabricated with little fabrication errors and can thus be utilized as a stable reference voltage source.
The threshold voltage V_th of such MOS transistors having a semiconductor gate electrode will be described with reference to Figs. 4(A) and 4(B). In the case of the N^+- gate MOS transistor 301 shown in Fig. 3A, the following equation holds as will be apparent from the energy band diagram of Fig. 4(A):
where

VG; potential difference between N-type semiconductor substrate 303 and gate electrode (N^+-type semiconductor)
X; electron affinity
Eq; energy gap
φs; surface potential of N-type semiconductor substrate 303
φ_FN+; Fermi potential of N-type semiconductor substrate 303 when Fermi potential of N⁺-type semiconductor is taken as reference
φ_Fi; Fermi potential of N-type semiconductor substrate 303 when Fermi potential of intrinsic semiconductor is taken as reference
q; unit charge of electrons
V₀; potential difference applied across insulator
E_c; lower limit of energy level of conduction band
E_v; upper limit of energy level of valence band
E_i; Fermi level of intrinsic semiconductor When, in the equation (1), the work function of the gate electrode 3011 of the N^+- gate MOS transistor 301 is expressed by the potential φ_MN ⁺, and the work function of the semiconductor is similarly expressed by the potential φ_si, the following equation (2) holds:
Since φ_si is given by
V₀ is expressed as follows:

Further, from the relation of the charges shown in Fig. 4(B), the following equation (5) holds:
where

C_OX; capacitance of insulator per unit area
Q_SS; fixed charges in insulator
Q_B; fixed charges produced by ionization of impurity in semiconductor substrate
Q_i; carriers formed as channel.

From the equations (4) and (5), the following equation (6) holds:
Since the gate voltage V_G provides the threshold voltage at the time of formation of the channel Q_i, the threshold voltage V_thn+ of the N^+- gate MOS transistor 301 is given by
In this case, φ_S = 2φ_F.
In the case of the intrinsic-gate MOS transistor 302 too, similar equations hold except the work function φ_Mi of its gate electrode 3021. The work function φ_Mi is expressed as follows:
Therefore, the threshold voltage V_thi of the MOS trans- sistor 302 is given by
In this case, φ_S ⁼ 2φ_F.
Consequently, the threshold voltage difference (V_thi - V_thn+) between the N+-gate MOS transistor 301 and the intrinsic-gate MOS transistor 302 is expressed as
Thus, the threshold voltage difference is equal to the difference between the Fermi potentials of the semiconductors forming the gate electrodes of the MOS transistors 301 and 302.
Description will then be directed to means for deriving the difference between the threshold voltages V_th of such MOS transistors.
Although a circuit which will be described below can be used as one of means for deriving the Fermi level difference |E_i-E_v| described above, such a circuit can generally be applied to a reference voltage generating device in which the voltage corresponding to the threshold voltage difference between FET's having different threshold voltages V_th is utilized to provide the reference voltage.
Fig. 5(A) is a circuit diagram of a circuit generating a voltage corresponding to the difference between the threshold voltages of MOS transistors, and Fig. 5(B) is a graph showing the V_GS- I_DS characteristic of the circuit shown in Fig. 5(A).
Referring to Fig. 5(A), MOS FET's T_N+ and T_i having different threshold voltages V_thn ⁺ and ^V _thi respectively but being substantially equal to each other in their mutual conductance β are each connected at the drain and gate in common to constitute so-called MOS diodes. The symbol I_o designates a constant cur- . rent source to which each MOS FET is connected, and V_N+ and V_ip designate the drain voltages of the _MOS FET's T_N+ and T_i respectively. Since I_o is expressed as
the drain voltages V_N+ and V_ip of the MOS FET's T_N+ and T_i are expressed as follows respectively:
Therefore, the difference between the threshold voltages V_thn+ and ^V _thi can be obtained by taking the difference between the drain voltages V_N+ and V_ip.
The constant current source I_o may be a resistor having a sufficiently high resistance. Provided that the resistance characteristic is uniform, the constant current source I_o may be a diffused resistor, a polycrystalline silicon resistor, a resistor made by ion implantation or a resistor utilizing a MOS transistor.
Thus, when the aforementioned N^+- gate MOS transistor 301 and intrinsic-gate MOS transistor 302 are used in place of these MOS transistors T_N+ and T respectively in the circuit shown in Fig. 5(A), the Fermi level difference |E_i - Ev| between the N-type semiconductor and the intrinsic semiconductor, which difference is substantially equal to the threshold voltage difference, can be derived from the circuit shown in Fig. 5(A).
The above description has referred to the circuit for deriving the difference between the threshold voltage V_th of the MOS transistor T_N+ and that V_th of the MOS transistor T_i. However, the value of the derived threshold voltage V_th difference is small as shown in Fig. 3(B). A method for amplifying the threshold voltage V_th difference by the factor of n (n: an integer) and utilizing such an amplified voltage as a reference voltage will now be described.
As described already, threshold voltages V_th of silicon-gate MOS transistors or an N^+-gate MOS transistor and an intrinsic-gate MOS transistor formed in the same wafer do not vary or fluctuate substantially, and a reference voltage generating circuit utilizing the threshold voltage difference between the N^+-gate MOS transistor and the intrinsic-gate MOS transistor can provide a stable output voltage. However, the level of the output voltage from such a reference voltage generating circuit is low compared with that of a reference voltage generating circuit utilizing the threshold voltage difference between a P^+-gate MOS transistor and an N -gate MOS transistor. Therefore, the output voltage from the MOS transistor pair is amplified by the factor of n (n: an integer), that is, by providing n pairs of N^+-gate MOS transistors and intrinsic-gate MOS transistors in the circuit to utilize the threshold voltage difference in each pair.
Fig. 6 is a circuit diagram showing the structure of an embodiment of the present invention adapted for amplifying the threshold voltage difference by the factor of 2 according to the basic idea of the present invention.
Referring to Fig. 6, a P-channel MOS transistor 10 is connected at its source to the positive terminal 1 of a power source of the reference voltage generating circuit. An N-channel N -gate MOS transistor 11 is connected at its drain and gate to the gate and drain respectively of the P-channel MOS transistor 10, and another N-channel N^+- gate MOS transistor 12 is connected at its drain and gate to the drain and source respectively of the N-channel N^+-gate MOS transistor 11 and at its source to the negative power supply terminal. Another P-channel MOS transistor 20 is connected at its source to the positive power supply terminal 1 and at its gate to the gate of the P-channel MOS transistor 10. An N-channel intrinsic-gate MOS transistor 21 is connected at its drain and gate to the drain of the P-channel MOS transistor 20, and another N-channel intrinsic-gate MOS transistor 22 is connected at its drain and gate to the drain and source respectively of the N-channel intrinsic-gate MOS transistor 21 and at its source to the negative power supply terminal.
Let V₁ be the drain-source voltage of the N-channel N^+- gate MOS transistor 12 in the arrangement of the MOS transistors 10, 11 and 12. Current I₁ flowing through this N-channel N^+- gate MOS transistor 12 is given by
where

β_on; channel conductance constant of N-channel N^+- gate MOS transistor 12
β₁₂; dimension ratio (channel width/channel length) of N-channel N^+- gate MOS transistor 12
V_thn+; threshold voltage of N-channel N⁺-gate MOS transistor 12.

On the other hand, current I₂ flowing through the N-channel intrinsic-gate MOS transistor 22 is given by

where

β₂₂; dimension ratio of N-channel intrinsic-gate MOS transistor 22
V_thi; threshold voltage of N-channel intrinsic-gate MOS transistor 22
V₂; drain-source voltage of N-channel intrinsic-gate MOS transistor 22.

Since the N-channel MOS transistors 11 and 22 have the same gate voltage, the currents I₁ and I₂ are equal to each other.
The drain-source voltages V₁ and V₂ of the MOS transistors 12 and 22 are computed from the equations (13) and (14) as follows respectively:
Suppose that the dimension ratios β₁₂ and β₂₂ are equal to each other, then, the following equation (17) holds:

V₁- V₂ = 2(V_thn+ - V_thi) ..... (17)

Thus, the drain voltage difference (V₁-V₂) between the N^+- gate MOS transistors 11, 12 and the intrinsic-gate MOS transistors 21, 22 provides a voltage equal to the factor-of-2 amplified threshold voltage difference.
Fig. 7 is a circuit diagram showing the structure of another embodiment of the present invention adapted for amplifying the threshold voltage difference by the factor of n (n: an integer). As in the case of Fig. 6, diode-connected N-channel N⁺-gate MOS transistors are connected between N-channel N^+- gate MOS transistors 11 and 12 to provide a total of n, and diode-connected N-channel intrinsic-gate MOS transistors are connected between N-channel intrinsic-gate MOS transistors 21 and 22 to provide a total of n. The difference between the drain-source voltages V₁' and V₂' of the N^+- gate MOS transistor 12 and intrinsic-gate MOS transistor 22 is expressed as follows:
Thus, the threshold voltage difference between the N^+-gate MOS transistor 11 and the intrinsic-gate MOS transistor 21 can be amplified by the factor of n.
Therefore, the method shown in Fig. 7 can be used for providing a reference voltage which is n (n: an integer) times as high as the threshold voltage difference between the N⁺-gate MOS transistor 11 and the intrinsic-gate MOS transistor 21. Although the circuits of C MOS structure including P-channel MO_S transistors acting as an active load combined with N-channel N^+-gate MOS transistors and N-channel intrinsic-gate MOS transistors have been described with reference to Figs. 6 and 7, by way of example, it is apparent that such a reference voltage can be similarly generated by the combination of P-channel N -gate MOS transistors and P-channel intrinsic-gate MOS transistors. It is also apparent that single-channel MOS transistors only may be similarly effectively used.
Embodiments shown in Figs. 8 and 9 correspond to or are modifications of those shown in Figs. 6 and 7 respectively. The modifications shown in Figs. 8 and 9 are adapted for amplifying the threshold voltage difference between an N-channel intrinsic-gate MOS transistor and an N-channel N^+-gate MOS transistor by the factors of 2 and n respectively. Thus, in the case of Fig. 8, the individual MOS transistors are diode-connected in two stages, while, in the case of Fig. 9, they are diode-connected in n stages.
The numerals 110 in Fig. 8 and lln, 120 in Fig. 9 designate N-channel N⁺-gate MOS transistors, and the numerals 210 in Fig. 8 and 21n, 220 in Fig. 9 designate N-channel intrinsic-gate MOS transistors.
The numerals 100 and 200 in each of Figs. 8 and 9 designate P-channel MOS transistors of current mirror arrangement as in the case of Figs. 6 and 7.
According to the embodiment shown in Fig. 8, the MOS transistors 120 and 220 are connected at their drains to the sources of the MOS transistors 110 and 210 respectively, so that the MOS transistors 120 and 220 are not adversely affected by the drift that may occur in the MOS transistors 110 and 210. Therefore, this embodiment is advantageous in that the operating characteristic of the reference voltage generating circuit can be stabilized. The same applies also to the embodiment shown in Fig. 9.
An energy level model of an N-type semiconductor and its temperature characteristic are shown in Figs. 10(A) and 10(B) respectively.
The carrier in such a semiconductor is electrons n_d ionized from a doner impurity N₃ and pairs of electrons and holes excited from the valence band. When the amount of the doner impurity N_d is sufficiently large, the excited electron-hole pairs can be neglected, and the number n of conduction electrons can be approximated as n
n_d. As is well known, N_dcan be computed from the probability of the number of electrons trapped at the doner level, and n can be computed from the number of electrons present in the conduction hand, as follows:

where

h; Planck's constant
m^*; effective mass of electron Therefore, the following equation holds:
And, N_d/N_c is expressed as follows:

Since it is now assumed that the Fermi level is close to the position of the level E , the first term in the equation (23) in the right-hand members in the equation (23) can be neglected, and the following equation (24) holds:
This equation (24) indicates that, when the impurity concentration N_d is high not only at a low temperature but also at the room temperature, the ratio N_c/N_dapproaches unity (1) to set up the relation N
. Therefore, the Fermi level is situated intermediate between the lower limit E_c of the con- duction band and the doner level E_d, and the temperature dependence becomes substantially equal to the temperature characteristic of E_c. However, when the temperature becomes sufficiently high, many pairs of electrons and holes are excited from the valence band to reduce the effect of the impurity, so that the Fermi level approaches the level E_i of the intrinsic semiconductor. The above relation is graphically shown in Fig. 10(B). When, for example, phosphorus P is used as an impurity to be doped in an N-type semiconductor in a process for fabricating S_i semiconductor integrated circuits, the temperature-dependent change of the differ- enc^e (E_FN - E_Fi) between the Fermi level of the N-type semiconductor and that of the intrinsic semiconductor is about 0.52 eV to 0.43 eV within the temperature range of 200·K to 400·K (-70°C to 130°C). Thus, the change rate is about 0.45 (mV/°C) (= 450 ppm/°C), and this means that the change rate has a large temperature dependence. Therefore, a compensation circuit which will be described now is required to ensure generation of a stable reference voltage.
A reference voltage generating circuit of the band gap type is advantageous over a reference voltage generating circuit of the type utilizing the threshold. voltage of a MOS transistor or the forward voltage drop of a diode in that the temperature-dependent change of its operating characteristic is less than that of the latter. However, the temperature dependence of such a reference voltage generating cirduit becomes a matter of consideration when such a circuit is incorporated in, for example, a high-accuracy analog circuit.
Fig. 11 is a circuit diagram showing the structure of still another embodiment of the present invention. That is, Fig. 11 shows one form of the reference voltage generating circuit of the band gap type which is provided with the function of temperature compensation. In Fig. 11, the numerals 1 to 22 designate the same parts as those appearing in Fig. 6 except the ground terminals of the N- channel MOS transistors 12 and 22.
Referring to Fig. 11, a P-channel MOS transistor 30 is connected at its source to the positive power supply terminal 1. An N-channel N^+- gate MOS transistor 31 is connected at its drain and gate to the drain and gate of the P-channel MOS transistor 30 respectively. An N-channel N^+- gate MOS transistor 32 is connected at its drain to the drain of the P-channel MOS transistor 30 and at its gate to the source of the N^+- gate MOS transistor 31. An N-channel MOS transistor 33 is connected at its drain to the source of the N⁺-gate MOS transistor 32 and at its source to the negative power supply terminal. A bias voltage input terminal . 35 is connected to the gate of the N-channel MOS transistor 33. Another N-channel MOS transistor 40 is connected at its drain to the sources of the N^+-gate and intrinsic-gate MOS transistors 12 and 22, at its gate to the bias voltage input terminal 35 and at its source to the negative power supply terminal.
When now a bias voltage V_B is applied to the bias voltage input terminal 35, currents I₃₃ and I₄₀ as shown below flow through the N- channel MOS transistors 33 and 40 respectively:

where

β_33' β₄₀; dimension ratios of respective _N- channel MOS transistors 33 and 40
V_thn; threshold voltage of N- channel MOS transistors 33 and 40

The ratio between I₃₃ and I₄₀ is 1:2 when the ratio between β₃₃ and β₄₀ is selected to be 1:2.
That is, the value of constant current flowing through the N-channel MOS transistor 33 is one-half the value of constant current flowing through the N-channel MOS transistor 40, or the relation 2I₃₃= I₄₀ holds in this case.
The drain voltage V_D1 appearing at the drain. of the N^+- gate MOS transistor 12 provides the gate voltage of the P-channel MOS transistor 30 and N-channel MOS transistor 31, and the current I₁ flowing through the N-channel N^+- gate MOS transistors 31, 32 and P-channel MOS transistor 30 is given by

where β_p, β_n+; dimension ratios of respective P channel MOS transistor 30 and n gate transistors 31, 32. From these two equations (27) and (28), the drain voltage V_D1 of the N^+- gate MOS transistor 12 is computed as follows:
On the other hand, since the gate voltages of the P- channel MOS transistors 10 and 20 are equal to each other, the current flowing through the N^+- gate MOS transistor 12 is equal to that flowing through the intrinsic-gate MOS transistor 22, and the sum of these currents flows through the N-channel MOS transistor 40.
When the relation between the current flowing through the N-channel MOS transistor 33 and that flowing through the N-channel MOS transistor 40 is selected to be 1:2 as described above, the currents flowing through the N^+- gate MOS transistors 12 and 32 are equal to each other, and the drain voltage of the P-channel MOS transistor 30 is also equal to V_D1. That is, the input and output voltages of the circuit composed of the MOS transistors 30 to 33 are equal to each other, and such a relation establishes the most stable state.
Another P-channel MOS transistor 36 is connected at its source to the positive power supply terminal 1, at its gate to the drain of the N^+- gate MOS transistor 31 and at its drain to the gate of the _P-channel MOS transistor 10. Another N-channel _N ^+-gate M_OS transistor 37 is connected at its drain and gate to the drain and gate of the P-channel MOS transistor 36 respectively. Another N-channel N^+- gate MOS transistor 38 is connected at its drain to the drain of the P-channel MOS transistor 36 and at its gate to the source of the N^+- gate MOS transistor 37. Another N-channel MOS transistor 39 is connected at its drain to the source of the N^+- gate MOS transistor 38, at its gate to the bias voltage input terminal 35 and at its source to the negative power supply terminal.
The combination of the MOS transistors 36 to 39 operates in a manner similar to the operation of the aforementioned combination of the MOS transistors 30 to 33, and the current flowing through the N-channel MOS transistor 39 is equal to that flowing through the N-channel MOS transistor 33. Therefore, for the same reason described for the combination of the MOS transistors 30 to 33, the drain voltage of the P-channel MOS transistor 36 is equal to the drain-source voltage V_D1 of the N^+- gate MOS transistor 12.
When a temperature variation is taken into consideration, the equation (17) is rewritten as follows:
In the above equation (30), 2 Δ_thn+T is the term indicative of the temperature variation of the N^+-gate MOS transistors, and, ideally, (V₁ - V₂) in the circuit including the intrinsic-gate MOS transistors 21 and 22 is expressed by the equation (30) since these intrinsic-gate MOS transistors are not affected by a temperature. variation.
When now the temperature rises, the threshold voltage level of the N -gate MOS transistor 12 is lowered to reduce the gate voltage of the N -gate MOS transistor, and, at the same time, the on-state resistance of the P-channel MOS transistor 30 is decreased to raise the drain volage of the P-channel MOS transistor 30. Due to this rise in the drain voltage of the P-channel MOS transistor 30, the gate voltages of the P-channel MOS transistor 36 and N^+- gate MOS transistor 37 having been stabilized at V_D1 are raised to increase the on-state resistance of the P-channel MOS transistor 36, with the result that the drain voltage of the P-channel MOS transistor 36 drops by the amount corresponding to the temperature variation, and the resultant voltage variation is applied to the gate of the P-channel MOS transistor 10. Due to the drop of the gate voltage of the P-channel MOS transistor 10, its on-state resistance decreases to increase the current supplied to the N^+- gate MOS transistor 12 thereby raising the drain voltage thereof. Thus, the variation of the threshold voltage V_th attributable to the temperature rise can be compensated.
When, on the other hand, the temperature drops, the value of ΔV_thn+ of the N⁺-gate MOS transistor 12 increases to increase the drain voltage thereof. As a result of such a voltage variation, the gate voltages of the N^+- gate MOS transistor 31 and P-channel MOS transistors 30 are raised to increase the on-state resistance of the P-channel MOS transistor 30. As a result of such a resistance variation, the drain voltage of the P-channel MOS transistor 30 drops to cause a corresponding drop of the gate voltages of the P-channel MOS transistor 30 and N^+- gate MOS transistor 37 having been stabilized at V_D1. Due to such a voltage variation, the on-state resistance of the P-channel MOS transistor 36 decreases to raise the drain voltage thereof, and the on-state resistance of the P-channel MOS transistor 10 increases with the rise of the gate voltage of the P-channel MOS transistor 10. Consequently, the current flowing through the N^+- gate MOS transistor 12 decreases, and its drain voltage drops to compensate the variation of V_thn+ attributable to the temperature drop.
Fig. 12 is a circuit diagram showing the structure of yet another embodiment of the present invention. That is, Fig. 12 shows another form of the reference voltage generating circuit which is provided with the function of temperature compensation and adapted for amplifying the threshold voltage difference by the factor of 2.
Referring to Fig. 12, a gate bias voltage is applied from a bias voltage input terminal 350 to the gates of MOS transistors 330, 390 and 400, and the value of current flowing through the MOS transistor 400 is two times as large as that flowing through each of . the MOS transistors 330 and 390. The structure shown in Fig. 12 is based on that shown in Fig. 8 and differs from that shown in Fig. 11. The embodiment shown in Fig. 12 has a higher degree of freedom than that shown in Fig. 11 in regard to the function of temperature compensation. It is apparent that the principle of temperature compensation in Fig. 12 is similar to that described with reference to Fig. 11.
Fig. 13 is a graph showing the VGS-ID characteristics of MOS transistors to illustrate the function of temperature compensation in Fig. 12 from the aspect of the MOS characteristics. In Fig. 13, the characteristic curve (A) represents the characteristic of an intrinsic-gate MOS transistor, the characteristic curve (B) represents the characteristic of an N^+-gate MOS transistor, and the characteristic curve (C) indicates how the characteristic of the N^+-gate MOS transistor is shifted under influence of temperature.
In the absence of any influence of temperature, the threshold voltage difference at a drain current I_D1' that is, the voltage difference (V_b- V_a) in Fig. 12 is ΔV₁ . In the presence of a temperature variation, the characteristic of the N⁺-gate MOS transistor is shifted from the curve (B) to the curve (C) under influence of temperature, and the voltage difference (V_b- V_a) increases to AV₂ from ΔV₁. Since the threshold voltage level of the N^+-gate MOS transistor is lowered under the above situation, more current can now flow therethrough, and the current value flowing through the N^+-gate MOS transistor changes to I_D2 from I_D1. Thus, the threshold voltage difference is now practically determined by I_Dl on the characteristic curve (A) and I_D2 on the characteristic curve (C) so that the voltage difference (V_b- V_a) approaches ΔV₁ representing the value of voltage appearing in the absence of any temperature variation.
Fig. 14 is a circuit diagram showing the structure of a further embodiment of the present invention. In Fig. 14, the numerals 1 to 40 designate the same parts as those appearing in Fig. 11.
Referring to Fig. 14, a P-channel MOS transistor 60 is connected at its source to the positive supply terminal 1 and at its gate to its drain. An N-channel MOS transistor 61 is connected at its drain to the drain of the P-channel MOS transistor 60 and to the gate of the N-channel MOS transistor 33, at its gate to its drain and at its source to the negative power supply terminal. Another P-channel MOS transistor 70 is connected at its source to the positive power supply terminal 1 and at its gate to the drain of the _P-channel MOS transistor 20. Another N-channel MOS- transistor 71 is connected at its drain to the drain of the P-channel MOS transistor 70, at its gate to the drain of the N-channel MOS transistor 61 and at its source to the negative power supply terminal. The numeral 80 designates a reference voltage output terminal in this embodiment of the present invention.
The P-channel MOS transistor 60 and the N-channel MOS transistor 61 constitute a bias circuit. Current I₆₀ flowing through the P-channel MOS transistor 60 in its saturation region is expressed as follows:
where

β₆₀; dimension ratio of P-channel MOS transistor 60
V_BI drain voltage of P-channel MOS transistor 60
V_thp; threshold voltage of P-channel MOS transistor 60

Similarly, current I₆₁ flowing through the N-channel MOS transistor 61 is expressed as follows:
where

β₆₁; dimension ratio of N-channel MOS transistor 61
V_thn; threshold voltage of N-channel MOS transistor 61

From the relation I60 I61' the drain voltage V_B of the P-channel MOS transistor 60 is expressed as follows:
Therefore, any desired bias voltage V_B can be obtained by suitably selecting the dimension ratios of the P-channel MOS transistor 60 and N-channel MOS transistor 61. The P-channel MOS transistor 70 and N-channel MOS transistor 71 constitute a buffer circuit, and the gate voltage of the P-channel MOS transistor 70 varying depending on the threshold voltage difference changes the on-state resistance of this MOS transistor 70 so that an output voltage corresponding to the gate voltage of the P-channel MOS transistor 70 is generated.
In Fig. 14, this output voltage appears across the output terminal 80 and the positive power supply terminal 1.
Fig. 15 is a circuit diagram showing the structure of a still further embodiment of the present invention in which the threshold voltage difference between an N⁺-gate MOS transistor and an intrinsic-gate _MOS transistor is utilized to amplify it by the factor of n (n: an integer) to provide such a reference voltage. Actually, the structure shown in Fig. 15 is the combination of those shown in Figs. 7 and 14.
Thus, such an embodiment of the present invention provides the following advantages:

(1) A reference voltage source substantially free from output voltage variations attributable to process variables can be provided, and it generates an output voltage which is n times (n: an integer) as high as the threshold voltage difference between an N^+-gate MOS transistor and an intrinsic-gate MOS transistor. Therefore, the applicable range of the reference voltage source in IC's can be widened.
(2) A temperature compensation circuit minimizes the influence of temperature variations in such a reference voltage source of the band gap type so that the reference voltage source of the band gap type can operate without being appreciably affected by the temperature variation.

It will thus be seen that the embodiment of the present invention shown in Fig. 15 can provide an output voltage which is n times (n: an integer) as high as the threshold voltage difference between an N⁺-gate MOS transistor and an intrinsic-gate MOS transistor. A arbitrary reference voltage output corresponding to a given threshold voltage difference can be provided by a structure as shown in Fig. 16.
Fig. 16 is a circuit diagram showing the structure of a yet further embodiment of the present invention in which the threshold voltage difference between an N⁺-gate MOS transistor and an intrinsic-gate MOS transistor arranged in pair is utilized to obtain any desired reference voltage and in which the numerals 1 to 71 designate the same functional parts as those explained with reference to Fig. 14.
Referring to Fig. 16, an operational amplifier 100 is connected at its plus input terminal to the drain of the P-channel MOS transistor 70. A resistor R₁ is connected at one end thereof to the minus input terminal of the operational amplifier 100 and at the other end thereof to the negative power supply terminal. Another resistor R₂ is connected at one end thereof to the minus input terminal of the operational amplifier 100 and at the other end thereof to the output terminal of the operational amplifier 100.
The output voltage V₀ appearing at the output terminal 101 of the operational amplifier 100 is expressed as follows:
where V_in is the drain voltage of the P-channel MOS transistor 70. The output voltage of the reference voltage source structure shown in Fig. 16 appears also across the positive power supply terminal 1 and the drain of the P-channel MOS transistor 70.
Figs. 17 and 18 are circuit diagrams showing the structure of other forms of the reference voltage source based on the structure of Fig. 9 and adapted for amplifying the threshold voltage difference by the factor of n (n: an integer). That is, the basis idea of connecting the drain of a succeeding MOS transistor to the source of a preceding MOS transistor as described with reference to the embodiment shown in Fig. 8, - which basic idea is also applied to the embodiment shown in Fig. 9 - is also applied to the embodiments shown in Figs. 17 and 18. Therefore, the embodiments shown in Figs. 17 and 18 are modifications of those shown in Figs. 11 and 16 respectively.
The output voltage V₀ appearing at the output terminal 1010 of an operational amplifier 1000 in Fig. 18 is expressed as follows:
Fig. 19 is a graph showing the power supply voltage - output voltage characteristics of two trial-fabricated models of the reference voltage source of the present invention utilizing the threshold voltage difference. The structure shown in the lower part of Fig. 19 includes a pair of an N^+-gate MOS transistor and an intrinsic-gate MOS transistor, while that shown in the upper part includes two pairs of such transistors (Fig. 14). However, the models do not include the temperature compensation circuit. It will be seen in Fig. 19 that V_ref = V₁- V₂ varies only within the range of t15 mV (the range defined between the two lines) in each case even when the power supply voltage V_DD varies between 4.5 V and 5.5 V.
More precisely, even when the power supply voltage V_DD varies between 4.5 V and 5.5 V, it will be apparent from Fig. 19 that the output voltage of the circuit shown in the lower part of Fig. 19 is maintained stable at about 0.55 V. In the case of the lower-part circuit which provides the output voltage two times as high as that of the upper-part circuit, it will be also apparent from Fig. 19 that the output voltage is maintained quite stable regardless of variations of the power supply voltage ^V _DD.
It will be understood from the foregoing detailed description of various embodiments and modifications of the present invention that a reference voltage source of the band gap type capable of generation of any desired stable reference voltage can be provided regardless of whether it is of a C MOS structure or of a single-channel MOS structure, so that an IC including a built-in on-chip reference voltage source capable of operation with high accuracy can be fabricated.
According to the reference voltage source of the present invention, a stable reference voltage substantially free from voltage variations attributable to process variables can be fabricated by the usual fabrication process.
Also, according to the present invention, the reference voltage can be set at any desired level.

Claims

1. A reference voltage generating devise comprising an N-type semiconductor (3011) and an intrinsic semiconductor (3021) both of which are formed of the same semiconductive material, and means (FIG. 5) for deriving a voltage corresponding to the difference between the Fermi energy levels of said semiconductors.

2. A reference voltage generating device as claimed in Claim 1, wherein said N-type semiconductor (3011) provides the gate electrode (3012) of a first MOS transistor, said intrinsic semiconductor (3021) provides the gate electrode (3022) of a second MOS transistor formed in the same semiconductor substrate (303) as that of said first MOS transistor, and said means for deriving the voltage corresponding to said difference between the Fermi energy levels utilizes the threshold voltage difference (V_thi - Vthn+) betweeen said first and second MOS transistors.

3. A reference voltage generating device comprising a semiconductor (3011) of a first conductivity type and a semiconductor (3021) of a second conductivity type both of which are formed of the same semiconductive material, means for deriving a voltage corresponding to the difference between the Fermi energy levels of said semiconductors, and means for amplifying voltage.

4. A reference voltage generating device as claimed in Claim 3, wherein said means for amplifying said voltage is means (FIG. 6 to 9) for amplifying said voltage by the factor of n (n: an integer).

5. A reference voltage generating device as claimed in Claim 3, wherein said semiconductor (3011) of the first conductivity type provides the gate electrode (3012) of a first MOS transistor (11), said semiconductor (3021) of the second conductivity type provides the gate electrode (3021) of a second MOS transistor (21) formed in the same semiconductor substrate (303) as that of said first MOS transistor, said means for deriving the voltage corresponding to said difference between the Fermi energy levels utilizes the threshold voltage difference (V_thi- V_thn+) between said first and second MOS transistors, and said means for amplifying said voltage includes a third MOS transistor (12) whose gate electrode is formed of the semiconductor of the first conductivity type and which is connected at its drain (source) to the gate of said first MOS transistor (11) and at its gate to the source (drain) of said first MOS transistor (11), and a fourth _MOS transistor (22) whose gate electrode is made of the semiconductor of the second conductivity type and which is connected at its source (drain) to the gate of said second MOS transistor (21) and at its drain (source) to the drain (source) of said second MOS transistor (21).

6. A reference voltage generating device as claimed in Claim 5, wherein n (n > 1) MOS transistors (1n) each having its gate electrode formed of the semiconductor of the first conductivity type are diode-connected between the source (drain) of said first MOS transistor (11) and the gate of said third MOS transistor (12), and n (n > 1) MOS transistors (2n) each having its gate electrode formed of the semiconductor of the second conductivity type are diode-connected between the source (drain) of said second MOS transistor (21) and the gate of said fourth MOS transistor (22).

7. A reference voltage generating device as claimed in Claim 3, wherein said semiconductor (3011) of the first conductivity type provides the gate electrode (3011) of a first MOS transistor (110), said semiconductor (3021) of the second conductivity type provides the gate electrode (3021) of a second MOS transistor (210) formed in the same semiconductor substrate (303) as that of said first MOS transistor, said means for deriving the voltage conrresponding to said difference between the Fermi energy levels utilizes the threshold voltage difference (V_thi - V_thn+) between said first and second MOS transistors, and said means for amplifying said voltage includes a third MOS transistor (120) whose gate electrode is formed of the semiconductor of the first conductivity type and which is connected at its drain (source) and gate to the source (drain) of said first MOS transistor (110), and a fourth MOS transistor (220) whose gate is formed of the semiconductor of the second conductivity type and which is connected at its drain (source) and gate to the source (drain) of said second MOS transistor (210).

8. A reference voltage generating device as claimed in Claim 7, wherein n (n > 1) MOS transistors (lln) each having its gate electrode formed of the semiconductor of the first conductivity type are diode-connected between the source (drain) of said first MOS transistor (110) and the gate and drain (source) of said third MOS transistor (120), and n (n > 1) MOS transistors (21ⁿ) each having its gate electrode formed of the semiconductor of the second conductivity type are diode-connected between the source (drain) of said second MOS transistor (210) and the gate and drain (source) of said fourth MOS transistor (220).

9. A reference voltage generating device as claimed in Claim 3, further comprising a circuit for compensating temperature variation of at least one of said semiconductor (3011) of the first conductivity type and said semiconductor (3021) of the second conductivity type, said temperature compensation circuit including a first and a second control circuit so that current supplied to said semiconductors of the first and second conductivity types can be controlled depending on a temperature variation.

10. A reference voltage generating device as claimed in Claim 9, wherein said first control circuit includes a P-channel MOS transistor (30) connected at its source (drain) to a positive power supply terminal (1), a first N-channel N^+-gate MOS transistor (31) connected at its drain (source) to the drain (source) of said P-channel MOS transistor (30) and at its gate to the gate of said MOS transistor (30), a second N^f-gate MOS transistor (32) connected at its drain (source) to the drain (source) of said P-channel MOS transistor (30.) and at its gate to the source (drain) of said first N^+-gate MOS transistor (31), and a third N-channel M_OS transistor (33) connected at its drain (source) to the source (drain) of said second N^+-gate MOS transistor (32), at its source (drain) to a negative power supply terminal and at its gate to a bias voltage input terminal (35); and said second control circuit includes a P-channel MOS transistor (36) connected at its source (drain) to said positive power supply terminal (1), a fourth N-channel N^+-gate MOS transistor (37) connected at its drain (source) to the drain (source) of said P-channel MOS transistor (36) and at its gate to the gate of said MOS transistor (36), a fifth N^+-gate MOS transistor (38) connected at its drain (source) to the drain (source) of said P-channel MOS transistor (36) and at its gate to the source (drain) of said fourth N^+-gate MOS transistor (37), and a sixth N-channel MOS transistor (39) connected at its drain (source) to the source (drain) of said fifth N^+-gate MOS transistor (38), at its source (drain) to said negative power supply terminal and at its gate to said bias voltage input terminal (35), said first N^+-gate MOS transistor (31) being connected at its drain (source) to the gate of said fourth _N ^T-gate MOS transistor (37).

11. A reference voltage generating device as claimed in Claim 9, wherein said first control circuit includes a P-channel MOS transistor (300) connected at its source (drain) to a positive power supply terminal (1), a first N-channel N^+-gate MOS transistor (310) connected at its drain (source) to the drain (source) of said P-channel MOS transistor (300) and at its gate to the gate of said MOS transistor (300), a second N^+-gate MOS transistor (320) connected at its drain (source) to the source (drain) of said first N^+-gate MOS transistor (310) and at its gate to the source (drain) of said first N^+-gate MOS transistor (310), and a third N-channel MOS transistor (330) connected at its drain (source) to the source (drain) of said second N^+-gate MOS transistor (320), at its source (drain) to a negative power supply terminal and at its gate to a . bias voltage input terminal (350); and said second control circuit includes a P-channel MOS transistor (360) connected at its source (drain) to said positive power supply terminal (1), a fourth N-channel N^+-gate MOS transistor (370) connected at its drain (source) to the drain (source) of said P-channel MOS transistor (360) and at its gate to the gate of said MOS transistor (360), a fifth _N ^+-gate MOS transistor (380) connected at its drain (source) to the drain (source) of said P-channel M^OS transistor (360) and at its gate to the source (drain) of said fourth N^+-gate MOS transistor (370), and a sixth N-channel MOS transistor (390) connected at its drain (source) to the source (drain) of said second N^+-gate MOS transistor (380), at its source (drain) to said negative power supply terminal and at its gate to said bias voltage input terminal (350), said first N^+-gate MOS transistor (310) being connected at its drain (source) to the gate of said fourth N -gate MOS transistor (370).

12. A reference voltage generating device as claimed in any one of claims 3 to 11, wherein said semiconductor of the first conductivity type is an N-type semiconductor, and said semiconductor of the second conductivity type is an intrinsic semiconductor.