EP0197965B1 - Fet-stromquelle - Google Patents

Fet-stromquelle Download PDF

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Publication number
EP0197965B1
EP0197965B1 EP85904764A EP85904764A EP0197965B1 EP 0197965 B1 EP0197965 B1 EP 0197965B1 EP 85904764 A EP85904764 A EP 85904764A EP 85904764 A EP85904764 A EP 85904764A EP 0197965 B1 EP0197965 B1 EP 0197965B1
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EP
European Patent Office
Prior art keywords
current
field effect
transistor
integrated circuit
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP85904764A
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English (en)
French (fr)
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EP0197965A1 (de
Inventor
Bernard Lee Morris
Jeffrey Jay Nagy
Lawrence Arthur Walter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
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Priority claimed from US06/656,343 external-priority patent/US4645948A/en
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0197965A1 publication Critical patent/EP0197965A1/de
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Publication of EP0197965B1 publication Critical patent/EP0197965B1/de
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • This invention relates to an integrated circuit comprising a current source adapted to provide a constant current.
  • circuits that provide a constant reference voltage, but relatively less on the apparently similar job of producing a constant reference current.
  • FET field effect transistor
  • steps are frequently taken to mitigate the effects of large lot-to-lot variations in device parameters, for which field effect transistors are notorious.
  • circuits are usually designed to minimize the effects of threshold and gain variations that occur for field effect transistors on different wafers.
  • a resistor is typically included in the source path of a FET to provide degenerative feedback, which reduces these variations.
  • U.S.A. patent no. 4009432 discloses a constant current supply which includes a field effect transistor having a gate-source resistor, and means for providing an output current.
  • a current mirror increases the gain of the circuit, thereby improving the power supply rejection.
  • the reference circuit When utilized with analog or digital field effect transistor circuitry implemented on the same semiconductor substrate, the reference circuit also compensates for processing variations.
  • the field effect transistor is an enhancement mode type.
  • the following description relates to a circuit which can provide a temperature and power supply independent current, and in a preferred embodiment actively compensates for inherent process variations. This results in a smaller spread of linear circuit parameters, such as operational amplifier slew rate, gain, and gain-bandwidth, than can be obtained with an "ideal" current source.
  • the present technique results in part from a recognition that positive and negative temperature coefficient terms can be balanced to a desired degree in a FET, to obtain a desired temperature coefficient.
  • the present invention also provides that the current source FET may be fabricated by the same fabrication process (e.g., on the same semiconductor substrate) as the circuits utilizing the controlled current. Then, process variations produce changes in the current source FET that offset changes in performance parameters (e.g., gain, slew rate, etc.) in the controlled circuit. By this technique, a FET is utilized to good advantage as a current source.
  • the basic core of the source is shown in FIG. 1, wherein a field effect transistor has a reference resistor (R) connected between the gate and the source.
  • the field effect transistor is typically an insulated gate type (i.e., an IGFET), which may be a metal-oxide-silicon field effect transistor (MOSFET) type.
  • IGFET insulated gate type
  • MOSFET metal-oxide-silicon field effect transistor
  • the current through the channel of the IGFET is: where ⁇ is the gain, VGS is the voltage of the gate with respect to the source and Vt is the threshold voltage, of the IGFET.
  • the value of Cox can be calculated as: The permittivity of free space times the dielectric constant of the gate insulator (about 3.85 for an oxide) divided by the thickness of the gate insulator. Equation (1) may be solved for VGS: For a constant channel current I, the temperature coefficient of VGS is the sum of two terms. The first involves ⁇ , whose temperature dependence arises from that of the mobility of the majority carriers flowing in the channel between the source and the drain.
  • Equation 4 The ability of this source to compensate for process variations is also shown in Equation 4.
  • a "fast” (e.g., relatively thin gate oxide and short channel length) process will have a large (3, and thus a small value of VGS.
  • the reference current (I R ) is equal to VGS/R, so it will decrease.
  • a “slow” (e.g., relatively thick gate oxide and long channel length) process with a small ⁇ wil have a larger VGS, and thus a larger reference current.
  • a fast process usually results from relatively more etching of the gate material, which reduces its length relatively more than its width. Hence, when the channel is formed, the ratio Z/L is increased. The opposite is true for a slow process.
  • Other factors may also be involved, such as semiconductor junction depths, gate insulator thicknesses, doping levels, etc.
  • FIG. 2 A simple circuit that uses the VGS/R concept to generate a constant current is shown in FIG. 2.
  • the channel current through the reference transistor (M3) should be held proportional to the reference current (IR).
  • transistor M1 mirrors the channel current in M5, which is connected as a diode.
  • M5 also causes the reference current I R to flow through R1.
  • I R is identical to the channel current flowing through M5. If a current I is flowing in M1 and M5, then current 21 is mirrored in M4, which is twice the size of M2.
  • the channel current in reference transistor M3 is equal to that in M4 minus that delivered by M5. The final result is that a current I flows through all the transistors except M4, which has a current of 21.
  • the bias-out positive (BOP) provides a voltage to the gate of one or more P-channel current output transistors M50; see FIG. 4.
  • the output current, l out is proportional to the reference current, I R .
  • the proportionality constant depends upon the size of M50 as compared to M5 of FIG. 2 (or as compared to M48 of FIG. 3.)
  • a corresponding bias-out negative (BON) can be supplied to one or more N-channel current output transistors M60; see FIG. 5.
  • FIG. 3 A more typical circuit employing the inventive concept is shown in FIG. 3.
  • the widths and lengths of the transistor channels, in micrometers, is given as W/L for each associated transistor.
  • M410 is sized to drw a small current, typically less than 0.1% of the current through reference resistor R1, which is set at a nominal value of 100pa.
  • M410 and its bias resistors can be replaced by a depletion transistor.
  • the other additional transistors are optionally included to improve power supply rejection by cascading all of the mirrors, and to mirror the current to M413, which actually drives the negative bias output (BON).
  • a positive bias output (BOP) is provided from the drain of M48.
  • the reference resistor R1 can be of any type that gives a positive temperature coefficient of resistance. It is advantageously made with a P+ diffusion, which has a much lower TCR (temperature coefficient of resistivity) and VCR (voltage coefficient of resistivity) than the P-tub. The absolute control of the P+ sheet resistance is also very good, typically within plus or minus 15% of the nominal value. R1 can alternately be made of polysilicon or other material. The sizes of R1 and reference transistor M45 are typically set to give a zero TCC (temperature coefficient of current) in M413 and M48 at nominal conditions. The resistance of the reference resistor (R1) is typically greater than 100 ohms, and typically less than 10 megaohms, although a wider range is possible.
  • the size of the reference transistor (M45) is desirably chosen so that the channel length (L) is large enough to minimize processing variations. A length of about 8 to 10 micrometers is suitable for typical processing conditions. Then, the gain may be set by choosing the width, Z, to give the desired temperature coefficient.
  • One methodology for obtaining the desired temperature coefficient of the current from the source is as follows:
  • the resistor R was assumed to be made with P+ diffusion, and to have a plus or minus 15% maximum variation with processing.
  • Varying the temperature from 0 to 100°C showed that the VBE/R source has by far the largest temperature variation.
  • the band-gap source (B) also has an appreciable TCC due to the finite TCR of the resistor.
  • the self-compensating feature of the VGS/R source was apparent. At 25°, the low speed process gives 35% higher current, and the high speed process 30% lower current than nominal. Both cases show a larger TCC than exists with the nominal process, but no worse than that of the band-gap source (B).
  • the effect of the different current sources on the performance of a typical operational amplifier (op-amp) has also been investigated.
  • the op-amp used in these simulations was a simple two stage design. There are two independent effects of temperature on op-amp performance. The first is the intrinsic effect of temperature on the op-amp, independent of current. The second is the effect of current variations due to the temperature dependence of the current source.
  • the ideal current source (A) is used in these simulations to separate these two effects.
  • the slew rate, gain-bandwidth product (GBW), and gain, as a function of temperature were investigated for nominal processing at a constant current of 100pa.
  • PSRR power supply rejection ratio
  • CMRR common mode rejection ratio
  • common mode range is somewhat worse. This is due to exactly the self-compensating feature that improves the other parameters.
  • the smallest common mode range exists when the transistors are slow and the current is high. In other current sources there is no connection between these two; even when the worst-case assumption of high current is made, it is not as high as it is in the self-compensating source. For the op-amp used here, this results in a worse-case loss of 500mv of input range. This op-amp was not designed to give a particularly large common mode range, and the loss would be proportionally less on op-amps with larger Z/L ratios on the input transistors.
  • FIGS. 8 and 9 Another way to define the resistor is shown in FIGS. 8 and 9.
  • the polysilicon (poly) level is used instead of the field oxide to define the feature size.
  • the poly line size is one of the most critical and well controlled parameters in the process, and in self-aligned silicon gate technology, the polysilicon layer defines the gate electrode size. Hence, thie poly line size will often determine whether any given wafer is "slow” or "fast”. For this reason, a resistor defined by the layer that defines the gate electrode can have a tighter design tolerance than one defined by the field oxide.
  • the actual poly line size differs from the nominal size by an amount DL.
  • a positive DL means wider poly and a slower process
  • negatiove DL means narrow poly and a fast process.
  • the resistor width is W- DL, so that:
  • a positive DL (slow process) causes the resistor to increase, and the negative DL (fast process) causes it to decrease from the design value. This will oppose the "self-compensation" feature of the VGS/R source, since process induced changes in VGS will now be tracked by a similar change in R.
  • the relative value of these two quantities depends on the resistor's nominal width. For an extremely wide resistor, R does not depend on DL at all. As the resistor width decreases, the effect of DL becomes larger. Note that other self-aligned gate electrode materials (e.g., a refractory metal or metal silicide) can be used to define the resistor, to achieve this effect.
  • the current I VGS/R for three different resistor widths is shown in FIG. 11. It was calculated using the 40/10 N-channel transistor M45 in FIG. 3 and nominal process conditions. The case of infinite resistor width corresponds to the case discussed above. At 7 microns the current is nearly independent of poy line size, and at 4 microns the process compensation is actually the reverse of that discussed above.
  • the circuit shown in FIG. 3 has been implemented in a typical 3.5 micron Twin-Tub CMOS process on a n-type substrate on a lot in which the poly width was intentionally varied.
  • the resistor R1 was poly defined, with a nominal width of 4 microns.
  • the current vs. temperature curves for three different wafers were determined.
  • the sheet resistance of the P+ diffusion, was measured at 10 percent below the nominal value for this lot. This accounts for most of the difference between the measured current of 107 jja and the design value of 100 pa for the nominal poly.
  • the current calculated from FIG. 11 was 87% of the nominal value, and the measured current was 84% of the nominal.
  • the calculated current was 105% nominal, and the measured current was 114% of the nominal.
  • the maximum variation of current over the temperature range 10°C-120°C was 2.1%. From 25°C-120°C it is 1.5%. Both the narrow and wide poly had similar temperature variations of their current.
  • the resulting controlled current can be readily maintained within ⁇ 5 percent, and typically within ⁇ 2 percent, of the average value, over a temperature range of from 0°C to 100°C, or even wider. These values are even more readily obtained over a typical commercial temperature range of from 0°C to 70°C.
  • the current source automatically compensates for variations in the transistor process, with a "fast” process giving lower current and a “slow” one giving a higher current. If desired, this compensation can be reduced or eliminated with respect to variations in the polysilicon line width size by proper resistor design.
  • depletion mode devices including junction field effect transistors, and Shottky gate field effect transistors (e.g., MESFETS) implemented in gallium arsenide or other III-V materials.
  • MESFETS Shottky gate field effect transistors
  • one advantage of the present technique is that it does allow the use of enhancement mode FET's; i.e., those having a threshold voltage, Vt, that is >0 for an n-channel device, and Vt ⁇ 0 for a p-channel device.
  • Vt threshold voltage
  • Vt ⁇ 0 threshold voltage
  • thee voltages are measured at the gate in reference to the source; i.e., VGS.
  • Enhancement mode field effect transistors are typically of the insulated gate (IGFET) type, of which MOSFET's are an example. Their use is advantageous because a smaller channel current can then typically be utilized in the reference transistor than if a depletion-mode device were used.
  • the reference current is directed through the reference resistor in the direction that causes the channel current in the reference transistor to flow (or to increase its flow), as the reference current increases. That is, VGS is generated in the direction of forward bias by the reference current.
  • enhancement mode field effect transistors are usually available on an integrated circuit using fewer process steps than depletion mode devices require.
  • the means for causing the channel current and the reference current to be proportional inherently produces the desired direction of reference current flow. This is in contrast with the prior art technique of biasing a current source FET using degenerative feedback by placing a resistor in the source path. In that case, an increase in the current through the resistor causes a change in VGS in the direction that tends to decrease the channel current of the FET.
  • the present invention may be used in analog integrated circuits, it may also be used in digital integrated circuits.
  • a current source for the sense amplifiers, for improved speed and sensitivity.
  • the use of a controlled current source is known for use with digital logic circuits to reduce chip-to-chip performance variations.
  • the current source associated with the logic gates has been controlled using a reference clock and comparator circuitry; see “Delay Regulation - A Circuit Solution to the Power/Performance Tradeoff", E. Berndlmaier et al, IBM Journal of Research and Development, Vol. 25, pp. 135-141 (1981). ).
  • the present invention can advantageously be implemented on the same chip or wafer as the logic gates to perform this function.
  • a single bias circuit e.g., FIG. 3 can provide control of a plurality of current output transistors (FIGS. 4, 5) located at various places on a chip or wafer.
  • the term "integrated circuit" as used herein includes both utilizations.
  • the controlled current from the present source can be used to produce a controlled voltage, as by passing it through a resistor having a given temperature coefficient, or through a resistor-diode combination; i.e., a band-gap reference, etc.
  • the characteristics of a band-gap reference are described in "New Developments in IC Voltage Regulators", R. J. Widlar, IEEE Journal of Solid State Circuits, Vol. SC-6, pp. 2-7 (1971).
  • the device receiving the controlled current may be formed on a different substrate from the current source.
  • K is the feedback constant determined by the relative sizes of M1, M2, M4, and M5.
  • K is the feedback constant determined by the relative sizes of M1, M2, M4, and M5.
  • the value of K shown in FIG. 2 is two, but it may be any value consistent with stability. Summing the currents at the drain of M4 gives: However: Substituting (1A) into (2A) and rearranging gives: which is quadratic in ORH. Solving gives: Squaring and rearranging gives:
  • Equation (5A) reduces to:
  • Equation (5A) reduces to: which has an inherent positive temperature coefficient. Even though 1/R1 2 has negative temperature behavior, it is outweighed by 1/(3 which goes as T 3 /2.
  • the value of the reference resistor R1, the size of transistor M3, and the value of the feedback constant K influence the channel current through the reference transistor, as indicated by (1A).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)

Claims (9)

1. Integrierte Schaltung mit einer Stromquelle, die einen Konstantstrom Oout) an wenigstens ein Bauteil liefert, wobei die Stromquelle einen Bezugsfeldeffekttransistor (M3) mit einer vorgegebenen Schwellenwertspannung und einer vorgegebenen Verstärkung besitzt und bei dem die Gate-Elektrode mit der Source-Elektrode über einen Bezugswiderstand (R1) verbunden ist, ferner eine Einrichtung (M1, M2, M3, M4, M5), die einen Bezugsstrom über den Bezugswiderstand im Verhältnis zu dem Strom, der über den Kanal des Bezugstransistors fließt, fließen läßt und eine Einrichtung (M50), die bewirkt, daß der Konstantstrom dem Bezugsstrom proportional ist, dadurch gekennzeichnet, daß die Größe des über den Bezugstransistor fließenden Kanalstroms (I) so gewählt ist, daß sich für den Konstantstrom ein Temperaturkoeffizient von etwa Null ergibt.
2. Integrierte Schaltung nach Anspruch 1, bei der der Bezugsfeldeffekttransistor ein Anreicherungstyp-Transistor ist.
3. Integrierte Schaltung nach Anspruch 1 oder 2, mit wenigstens einem Feldeffekttransistor eines ersten Kanal-Leitfähigkeitstyps und wenigstens einem Transistor eines Kanal-Leitfähigkeitstyps, der dem ersten Typ entgegengesetzt ist.
4. Integrierte Schaltung nach Anspruch 3, gebildet in einem Halbleitersubstrat, daß wenigstens eine erste Zone des ersten Leitfähigkeitstyps mit einer Vielzahl von darin erzeugten Feldeffektransistoren besitzt, und eine zweite Zone des entgegengesetzten Leitfähigkeitstyps, in welcher der Bezugsfeldeffektransistor gebildet ist, wobei die zweite Zone durch eine pn-Übergang von der ersten Zone isoliert ist.
5. Integrierte Schaltung nach Anspruch 4, bei der Source-Anschluß des Bezugsfeldeffekttransistors elektrisch mit der isolierten Zone verbunden ist.
6. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, bei der die rückseitige Gate-Elektrode des .Bezugsfeldeffekttransistors mit einer Bezugsspannung verbunden ist.
7. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, bei der der Bezugswiderstand durch Implantieren eines Dotierstoffs durch eine Öffnung in einer die Gate-Elektrode bildenden Schicht erzeugt ist, wobei die Größe des Bezugswiderstands sich entsprechend den Prozeßänderungen verändert, die auch die Größe der Gate-Elektrode beeinflußen.
8. Integrierte Schaltung nach Anspruch 7, bei der das Material Polysilizium umfaßt.
9. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, bei der die Einrichtung, die bewirkt, daß ein Bezugsstrom im Verhältnis zu dem Kanalstrom fließt, einen Stromspiegel umfaßt.
EP85904764A 1984-10-01 1985-09-18 Fet-stromquelle Expired - Lifetime EP0197965B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US06/656,343 US4645948A (en) 1984-10-01 1984-10-01 Field effect transistor current source
US68599084A 1984-12-24 1984-12-24
US685990 1984-12-24
US656343 1984-12-24

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EP0197965A1 EP0197965A1 (de) 1986-10-22
EP0197965B1 true EP0197965B1 (de) 1991-01-16

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EP85904764A Expired - Lifetime EP0197965B1 (de) 1984-10-01 1985-09-18 Fet-stromquelle

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EP (1) EP0197965B1 (de)
KR (1) KR880700349A (de)
CA (1) CA1252835A (de)
DE (1) DE3581399D1 (de)
ES (1) ES8700502A1 (de)
HK (1) HK44692A (de)
SG (1) SG84291G (de)
WO (1) WO1986002180A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1566717A1 (de) * 2004-02-20 2005-08-24 Atmel Nantes Sa Vorrichtung zur Erzeugung einer verbesserten Referenzspannung und entsprechende integrierte Schaltung
KR20190025044A (ko) * 2015-09-21 2019-03-08 심프토트 테크놀로지스 엘엘씨 회로 보호 및 자가촉매적 전압 변환을 위한 단일 트랜지스터 장치

Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
US4868416A (en) * 1987-12-15 1989-09-19 Gazelle Microcircuits, Inc. FET constant reference voltage generator
US5608314A (en) * 1994-04-11 1997-03-04 Advanced Micro Devices, Inc. Incremental output current generation circuit
US10205313B2 (en) 2015-07-24 2019-02-12 Symptote Technologies, LLC Two-transistor devices for protecting circuits from sustained overcurrent

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Publication number Priority date Publication date Assignee Title
US4009432A (en) * 1975-09-04 1977-02-22 Rca Corporation Constant current supply
US4051392A (en) * 1976-04-08 1977-09-27 Rca Corporation Circuit for starting current flow in current amplifier circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Handbook of Semiconductor Electronics, edited by Lloyd P Hunter and published by McGraw-Hill Book Company, 1970 pages 13-10 and 13-11 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1566717A1 (de) * 2004-02-20 2005-08-24 Atmel Nantes Sa Vorrichtung zur Erzeugung einer verbesserten Referenzspannung und entsprechende integrierte Schaltung
FR2866724A1 (fr) * 2004-02-20 2005-08-26 Atmel Nantes Sa Dispositif de generation d'une tension electrique de reference de precision amelioree et circuit integre electronique correspondant
KR20190025044A (ko) * 2015-09-21 2019-03-08 심프토트 테크놀로지스 엘엘씨 회로 보호 및 자가촉매적 전압 변환을 위한 단일 트랜지스터 장치
US11355916B2 (en) 2015-09-21 2022-06-07 Symptote Technologies Llc One-transistor devices for protecting circuits and autocatalytic voltage conversion therefor
US11611206B2 (en) 2015-09-21 2023-03-21 Symptote Technologies Llc One-transistor devices for protecting circuits and autocatalytic voltage conversion therefor
US11962141B2 (en) 2015-09-21 2024-04-16 Symptote Technologies Llc One-transistor devices for protecting circuits and autocatalytic voltage conversion therefor

Also Published As

Publication number Publication date
HK44692A (en) 1992-06-26
DE3581399D1 (de) 1991-02-21
CA1252835A (en) 1989-04-18
WO1986002180A1 (en) 1986-04-10
KR880700349A (ko) 1988-02-22
ES8700502A1 (es) 1986-10-16
EP0197965A1 (de) 1986-10-22
ES547346A0 (es) 1986-10-16
SG84291G (en) 1991-11-22

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