Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
  • G11C16/12—Programming voltage switching circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
  • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
  • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
  • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
  • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable

Definitions

• This invention relates to programmable memory cells of the kind including memory means, having a first virtual node, a second virtual node and a gate elec ⁇ trode, for electrically coupling said first and second virtual nodes in response to the relative magnitude between a programmable threshold voltage level and a voltage on said gate electrode; first gate means, having an address electrode, a first virtual node, electrically coupled to said first virtual node of said memory means, and a gate electrode, for electrically coupling said address electrode with said first virtual node in response to the relative magnitudes of the voltages at said address electrode and said gate electrode; second gate means, having a first electrical node, a first virtual node, electrically coupled to said second vir ⁇ tual node of said memory means, and a gate electrode, for electrically coupling said first electrical node with said first virtual node in response to a voltage on said gate electrode, voltage generating means for generating voltages, coupled to said nodes and elec ⁇ trodes of said memory means, said first gate means and said second gate
• the invention also relates to programmable matrix and logic arrays of cells.
• a programmable memory cell of the kind speci ⁇ fied is known from an article by H. A. R. egener: "The Gated-Access MNOS Memory Transistor", IEEE Trans ⁇ actions on Electron Devices, Vol. ED-27 No.l, January 1980, pages 266-276.
• a programmable memory cell of the kind specified characterized in that said voltage gener ⁇ ating means is effective to provide: a first voltage sequence, suitable to program said cell to a first binary state, comprising, a coupling of voltages to said gate electrode of said first gate means and to said gate electrode of said memory means in substantial time synchronism with substantially zero voltages on said address electrode of said first gate means and on said gate electrode of said second gate means; a second voltage sequence, suitable to program said cell to an alternate, second binary state, comprising, a coupling of voltages to said gate electrode of said memory means and to said address and gate electrodes of said first gate means, suitable to electrically decouple said address electrode from said virtual node in said first gate means, in substantial time synchronism with a substantially zero voltage on said gate electrode of said second gate means; and a third voltage sequence, suitable to read the binary state programmed into said cell, comprising, a coupling of voltages to said gate electrode of said first gate means and to said gate electrode
• an M row by N column programmable array characterized by: a multiplicity of memory cells, each having a first address line, a second address line, a memory line, a read line and third line; M row address lines, each commonly connecting said first address lines of said cells in respective columns; N column address lines, each commonly connecting said second address lines of said cells by successive pairs in respective columns; a read line, commonly connecting said cell read read lines; and a memory line, commonly connecting said cell memory lines.
• a programmable logic array characterized by: a multiplicity of memory cells, each having a first address line, a second address line, a memory line, a read line and a third line; a memory line, commonly connecting said cell memory lines; a first group of cells, having commonly connected first address lines by rows and second address lines by columns to form a logic AND array; a second group of cells, having commonly connected first address lines by rows and second address lines by columns to form a logic OR array; means for coupling said columns of said first group with said rows of said second group; and means for selectively addressing individual memory cells through first and second address lines with programming signals in time correspondence with signals on said memory line.
• the present invention is directed to a unique electrically programmable memory cell, its configurations in matrix arrays, and its organization in programmable logic arrays (PLAs).
• PLAs programmable logic arrays
• the essential features of the individual cells, as well as groups thereof, are inherently linked to their internal structure of three series connected gates, and an independent memory line for conveying high voltage programming signals into the memory elements within the cells.
• the use of a distinct and dedicated line to program the memory element over ⁇ comes the multitude of functional and structural limita ⁇ tions normally constraining semiconductor chip designs when memory programming voltages are to be routed through address, data or control lines.
• the cell communicates through the combination of bit and word address lines, a read line and a memory line.
• the latter is used to erase and write (program) each cell, and is therefore normally subjected to voltages far exceeding those appearing on the, other lines.
• the invention contem- plates three cell gates formed by the series connection of a field effect transistor (FET), an alterable thres ⁇ hold transistor and another FET, and defining a channel of variable conductivity between a bit address line at one end and a grounded line at the other. A conductive path therebetween defines one cell state, while a non- conductive path provides the other.
• FET field effect transistor
• the word line, connected to one FET gate electrode, and the read line, connected to another FET gate electrode, are energized as the memory line, connected to the alterable threshold transistor gate electrode, is biased to its read condition. Sensing the presence or absence of a conductive path between the bit line and the grounded line during the read mode in ⁇ dicates the cell's state. With the Series connected word and read FETs energized to conduct, the relationship between the memory bias level and the alterable transis ⁇ tor threshold prescribes the conductivity of that gate and the complete cell. If, as taught herein, the memory element threshold level is altered above or below the memory line bias level during programming, the overall state written in the cell is also changed.
• An erase pulse on the memory line prepares the cell for the succeeding write sequence.
• the cell is then programmed by opening the path through the read FET and appropriately energizing the memory element with a voltage on the memory line. If the memory line voltage pulse is sufficiently long in overall duration, yet comprised of multiple relatively short pulses, the memory element will be written to a new state when the combination of bit line and word line voltages causes the word FET to conduct.
• the programmable memory cell described above is readily amenable to a unitary structural organization, -5-
• a single substrate has a conductively doped bit line region, a conductively doped region at ground po ⁇ tential and a channel therebetween covered by two con ⁇ ventional field effect gate electrodes on either side of an alterable threshold transistor electrode.
• This configuration of the cell is particularly suited for processes in which the electrodes are formed by layered depositions of heavily doped, and therefore conductive, polycrystalline silicon.
• the diversity of lines by which each cell is coupled permits fabrication in matrix arrays while retaining the independence of the high voltage memory line. In such arrays all memory lines can be commonly joined. Depending on the array configuration one or two read lines suffices. Connection of bit lines and word lines into row and column addresses is readily accom ⁇ plished in numerous ways, substantially dictated by the design objectives of the overall array.
• a further refinement of the cells into groups is generally known as the programmable logic array
• PLA memory line
• Data to be processed enters the PLA through the logic AND segment of the array and departs from the logic OR segment. Consistent with the basic operating principles of the cell, data is processed in concurrence with a read signal on the read line and an appropriate bias level on the memory line.
• the logic AND and OR segments of the array are decoupled. The cell states are entered into the AND segment through the array input lines, while the OR segment is written through a coupling with array output lines.
• rows or columns of the array segments are scanned sequentially with synchronization of the word line, bit line and memory line pulses.
• Fig. 1 is a schematic depicting the functional organization of the cell.
• Fig. 2 contains plots of voltage vs. time during the operation of the cell in Fig. 1.
• Fig. 3 schematically depicts various conditions within the gate region of an MNOS transistor type memory element.
• Fig. 4 is a schematic of the capacitance distribution associated with the regions in Fig. 3.
• Fig. 5 contains a schematic cross-section of a unitary cell with operational illustrations.
• Fig. 6 schematically shows one organization of cells in a matrix array.
• Fig. 7 schematically shows a second organization of cells in a matrix array.
• Fig. 8 contains a schematic of a PLA utilizing the present cells.
• Fig. 9 is a schematic of a shift register circuit suitable for defining a programming sequence for the PLA.
• Fig. 10 contains a schematic cross-section of the unitary cell with structural illustrations.
• ROMs Read only memories
• EAROM or EEPROM
• This invention relates to such devices, with special recognition of the trend toward single chip arrays of large overall area and small cell size, processed directly on silicon wafer substrates.
• the present invention addresses itself to a problem of particular concern to designers of EAROMs generally, and particularly those designers of such memory arrays who utilize alterable threshold transistors to form the nonvolatile memory elements within the cells.
• writing and erasing requires the use of relatively high voltages, heretofore routed directly on address or control lines of the chip. For instance, writing or erasing typically demands plus or minus twenty volts at the gate electrode of the MNOS transistor, compared to the five volt levels normally utilized for control and logic functions.
• the invention overcomes these conflicting objectives while retaining the intrinsic attributes of EAROM.
• a three gate memory cell comprised of series connected field effect type transis ⁇ tors. Addressing is by bit and word lines, erasing and writing is performed by way of a commonly connected memory line, and reading is performed by the concurrence of a low voltage memory line bias and a read line command signal. In this way, the address and control circuits experience only the low voltage, logic level signals.
• alterable threshold transistors include the broad class of nonvolatile devices in which the MNOS transistor is merely one constituent.
• MNOS as utilized herein is generic, encompassing the group of alterable thres ⁇ hold transistors in which threshold levels are changed by the conduction of charge from the transistor channel through a thin oxide layer into a region between the channel and gate.
• Variants within the generic group include devices having nonmetallic (heavily doped
• Fig. 1 showing discrete transistors joined by terminal electrodes
• the basic con ⁇ cepts are preferably implemented in an integrated con ⁇ figuration containing multiple gate electrodes located over a single conductive channel.
• virtual nodes N, and ⁇ are shown connecting memory transistor Q 2 with access transistors Q-, and Q 3 on opposite sides thereof.
• the embodiment of the basic cell comprises a series connection of three transistors, Q.-Q-. At the left extreme of the cell is node V (,the subscript representing bit line). The right side of the cell terminates at node V .
• Virtual nodes N, and 2 join the three transistors. As their names imply, virtual nodes N. and N 2 do not normally exist as points of electrical contact.
• transistors Q, and Q- are enhancement mode, n-channel devices, and conduct when the voltages at their respective gate electrodes, Vw
• Transistor Q 2 embodies an MNOS device having an electrically alterable threshold voltage with extremes of approximate ⁇ ly -3 and +3 volts. Actuation of the MNOS transistor, as well as its programming, is performed through the gate electrode designated V (the subscript representing memory line). Clearly, to form a conductive path between nodes V_ and V g , all three transistors must be on. For purposes of the embodiment, the logic voltages at and
• V R_. are either +5 volts or 0 volts, while electrode VM M is subject to a "bias level of 0 volts, a relatively long pulse at -20 volts or a sequence of short pulses at +20 volts, during the course of reading, erasing and writing the memory cell, respectively.
• the voltages and their transitions will be considered with greater particularity in the ensuing paragraph covering the cell operation.
• a conductive path between bit node V and node V g is a logic "0" state of the cell, while a nonconductive path therebetween prescribes the logic "1" state.
• Fig. 2 of the drawings the con- ductive states of the individual transistors are shown at the right of each plot.
• the threshold voltages, designated V for each of the cell transistors are also depicted in the figure.
• V of MNOS transistor Q 2 is to shift the threshold from any prior level to -3 volts.
• the shift in threshold level shown by dashed lines, places the cell in a logic "0" state at the termination of the ERASE mode.
• t Q to t- the voltages on nodes and Vg, as well as electrodes " w and V R , are not constrained.
• the next time interval of interest between time t 2 and t 3 , is shown to be approxima-tely 10 milli- seconds in duration.
• the cell is in a WRITE mode with a logic state of "1" being programmed.
• MNOS transistor Q 2 receives a high duty cycle sequence of ten +20 volt, one millisecond pulses on gate electrode V M in time coincidence with a +5 volt signal on word electrode
• OMPI dence with a 0 voltage level conveyed through transistor Q- ⁇ alters the threshold voltage of Q 2 from -3 volts to its opposite extreme of +3 volts.
• the cell is now programmed to a logic state of "1". Given the foregoing sequence of events, the ensuing READ mode interval, between time t. and t g , should elicit a logic "1" state from the cell. As shown in Fig. 2, reading the cell is performed with a +5 volt command signal on read electrode of transistor Q 3 .
• the cell is addressed by the combination of a +5 volt signal on word electrode V and a high impedance, +5 volt address voltage on bit node V_.
• memory electrode V of transistor Q 2 is subjected to the selected bias level of 0 volts. As may be gleaned from the time plots, under these conditions only Q, and Q 3 are conducting, the voltage on electrode V of memory transistor Q 2 being below the threshold necessary to cause conduction therethrough. Without a conductive path through the complete cell, the address signal on bit node V_ is not grounded to node V ⁇ . Consequently, the absence of a conductive path, represented by +5 volts at node V , corresponds to a logic "1" state in the cell.
• tran- sistor Q With both the gate and source electrodes of Q, at +5 volts, tran- sistor Q, remains nonconducting.
• the effective floating of MNOS transistor Q 2 by the absence of conductive paths through either transistors Q, or Q 3 , inhibits the alteration of the threshold voltage in transistor Q 2 .
• the mechanism by which this occurs, and the constraints on pulse duration, will be considered in detail at a point hereinafter.
• the succeeding READ mode sequence yields a logic "0" state from the cell.
• the 0 volt bias level on electrode V during the READ mode is above the -3 volt threshold programmed within MNOS transistor Q 2 .
• MNOS transis ⁇ tor Q 2 , transistor Q-, and transistor Q 3 all conducting during the READ mode, the +5 volt, high impedance voltage on bit node V is grounded through node V g .
• the presence of zero volts at node V during the READ mode corresponds to a logic "0" state in the cell.
• a logic "1" state is programmed into the memory cell when the cell undergoes an ERASE mode followed by a WRITE mode in which V , V M and V View are respectively, +5 volts, +20 volts and 0 volts.
• V , V M and V View are respectively, +5 volts, +20 volts and 0 volts.
• V ⁇ is provided with +5 volts.
• Fig. 3 schematically shows the gate electrode region of• MNOS transistor Q_
• Fig. 4 depicts the corresponding distribution of capacitance among the various layers shown in Fig. 3.
• Fig. 5 expands the region of analysis to include the effects of transistors
• the deep depletion state as well as the related voltage distributions, are transitory conditions.
• ther ⁇ mally generated electron-hole pairs within the region begin to reduce its depth.
• the positively charged holes cancel the more distant negative charges while the negative constituents of the pairs are drawn into close proximity with the junction between the substrate and the silicon dioxide.
• the depletion region shrinks in thickness and increases in capacitance.
• the distribution of the voltage between electrode V render and the substrate is altered so that a greater portion of the voltage appears across capacitors C, and C 2 , the capacitors representing the silicon nitride and silicon dioxide layers.
• the voltage across the silicon nitride and silicon dioxide layers increases until the magnitude is adequate to permanently alter the MNOS transistor threshold.
• the latter condition is represented by the illustration on the right side of the substrate in Fig. 3.
• the time intervals are prescribed with a recognition that thermally generated electron-hole pairs will eventually collapse the deep depletion region, and thereby redistribute the voltage between electrode V and the substrate ground sufficiently to write the MNOS transistor to a logic "1" state.
• the 10 milli- second overall WRITE mode duration provides sufficient time to insure that the MNOS transistor is completely and reliably programmed to its logic "1" state when appro ⁇ priately commanded.
• the 1 millisecond duration of the constituent pulses is dictated by the requirement that programming to a logic "1" state not occur without the effects of external control. Namely, the period of each pulse, 1 millisecond, should be suf- * ficiently brief to prevent significant alteration in the capacitance distribution.
• the brief zero level of the memory line signal between successive 1 millisecond pulses need only be adequate to collapse the depletion region between repetitive pulses, a period typically extending no greater than 5 or 10 nanoseconds.
• n-channel cell is configured using a p-type substrate, 1, with n+ doped regions 2 and 3 therein.
• the field effect transistors (FETs) in the cell, Q, and Q 3 are characterized by gate electrodes 4 and 6, corresponding to previously noted electrodes
• the MNOS transistor, Q 2 forms the middle region of the unitary cell.
• the MNOS transistor is shown to include gate electrode 7, corres ⁇ ponding to electrode V , silicon nitride layer 8 and a thin silicon dioxide layer, 9A.
• Substrate 1 is shown connected to a ground potential.
• Diffusion region 2 is connected to node V through metallic contact layer 10 while n doped region 3 is electrically common with node V . Regions and electrodes 3, 4, 6 and 7 are readily accessible for further interconnection by fol- lowing fabrication techniques well-known to those prac ⁇ ticing in the art.
• W XfIlFPOO alter the threshold of the MNOS transistor.
• the voltage distribution shifting effects of thermally generated electron-hole pairs are avoided by the limited pulse duration of 1 millisecond. Since transistors Q, and Qm are nonconducting, no other sources of charge are available to rapidly thin the depletion region and thereby redistribute the write pulse voltage.
• the three gate cell is shown to be capable of individual programming by using low voltage word and bit address signals in synchronism with high voltage memory electrode pulses. Furthermore, as described at the onset, the high voltage pulses themselves do not appear on the conductive paths coup ⁇ ling the cell logic states, but rather, are relegated to a dedicated and distinct electrical conductor.
• the three gate, three transistor cells are in a configuration having a common connection of memory lines V , a common connection of read lines V R by alter ⁇ nate columns and a common connection of word lines V w in respective rows.
• Bit lines V ⁇ and lines V are common between successive cells in respective rows and further common in respective columns.
• the organization of cells and lines as shown in ⁇ Fig. 6 is particularly conducive to MOS integrated circuit fabrication processes in which the word lines consist of metallic interconnects joining doped poly- crystalline silicon gate electrodes, the read and memory lines are formed from heavily doped polycrystalline silicon, and the bit lines are heavily doped regions formed in the substrate itself.
• FIG. 7 An3other organization of the three gate cells into a memory array is schematically depicted in Fig. 7 of the drawings.
• the cells are generally organized in symmetric pairs on common structural col ⁇ umns. Each pair shares a common line V and common bit line V ⁇ , with line V g further being shared co monl ⁇ by
• This array is also characterized by word lines, designated V ' and V ', which are not shared by the cell pai 1rs noted above, but rather, are common in respective rows of the array structure. Note again, that programming of each cell during the WRITE mode remains individually con ⁇ trolled by the binary states on word lines, V ' and Vêt ', and bit lines, V ra ' and V render ' . 1
• the organization of the memory array as de ⁇ picted in Fig. 7 is also conducive to an integrated circuit layout.
• the lines V ' are formed by doped conductive regions in the substrate, bit lines V ' are composed of metallic conductors, while the read, word and memory lines are formed from conductively doped polycrystalline silicon.
• the group of cells in Fig. 7 can also be expanded to an M row by N column array.
• M row address lines are necessary to access the M rows of structural cell in the array. Further investigation reveals that N column address lines are also required.
• READ lines V are energized with +5 volts, commonly or by selective grouping of alternate columns, memory lines V set at a 0 bias voltage, the bit line signals applied to lines V , and the bit line voltage sensed for the presence of a ground potential created when a conductive path is formed through the cell to line V g .
• one or the other of the two read lines in the array of Fig. 6 must be selec ⁇ ted for energizing with +5 volts, while the other remains at 0 volts, in conformance with the column being read.
• V R'' serves the whole array.
• line V is preferably grounded, and bit line V supplied with voltage from a high impedance source, to read the cell state, it is the conductive path through the cell that comprises the essential operating feature of the cell.
• line V g is equally suited to be an output line, given the proper selection of impedances and voltage sensing locations.
• it is equally feasi ⁇ ble to provide +5 volts to line V g and sense the current flow to an electrical ground at line V
• FIG. 8 A more elaborate implementation of the three gate, three transistor memory cell appears in Fig. 8 of the drawings.
• the structural organization depicted there is generally known as a two input, two output PLA, here including the further refinement of nonvolatile state storage.
• a shift register circuit, used to gener ⁇ ate a sequence of pulses used during the WRITE mode in the PLA, is shown in Fig. 9 of the drawings.
• the "AND" segment of the array is first to receive the input data. Consequently, the "AND" array output serves as the "OR” array input. Further- more, output signals at D. and D 2 appear only when the states of input signals conform to the logic program in the PLA. To satisfy the diversity of logic programs normally sought, the AND segment of the array receives both the input signal and its inverse.
• the PLA depicted in Fig. 8 is designed to generate output signals at D. and D 2 only when all cells in the program path are nonconducting.
• the program to be stored in the AND segment of the array is entered using lines A_. and A 2 , in a manner to .be described with particularity hereinafter. Writing of the OR array utilizes lines P- ⁇ and P 2 .
• the embodying array is composed of n-channel cell ele ⁇ ments with the logic "1" state represented by +5 volts and the logic "0" state appearing as 0 volts.
• line V is at ground potential throughout the array, indicating that a con ⁇ ducting state in a cell during the READ mode will draw line V of the corresponding cell to ground potential.
• the memory transistor line designated V performs an ERASE function when energized with -20 volts, and a
• bit lines V _3 are in column lines at reference numerals 19 and 21.
• bit lines are also in columns (by defini ⁇ tion), and are continuums of programming input lines P-, and 2 .
• the data states entered using lines A, and A 2# as well as their inverses, serve as the word lines of the AND array, while the word lines in the OR array are continuations of AND array bit lines 19 and 21.
• the AND array bit lines and OR array word lines are joined through decoupling transistors 22 and 23.
• Read line V R is provided with a +5 volt command signal only when the PLA enters the READ mode. Consequently, during periods other than READ, the AND and OR arrays are essentially decoupled by transis- tors 22 and 23.
• a +5 volt signal is entered and sequentially clocked through the shift register circuit in Fig. 9 to produce pulses on lines S, and S 2 .
• the pulses on lines .S, and S 2 sequentially connect AND array lines 19 and 21 to ground potential.
• transistors 24 and 26 are nonconducting and the +5 volts is supplied through resistors 27 and 28 to lines 19 and 21 of the AND array. Recalling that lines 19 and 21 correspond to cell bit lines, it becomes apparent that the AND array cells are amenable to programming by synchronizing the signals on lines A, and A 2 , the shift register pulses on lines S, and S 2 , and the WRITE mode pulse on line V .
• V j T is at +5 volts when is at 0 volts.
• transistors 29 and 31 are in a conducting state.
• the voltages on word lines 32 and 33 are defined by the conductivity states of transistors 34 and 36. If both transistors are off, the respective lines are at +5 volts through resistors 37 and 38. When either transistor is conducting, the respective line is brought to ground potential.
• Reading of data through the PLA is accomplished by energizing the READ mode line, V , with +5 volts, placing memory line V at 0 volts and entering binary data through the A input lines.
• the three transistor cell in the PLA configuration embodiment shown is operated so that the following sequences and conditions are pre ⁇ scribed.
• V is pulsed at -20 volts for 100 milliseconds.
• V is pulsed with a sequence of +20 volt signals for a period of 10 milliseconds.
• V is 0 volts.
• S is +5 volts.
• S 2 is 0 volts.
• —A, and 2 define the AND array program.
• P, and P 2 define the OR array program.
• —D, and D 2 are open.
• V is pulsed with a sequence of +20 volt signals for a period of 10 milliseconds.
• V is 0 volts.
• S is 0 volts.
• S 2 is +5 volts.
• A, and A 2 define the AND array program.
• P, and P 2 define the OR array program.
• D, and D 2 are open.
• V M M is 0 volts.
• V is +5 volts.
• S. is 0 volts .
• a 2 are addressed by inputs of 0 or +5 volts .
• D-, and D 2 are logic array outputs .
• the poly 1 layer includes gate
• OMPI electrodes 4 and 6 of the transistors while the poly 2 layer comprises the doped polycrystalline silicon layer, 7, situated directly over and coextensive with silicon nitride layer 8. : ⁇ '
• the unitary cell is conceived to have an overall width of approximately 24 micrometers.
• Poly 1 gates 4 and 6, as well as the poly 2 gate region proxi ⁇ mate substrate 1, are approximately 4 micrometers in width.
• the lateral overlap between the poly 1 and poly layers is approximately 1.5 micrometers, a value primarily influenced by the 1 micrometer fabrication tolerance of available processing equipment.
• the cell is fabricated so that poly 1 and poly 2 are approximately 3,000 to 5,000 Angstroms in thickness, while silicon nitride layer 8 has a thickness of approximately 400 Angstroms.
• the silicon dioxide separating silicon nitride layer 8 from poly 1 layers 4 and 6 is approxi ⁇ mately 900 Angstroms in thickness.
• the thick- ness of the silicon dioxide separating the poly 1 layers from substrate 1 is approximately 700 Angstroms, while the corresponding separation between MNOS transistor silicon nitride layer 8 and substrate 1, layer 9A, is approximately 15-30 Angstroms.
• the p-type substrate preferably has a ⁇ 100> crystal orientation and a resistivity of 15 to 20 ohm-centimeters.
• the memory element in the cell includes other structural configurations characterized by their being responsive to an electric field between a gate electrode and a conductive channel so as to alter the threshold of the memory element.

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• 1980
  • 1980-12-29 US US06/220,644 patent/US4380804A/en not_active Expired - Lifetime
• 1981
  • 1981-12-04 CA CA000391484A patent/CA1179428A/fr not_active Expired
  • 1981-12-28 EP EP82900526A patent/EP0067872B1/fr not_active Expired
  • 1981-12-28 WO PCT/US1981/001762 patent/WO1982002275A1/fr active IP Right Grant
  • 1981-12-28 DE DE198282900526T patent/DE67872T1/de active Pending
  • 1981-12-28 JP JP82500541A patent/JPS57502024A/ja active Pending
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  • 1981-12-28 AU AU80839/82A patent/AU543975B2/en not_active Ceased
  • 1981-12-29 ZA ZA818973A patent/ZA818973B/xx unknown
• 1982
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