EP0064496A1 - Bande de vieillissement accelere a double couche conductrice a bandes multiples - Google Patents

Bande de vieillissement accelere a double couche conductrice a bandes multiples

Info

Publication number
EP0064496A1
EP0064496A1 EP19810901371 EP81901371A EP0064496A1 EP 0064496 A1 EP0064496 A1 EP 0064496A1 EP 19810901371 EP19810901371 EP 19810901371 EP 81901371 A EP81901371 A EP 81901371A EP 0064496 A1 EP0064496 A1 EP 0064496A1
Authority
EP
European Patent Office
Prior art keywords
strip
tape
conductors
bonded
semiconductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19810901371
Other languages
German (de)
English (en)
Inventor
Wayne A. Mulholland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of EP0064496A1 publication Critical patent/EP0064496A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Une bande connectrice (10) pour porter des signaux pour tester et donc effectuer un vieillissement accelere d'une pluralite de pastilles semiconductrices comprend une bande de support non conductrice (104) avec des conducteurs de puissance de non croisement (106, 108) et des conducteurs de signaux (110-140) lies a cette bande non conductrice de support. Une pluralite d'ensembles de points de contact (110a-140a) sont egalement lies a la bande de support (104) pour s'engager avec des points de test sur une bande (12) du dispositif sur laquelle les pastilles sont connectees. Des trous d'entrainement par encliquetage (142) sont prevus pour l'avance et l'alignement.
EP19810901371 1980-11-07 1980-11-07 Bande de vieillissement accelere a double couche conductrice a bandes multiples Withdrawn EP0064496A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1980/001496 WO1982001803A1 (fr) 1980-11-07 1980-11-07 Bande de vieillissement accelere a double couche conductrice a bandes multiples

Publications (1)

Publication Number Publication Date
EP0064496A1 true EP0064496A1 (fr) 1982-11-17

Family

ID=22154640

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19810901371 Withdrawn EP0064496A1 (fr) 1980-11-07 1980-11-07 Bande de vieillissement accelere a double couche conductrice a bandes multiples

Country Status (2)

Country Link
EP (1) EP0064496A1 (fr)
WO (1) WO1982001803A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4507544A (en) * 1982-09-29 1985-03-26 Reliability, Inc. Burn-in clock monitor
US4580193A (en) * 1985-01-14 1986-04-01 International Business Machines Corporation Chip to board bus connection
GB2210515A (en) * 1987-09-25 1989-06-07 Marconi Electronic Devices Fixture for an integrated circuit chip
US5164888A (en) * 1988-12-29 1992-11-17 International Business Machines Method and structure for implementing dynamic chip burn-in

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440027A (en) * 1966-06-22 1969-04-22 Frances Hugle Automated packaging of semiconductors
US3859718A (en) * 1973-01-02 1975-01-14 Texas Instruments Inc Method and apparatus for the assembly of semiconductor devices
US3818279A (en) * 1973-02-08 1974-06-18 Chromerics Inc Electrical interconnection and contacting system
US3939381A (en) * 1974-03-22 1976-02-17 Mcm Industries, Inc. Universal burn-in fixture
US4177519A (en) * 1975-07-28 1979-12-04 Sharp Kabushiki Kaisha Electronic control assembly mounted on a flexible carrier and manufacture thereof
US4089733A (en) * 1975-09-12 1978-05-16 Amp Incorporated Method of forming complex shaped metal-plastic composite lead frames for IC packaging
US4132856A (en) * 1977-11-28 1979-01-02 Burroughs Corporation Process of forming a plastic encapsulated molded film carrier CML package and the package formed thereby
US4147889A (en) * 1978-02-28 1979-04-03 Amp Incorporated Chip carrier
CA1138122A (fr) * 1978-10-13 1982-12-21 Yoshifumi Okada Carte de cablage imprime souple
US4195193A (en) * 1979-02-23 1980-03-25 Amp Incorporated Lead frame and chip carrier housing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8201803A1 *

Also Published As

Publication number Publication date
WO1982001803A1 (fr) 1982-05-27

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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AK Designated contracting states

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Designated state(s): AT CH DE FR LU NL SE

STAA Information on the status of an ep patent application or granted ep patent

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18D Application deemed to be withdrawn

Effective date: 19830103

RIN1 Information on inventor provided before grant (corrected)

Inventor name: MULHOLLAND, WAYNE A.