EP0364536A1 - Pastilles d'essai de vieillissement pour structures d'interconnexion a bonderisation automatique a film - Google Patents

Pastilles d'essai de vieillissement pour structures d'interconnexion a bonderisation automatique a film

Info

Publication number
EP0364536A1
EP0364536A1 EP89903601A EP89903601A EP0364536A1 EP 0364536 A1 EP0364536 A1 EP 0364536A1 EP 89903601 A EP89903601 A EP 89903601A EP 89903601 A EP89903601 A EP 89903601A EP 0364536 A1 EP0364536 A1 EP 0364536A1
Authority
EP
European Patent Office
Prior art keywords
burn
pads
conductors
tape
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89903601A
Other languages
German (de)
English (en)
Inventor
Richard A. Chase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of EP0364536A1 publication Critical patent/EP0364536A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates, in general, to tape automated bonding (TAB) tape interconnect structures, and more particularly to a TAB interconnect construction which facilitates burn-in and permits the use of a simplified burn-in socket.
  • TAB tape automated bonding
  • Tape automated bonding is a well known technique for fabricating packaged integrated circuit semiconductor devices.
  • Semiconductor integrated circuits chips, or dies conventionally have multiple electrical contact points which are connected through external electrical leads or thin film conductors to plug-in contacts, to printed circuit boards, or the like.
  • a strip of metallized tape in reel form carries a plurality of groups of metallic fingers or lines which form interconnect lines, or conductors.
  • the conductors are arranged in arrays to be connected at inner ends to contact points on the integrated circuits, as by compression bonding, for example, with the outer ends of the conductors then forming external contacts of an integrated circuit package.
  • Patents directed to this technique illustrate conductor arrays formed from a very thin flexible metallized tape having a typical thickness of 2.3 to 2.9 mils. The conductor array ..
  • the integrated circuit packages produced in the foregoing manner may then be used in a variety of circuit configurations, often becoming a part of highly expensive and complex circuits where high reliability is essential.
  • the probability of having all of the semiconductor devices in such a complex circuit functioning within specifications is quite low, and accordingly it is extremely important that each semiconductor device be tested before such assembly.
  • burn-in test In which bias supply voltages are applied to the device for a predetermined duration of time. Power is applied to the various bias voltage leads of the semiconductor chip, with power being applied for sufficient period of time to raise the temperature of the semiconductor device to a relatively high temperature, at least equal to that which it would be expected to encounter in use. This heating of the device with the applied bias voltages is intended to produce failures in any weak semiconductor devices, so that these can be weeded out and discarded, leaving only the satisfactory devices for assembly in circuits, or for delivery to customers.
  • the present invention is directed to a TAB interconnect tape carrying arrays of photo-etched printed circuit interconnect
  • test pads formed in the metallization of the printed circuit.
  • these test pads are formed on the same side of the TAB tape as the remaining interconnect conductors, while in a second form of
  • the test pads are formed in metallization on the opposite side of the TAB tape, from the conductor array.
  • the metallized power and ground test pads are connected to corresponding power and ground conductors on the first side of the TAB tape through vias in the insulating support tape that separates the metal layers.
  • the large test pads permit the use of a very simple and relatively inexpensive socket for connecting suitable power sources and ground contacts through the interconnect conductors to the semiconductor device for burn-in.
  • a semiconductor chip may have more than 300 signal and power lines, but typically only about 40 leads need to be contacted for burn-in purposes. This reduced lead count, together with the large pad contact points, permits the use of a test socket that would cost approximately $50 to fabricate, whereas test sockets for contacting all 300 or more leads could cost $10,000 or more, if they could be obtained at all.
  • the present invention is directed to a TAB tape segment carrying on its top surface a printed circuit interconnect conductor array having a plurality of signal, power and ground conductors.
  • Each conductor has an inner end positioned on the TAB tape for connection to a corresponding contact on a die, with the inner ends being closely spaced in a high-density array surrounding a central area where the die is to be received.
  • the conductors fan outwardly from the central area, and the ground and power conductors are connected at or near their outer ends to corresponding burn-in pads located near the periphery of the TAB tape segment.
  • the burn-in pads are discrete conductive pads preferably formed as a part of the printed circuit conductor array.
  • the burn-in pads Since most of the contacts on the die are signal contacts, and only some of -the die contacts- are ground or power contacts; the number of " burn-in pads is * considerably less than ' h total"" number of conductors in the array. As a result, the burn-in pads have a relatively low density and can be large and widely spaced near the periphery of the TAB tape segment to facilitate connection of the interconnect conductors to a test socket, by which burn-in voltages can be applied to the power and ground conductors. If desired, the burn-in pads can have a constant pattern, even for different TAB conductor arrays, so that a single test socket can be provided for different dies.
  • the burn-in pads in one form of the invention are on the same surface of the TAB tape as the interconnect conductors, but in a preferred form they are on the opposite surface of the tape.
  • the conductor array is on a first surface of the tape, and may, for example, have the same conductor pattern as in the first embodiment, but in this case there would be no burn-in pads on the first surface.
  • the burn-in pads are located on the opposite surface of the TAB tape, and are aligned with corresponding power conductors to which they are electrically connected by way of via holes through the TAB tape.
  • burn-in pads for the ground conductors may be used, but are not necessary, for the metal foil on "the second surface remaining after the burn-in pads are etched can be used as a common ground plane.
  • the ground plane is connected to the ground conductors on the first surface by way of vias formed through the TAB tape.
  • the burn-in pads for the power conductors are formed as insulated islands in the foil layer on the bottom surface of the TAB tape, isolating the pads from the surrounding ground plane.
  • the pads are located near the periphery of the TAB device so that they will have a relatively low density and a large contact area to facilitate use of a simple test socket.
  • Fig. 1 is a top plan view of a TAB interconnect tape carrying a printed circuit constructed in accordance with a first embodiment of the present invention
  • Fig. 2 is a partial top plan view of a second embodiment of the TAB interconnect tape of the present invention.
  • Fig. 3 is a partial bottom plan view of the TAB interconnect tape of Fig. 2;
  • Fig. 4 is a cross-sectional view of the device of Fig. 3, taken along lines 4-4. Best Mode for Carrying Out the Invention
  • Fig. 1 a TAB interconnect tape segment 10 constructed from a thin insulating tape material 12 carrying a metal foil printed circuit conductor array generally illustrated at 14.
  • the TAB tape is- usually an ' elongated "; strip, typically supplied- from a- tape reel, and " -may” have edge "" sprocket, holes (not shown)-for ⁇ indexing',' with " the tape carrying repetitive patterns of conductor arrays in the conductor foil.
  • the conductor arrays are normally fabricated in the metal foil layer of the tape by printing, masking and etching techniques, as is well known in the printed circuit art. Only a single printed circuit conductor array 14 is illustrated in the tape segment 10 of Fig. 1, but it will be understood that a TAB tape will typically carry a large number of such conductor arrays spaced along the length of the tape. Each conductor array 14 typically includes a multiplicity of electrical conductors which provide electrical paths between contacts on semiconductor chips, or dies (not shown) mounted on the tape and suitable external circuitry to which the semiconductor chip is to be connected.
  • the array 14 includes a large number of individual interconnect conductors 16 mounted on the insulating tape 12 and forming a fanned-out pattern to provide sufficient space between adjacent conductors to facilitate connection of the power, ground and signal leads on the semiconductor chip to an external circuit for permanent mounting or for test purposes.
  • the inmost ends 18 of the conductors 16 terminate at the center of the array in a pattern which exactly matches the pattern of contact points on a semiconductor chip to be mounted on the TAB tape, and thus define a chip receiving area 20 at the center of the array.
  • the die is positioned in the center of array 14 over the central area 20 with its contacts in alignment with the inmost ends 18 of the printed circuit array 14.
  • the contact points on the die are then bonded to the corresponding inner ends 18, for example, by pressure bonding.
  • the attached semiconductor chip, the bonds, and the inner ends of the interconnect conductors 16 are encapsulated to form a molded plastic package in the region illustrated by the dotted lines 22.
  • a suitable carrier frame (not shown) may be mounted on the carrier tape 12 and the tape segment 10 trimmed from the continuous strip to provide a chip package carrier, as is known in the art.
  • the array 14 illustrated in Fig. 1 is simplified to facilitate illustration of the invention, and thus includes only a small proportion of the interconnect conductors usually required for a complex semiconductor integrated circuit.
  • Such circuits may have in excess of 300 connection points formed in the general pattern illustrated at area 20 in Fig. 1, to be connected to the inner ends 18 of the conductors 16.
  • the conductors 16 are formed outwardly toward the peripheral edge 34 of the segment 10, and may have a pitch, or center to center distance, of about 8 mils, at the outer ends 36.
  • a test socket for connection to all of these closely-spaced outer ends requires a large number of extremely closely-spaced contacts.
  • test socket would be very expensive and time-consuming, since it would be a special-purpose tool that would have to be made to match a particular conductor array. Accordingly, burn-in testing of semiconductor chips even after they are mounted on the tape segment 10 and connected to the conductor array 14, remained difficult and expensive in the prior art.
  • burn-in testing is facilitated by the provision of a series of discrete, spaced, burn-in test pads 40, located around the peripheral edge 34 of the tape segment 10.
  • These test pads are formed at the same time as the array 14, using the same printed circuit techniques of printing, masking and etching, with the pads being connected directly to, or indirectly by way of conductor extensions 42, to the outer ends 36 of selected interconnect conductors 16.
  • the selected conductors 16 lead, in turn, to corresponding ground or power supply contact points on the semiconductor chip mounted on the TAB tape.
  • selected burn-in test pads 40 serve as ground points for the semiconductor chip, while other pads serve as power supply points for the chip.
  • the design of a socket for providing the required burn-in voltages to the semiconductor chip is greatly simplified, for the socket contacts can be relatively large and widely spaced, with only about 40 contacts being needed. This allows high lead count TAB devices to be burned in with a low cost, simple and readily available socket.
  • the burn-in pads 40 be evenly spaced about the peripheral edge of the segment 10.
  • a standard pattern for the pads 40 may be provided so that a standardized burn-in socket can be utilized. In such a case, the individual pads would be located in known positions, and the interconnections by way of conductor extensions 42 would then be included as a part of the design of the printed circuit array 14 to provide the desired connections.
  • Fig. 1 the entire printed circuit array and the burn-in pads are formed on a single surface of the TAB tape.
  • FIGs. 2, 3 and 4 An alternative configuration is illustrated in Figs. 2, 3 and 4, where the conductor array is on one surface of the tape 12, as before, but the burn-in test pads are formed on the opposite surface of the tape.
  • the assembly of Fig. 1 has the advantage of only requiring metal foil on one side of the support tape 12, whereas the configuration of Figs. 2 to 4 requires metallization on both surfaces of the tape.
  • the conductor array and the burn-in pads are formed on a TAB segment 50.
  • the TAB segment in this embodiment includes a tape 52, which is an insulating film or layer 52 that is metallized on both the top and bottom surfaces.
  • a thin metal foil on the top surface is patterned and etched in a conventional way to form a printed circuit conductor array 54 having a multiplicity of interconnect conductors 56, corresponding to the array 14 and conductors 16 described with respect to Fig. 1.
  • a thin metal foil 58 on the bottom surface of the tape (Fig. 3) is patterned and etched in conventional manner to provide a plurality of discrete, spaced burn-in pads 60.
  • the entire foil layer 58 except for pads 60 may be etched away, if desired, but preferably layer 58 is retained, with the pad areas being defined by etched-away regions 62 surrounding each pad, isolating the pads from the rest of the layer 58 so that the foil surrounding the pads will serve as a metallic ground plane.
  • the conductors 56 in array 54 have inner ends 64 which are located adjacent a chip-receiving area 66 located generally at the center of the printed circuit array.
  • the inner ends 64 are spaced and located for alignment with corresponding contact points on the integrated circuit chip to be mounted on segment 50.
  • the conductors 56 fan outwardly from their contact points with the chip so that the outermost ends 68 are more widely spaced than the innermost ends 64 to facilitate connection of the conductors to exterior circuits or to test equipment.
  • the array 54 may include in excess of 300 conductors connected to corresponding contacts on a semiconductor integrated circuit chip, with the pitch of the conductors being, for example, about 8 mils at the outer ends.
  • the film or tape 52 is an insulating material such as Kapton, while the metal foil preferably is copper. Because the leads 56 are copper foil with a protective surface metallization, it is conventional to provide plating busses or conductive cross-link 70 extending between the outer ends of conductors 56 to allow electroplating of the protective surface metallization. To facilitate removal of the plating busses 70, excise apertures 72 are provided. Additional excise apertures 74 are provided to permit severing of the conductors leading to the burn-in pads 60. If desired, a conductor support bar (not shown) formed from the insulating film may be provided to stabilize the conductors in the excise apertures 72, if desired. Preferably such-stabilizing bars are adhered to the bottom surfaces of the conductors 56.
  • a plurality of the TAB burn-in test pads 60 are formed from the metal foil layer 58.
  • the pads 60 are formed from the metal foil layer 58.
  • the pads 60 are formed by conventional printing, masking and etching techniques, as discussed above, to isolate the pads from the surrounding metal layer 58 when that layer is retained as a ground plane, with the result that each pad is surrounded by an individual etched-away region which forms a peripheral insulating channel such as those illustrated at 62 in Figs 3 and 4.
  • the channels are etched through the metal layer 58 to expose the underlying insulating tape.
  • the pads 60 are thus electrically insulated from the metal layer 58 and from each other so that they can be used as contacts for the burn-in process.
  • the burn-in test pads 60 are connected to selected power or ground conductors 56 on the opposite side of the insulating tape 52 by way of connector leads which pass through vias, or through openings, such as those illustrated at 80 and 82.
  • the vias are formed through the insulating layer 52 of Kapton, again by conventional masking and etching techniques, and are located to intersect selected conductors 56.
  • the vias preferably are formed prior to the metallization of the Kapton tape, so that when the foil layers are plated on the tape, the metal will flow through the vias to provide through conductors to provide electrical connections between the top and bottom metal layers on the tape 52. Thereafter, when the metal layers are patterned and etched to form the conductors 56 on the top surface (Fig.
  • the burn-in pads 60 can be used to connect a test socket to the die.
  • bias power conductors of array 54 are provided for the bias power conductors of array 54, while the layer 58 provides a ground plane which surrounds the individual pads.
  • the ground plane film 58 for the TAB device is thus 16 connected to the ground points on the die by way of selected conductors 56. Accordingly, bias power voltages may be applied to he die by way of pads 60 and ground plane 58 to burn-in the die connected to array 54.
  • the burn-in pads 60 are preferably located in a regular pattern near the peripheral edge of the tape segment 50 to facilitate contact with a burn-in socket.
  • the burn-in takes place after removal of the cross-links 70 so that the signal-carrying conductors, which are not connected to the burn-in pads, will not receive the power supply voltages.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Un segment de film (10) de bondérisation automatique à film porte sur sa surface supérieure une matrice (14) à haute densité de conducteurs d'interconnexion de circuits imprimés qui comprend une pluralité de conducteurs (16) de signaux, d'alimentation et de mise à la terre. Des pastilles (40) pour essais de vieillissement sont agencées soit sur la surface supérieure soit sur la surface inférieure du segment de film, ou sur les deux surfaces, et sont connectées à des conducteurs sélectionnés. Les pastilles d'essai sont mutuellement espacées et présentent une densité relativement faible afin de faciliter le contact avec l'équipement d'essai, ce qui permet de tester un dé connecté au réseau de circuits imprimés.
EP89903601A 1988-03-28 1989-03-14 Pastilles d'essai de vieillissement pour structures d'interconnexion a bonderisation automatique a film Withdrawn EP0364536A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17309488A 1988-03-28 1988-03-28
US173094 1988-03-28

Publications (1)

Publication Number Publication Date
EP0364536A1 true EP0364536A1 (fr) 1990-04-25

Family

ID=22630520

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89903601A Withdrawn EP0364536A1 (fr) 1988-03-28 1989-03-14 Pastilles d'essai de vieillissement pour structures d'interconnexion a bonderisation automatique a film

Country Status (4)

Country Link
EP (1) EP0364536A1 (fr)
JP (1) JPH02500221A (fr)
CA (1) CA1303752C (fr)
WO (1) WO1989009493A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150047A (en) * 1989-07-21 1992-09-22 Nippon Steel Corporation Member for use in assembly of integrated circuit elements and a method of testing assembled integrated circuit elements
DE4204459A1 (de) * 1992-02-14 1993-08-19 Siemens Nixdorf Inf Syst Filmtraegermontierter integrierter baustein
FR2739742B1 (fr) * 1995-10-09 1997-12-05 Sagem Procede de fabrication de module a micro-composants et support a circuits imprimes de liaison, et produit intermediaire de mise en oeuvre du procede
JP3717660B2 (ja) 1998-04-28 2005-11-16 株式会社ルネサステクノロジ フィルムキャリア及びバーンイン方法
JP5215032B2 (ja) * 2008-05-09 2013-06-19 スパンション エルエルシー 半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386389A (en) * 1981-09-08 1983-05-31 Mostek Corporation Single layer burn-in tape for integrated circuit
US4701363A (en) * 1986-01-27 1987-10-20 Olin Corporation Process for manufacturing bumped tape for tape automated bonding and the product produced thereby

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8909493A1 *

Also Published As

Publication number Publication date
JPH02500221A (ja) 1990-01-25
WO1989009493A1 (fr) 1989-10-05
CA1303752C (fr) 1992-06-16

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