CA1303752C - Plots de deverminage pour circuits imprimes associes structurellement - Google Patents

Plots de deverminage pour circuits imprimes associes structurellement

Info

Publication number
CA1303752C
CA1303752C CA000594187A CA594187A CA1303752C CA 1303752 C CA1303752 C CA 1303752C CA 000594187 A CA000594187 A CA 000594187A CA 594187 A CA594187 A CA 594187A CA 1303752 C CA1303752 C CA 1303752C
Authority
CA
Canada
Prior art keywords
burn
pads
tape
conductors
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA000594187A
Other languages
English (en)
Inventor
Richard A. Chase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of CA1303752C publication Critical patent/CA1303752C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
CA000594187A 1988-03-28 1989-03-20 Plots de deverminage pour circuits imprimes associes structurellement Expired - Fee Related CA1303752C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17309488A 1988-03-28 1988-03-28
US07/173,094 1988-03-28

Publications (1)

Publication Number Publication Date
CA1303752C true CA1303752C (fr) 1992-06-16

Family

ID=22630520

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000594187A Expired - Fee Related CA1303752C (fr) 1988-03-28 1989-03-20 Plots de deverminage pour circuits imprimes associes structurellement

Country Status (4)

Country Link
EP (1) EP0364536A1 (fr)
JP (1) JPH02500221A (fr)
CA (1) CA1303752C (fr)
WO (1) WO1989009493A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150047A (en) * 1989-07-21 1992-09-22 Nippon Steel Corporation Member for use in assembly of integrated circuit elements and a method of testing assembled integrated circuit elements
DE4204459A1 (de) * 1992-02-14 1993-08-19 Siemens Nixdorf Inf Syst Filmtraegermontierter integrierter baustein
FR2739742B1 (fr) * 1995-10-09 1997-12-05 Sagem Procede de fabrication de module a micro-composants et support a circuits imprimes de liaison, et produit intermediaire de mise en oeuvre du procede
JP3717660B2 (ja) 1998-04-28 2005-11-16 株式会社ルネサステクノロジ フィルムキャリア及びバーンイン方法
JP5215032B2 (ja) * 2008-05-09 2013-06-19 スパンション エルエルシー 半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386389A (en) * 1981-09-08 1983-05-31 Mostek Corporation Single layer burn-in tape for integrated circuit
US4701363A (en) * 1986-01-27 1987-10-20 Olin Corporation Process for manufacturing bumped tape for tape automated bonding and the product produced thereby

Also Published As

Publication number Publication date
JPH02500221A (ja) 1990-01-25
EP0364536A1 (fr) 1990-04-25
WO1989009493A1 (fr) 1989-10-05

Similar Documents

Publication Publication Date Title
US5036380A (en) Burn-in pads for tab interconnects
US4801561A (en) Method for making a pre-testable semiconductor die package
US4763409A (en) Method of manufacturing semiconductor device
EP0494782B1 (fr) Système de test et de vieillissement thermique pour une plaquette semi-conductrice et méthode pour sa fabrication
US5315241A (en) Method for testing integrated circuits
US5461328A (en) Fixture for burn-in testing of semiconductor wafers
US4977441A (en) Semiconductor device and tape carrier
US4701781A (en) Pre-testable semiconductor die package
US6020745A (en) Method of batch testing surface mount devices using a substrate edge connector
US6967494B2 (en) Wafer-interposer assembly
US4806409A (en) Process for providing an improved electroplated tape automated bonding tape and the product produced thereby
US5378981A (en) Method for testing a semiconductor device on a universal test circuit substrate
US6275051B1 (en) Segmented architecture for wafer test and burn-in
US5801432A (en) Electronic system using multi-layer tab tape semiconductor device having distinct signal, power and ground planes
US5544018A (en) Electrical interconnect device with customizeable surface layer and interwoven signal lines
US6448634B1 (en) Tape carrier, semiconductor assembly, semiconductor device and electronic instrument
JPH07221146A (ja) 半導体デバイス用非破壊相互接続システム
US5748209A (en) Thermal ink jet tab circuit having a plurality of trace groups wherein adjacent traces in each group are staggered
US6255602B1 (en) Multiple layer electrical interface
US5937515A (en) Reconfigurable circuit fabrication method
JPS6369247A (ja) プローブ装置
US5061988A (en) Integrated circuit chip interconnect
US4223337A (en) Semiconductor integrated circuit with electrode pad suited for a characteristic testing
US4981817A (en) Tab method for implementing dynamic chip burn-in
JP2874682B2 (ja) 半導体装置

Legal Events

Date Code Title Description
MKLA Lapsed