EP0057024A1 - Dispositif semiconducteur comportant un dispositif de sécurité - Google Patents

Dispositif semiconducteur comportant un dispositif de sécurité Download PDF

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Publication number
EP0057024A1
EP0057024A1 EP82200025A EP82200025A EP0057024A1 EP 0057024 A1 EP0057024 A1 EP 0057024A1 EP 82200025 A EP82200025 A EP 82200025A EP 82200025 A EP82200025 A EP 82200025A EP 0057024 A1 EP0057024 A1 EP 0057024A1
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European Patent Office
Prior art keywords
zone
collector
electrode
layer
voltage
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EP82200025A
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German (de)
English (en)
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EP0057024B1 (fr
Inventor
Hendrik Cornelis De Graaff
Wilhelmus Gerlachus Voncken
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Koninklijke Philips NV
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Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0722Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors

Definitions

  • the invention relates to a semiconductor device comprising at least one circuit element and having a semi- conductor body, in which the said semiconductor body comprises at least a first and a second electrode, which first electrode is connected to the said circuit element, in which a safety device is provided between the said first and second electrode so as to protect the first electrode from the occurrence of excess voltages above a previously determined value with respect to the voltage of the second electrode, which safety device comprises a lateral bipolar transistor having an emitter zone and a collector zone of a first conductivity type which adjoin a surface of the semiconductor body in laterally separated places and having an adjoining base region of a second conductivity type which forms a first and a second p-n junction with the said emitter zone and collector zone respectively, an insulating layer being present on the said surface of the semiconductor body, the base region between the said emitter zone and collector zone adjoining the insulating layer, the said insulating layer separating first, second and third conductive layers from the said semiconductor body, the first electrode comprising the first conductive layer which is connected to
  • a semiconductor device with a safety device comprising a lateral bipolar transistor as described above is known from British Patent Specification 1, 337,220.
  • the third conductive layer which extends above the base region is connected to the emitter zone so as to provide a "field relief electrode" to reduce the avalanche breakdown voltage of the collector junction.
  • the insulating layer has a thin portion at the area where the third conductive layer extends above the collector-base junction.
  • an insulated gate field effect transistor as a circuit element for such an integrated circuit to have a gate insulator which is as thin as possible so as to have good properties, for example, to increase the mutual conductance for rapid operation and lower operating voltage. Reduction of the thickness of a gate insulator, however, will lead to a reduced dielectric breakdown voltage and will give rise to breakdown of the gate insulator during operation as a result of accidental application of high voltage pulses of static electricity.
  • One of the objects of the invention is to provide an improved lateral bipolar safety transistor.
  • the semiconductor device of the kind mentioned in the opening paragraph is characterized according to the invention in that the said first and-third conductive layers are conductively connected together and both belong to the said first electrode, the third conductive layer forming a gate electrode of an auxiliary field effect transistor structure which furthermore comprises the emitter zone as source region and the collector zone as drain region, the said auxiliary field effect transistor structure having a threshold voltage which is lower than the said breakdown voltage of the second junction and which is preferably at least equal to the said collector-emitter voltage.
  • the voltage at which the bipolar transistor switches from the non-conductive to the conductive state is reduced by means of the field effect transistor and the switching speed of the bipolar safety transistor is increased.
  • the auxiliary field effect transistor becomes conductive before avalanche breakdown of the collector junction of the bipolar safety transistor takes place.
  • the effect of the auxiliary field effect transistor is that the conductive auxiliary field effect transistor injects charge carriers into the depletion region of the collector junction. As a result of avalanche multiplication the injected charge carriers may result in an extra current which flows through the base region and provides a potential which is sufficient to bias the emitter junction in the forward direction and to initiate bipolar transistor action.
  • the semiconductor device shown in Figures 1 and 2 has a circuit element which in this embodiment is formed by the field effect transistor 1 which is connected to a first electrode 2 which should be protected from the occurrence of excess voltages above a previously determined value with respect to the voltage of a second electrode 3, 3'.
  • a safety device 4 is connected between the first and the second electrodes 2 and 3, 3', respectively.
  • the safety device 4 comprises a lateral bipolar transistor 5 which according to the invention is provided with an auxiliary field effect transistor structure 6.
  • the semiconductor device has a semiconductor body 7 (Figure 2) with at least a first electrode and a second electrode 2 and 3, respectively, which body is common for a number of circuit elements (only one circuit element, in this embodiment the field effect transistor 1, is shown) and for the safety device 4 which comprises the lateral bipolar transistor having a built-in auxiliary field effect transistor.
  • the circuit element is the field effect transistor 1 which comprises a source region 112 and a drain region 113 of a first conductivity type, a thin gate insulator 114 and a gate electrode 115.
  • the lateral bipolar transistor provided as a safety device has an emitter zone 8 and a collector zone 9 of the first conductivity type which in laterally separated placed adjoins a surface 11 of the semiconductor body 7, and has an adjoining base region 10 of a second conductivity type which forms a first emitter p - n junction 12 and a second collector p-n junction 13,respectively, with the emitter zone and collector zone 8 and 9, respectively.
  • the surface 11 of the semiconductor body 7 is covered with an insulating layer 14. Between the emitter zone 8 and the collector zone 9 the base region 10 adjoins the insulating layer 14.
  • the insulating layer 14 furthermore separates the first, second and third conductive layers 13, 16, 17 from the semiconductor body 7, which layers are present above the collector zone 9, emitter zone 8 and base region 10, respectively.
  • the first electrode 2 comprises the first conductive layer 15 which is conductively connected to the collector zone 9.
  • the second electrode 3 comprises the second conductive layer 16 which is conductively connected to the emitter zone 8.
  • the third conductive layer 17 extends above the base region 10 between the emitter zone and collector zone 8, 9.
  • the first and third conductive layers 15, 17 are conductively connected together and both belong to the first electrode 2, the third conductive layer 17 forming a gate electrode of an auxiliary field effect transistor structure.
  • the auxiliary field effect transistor structure comprises the emitter zone 8 as source region and the collector zone 9 as drain region.
  • Figure 3 shows diagrammatically current-voltage characteristics of the safety device which is used in the semiconductor device shown in Figures 1 and 2.
  • the Figure shows the current which flows between the first electrode 2 and the second electrode 3 and/or 3' according ae the excess voltage applied to the first electrode increases from zero in a positive direction.
  • the generated mobile charge carriers can take up energy from the electric field. As soon as at least a few of these carriers have obtained sufficient energy therefor, further ionization may take place so that extra mobile charge carriers are generated.
  • the multiplication of mobile carriers further increases when the voltage increases and leads to an avalanche effect.
  • the diode junction breaks down and the current increases rapidly.
  • the current-voltage characteristic of the diode is shown diagrammatically in Figure 3 by the broken-line curve 202. In the semiconductor device shown in Figure 2 this curve 202 can be measured between the electrodes 2 and 3' if the latter is not interconnected to the electrode 3.
  • the collector-base junction does not show a normal avalanche breakdown as is indicated by curve 202, if the electrode 3 is connected to the electrode 3'.
  • An additional effect is that the leakage current flows to ground through the base region 10 and the substrate 7. As a result of this current and the series resistance of the base region the potential at the emitter-base junction 12 is increased.
  • the voltage across the emitter-base junction 12 increases until the emitter region 8 starts to inject charge carriers (electrons) in the base 10.
  • the current level at which the bipolar transistor switches to the on-state depends inter alia on the series resistance in the base reginn and the location of the conductive contact with said base region.
  • a conductive base contact may be provided on the lower side of the substrate 7 (electrode 3' in Figure 2) or in known manner on the upper surface 11 of the semiconductor body.
  • the safety transistor will operate similarly when the base region is kept floating. With a floating base region the leakage current of the collector-base junction will charge the base region so that the potential thereof increases until the voltage across the emitter-base junction has been increased sufficiently to initiate the transistor action. With a floating base region a voltage is measured between the electrodes 3 and 2 in the on-condition, which in bipolar transistors is generally denoted by BV CEO .
  • the avalanche breakdown voltage of the collector-base junction (the voltage at point 204 in Figure 3) is higher than the collector-emitter voltage of the lateral bipolar transistor in the conductive or on-state (curve 203).
  • the avalanche breakdown voltage was approximately 20 Volts and the collector-emitter voltage in the on-state was approximately 12 Volts.
  • the known lateral bipolar-transistor is improved by an incorporated auxiliary field effect transistor to which the excess voltage is applied between its gate electrode and its source region.
  • the threshold voltage of the auxiliary field effect transistor is chosen to be lower than the avalanche breakdown voltage of the collector-base junction. When the voltage increases the auxiliary field effect transistor will thus become conductive at the instant at which the threshold voltage is reached and before avalanche breakdown of the collector-base junction occurs. Electrons will flow through the auxiliary transistor from the emitter/source region into the field effect transistor channel and to the depletion region of the collector/base junction (drain-substrate junction). At least a part of the electrons will produce a multiplication process and will generate both new electrons and new holes.
  • the current through the safety device according to the invention increases more rapidly than in a lateral safety transistor of a conventional structure.
  • the improved safety transistor enters the transition state at a lower voltage (point 205 in Figure 3) and then switches (again shown diagrammatically by dots) to the on-state of the lateral bipolar transistor indicated by curve 203.
  • the auxiliary field effect transistor provides an extra base current source and thus increases the switching speed of the bipolar transistor with which said transistor changes from the off or blocked state to the on or readily conducting state. The actual switching occurs at a lower voltage level.
  • the auxiliary field effect transistor resulted in an improved switcing at approximately 17 Volts.
  • the above-mentioned preferred embodiment of the semi-conductor device with a safety device according to the invention can be manufactured in and on the same semi- conductor body together with other circuit elements, for example, field effect transistors, diodes and resistors, without this requiring extra steps.
  • the starting material is a semiconductor body 7, for example, a silicon substrate of the p-conductivity type having a resistivity of, for example, approximately 10 ohm.cm.
  • a surface 11 of the substrate 7 is covered with a layer masking against ion implantation and oxidation.
  • This layer comprises an approximately 400 R thick silicon oxide film 18 and an approximately 750 A thick silicon nitride film 19 which are provided in the usual manner, for example, by chemical deposition from the vapour phase.
  • An aperture is then formed in the masking layer 18, 19, in which aperture a highly doped zone 20 of the P-conductivity type is provided by boron implantation at 30 keV with a dose of 2.4 x 10 13 cm -2 .
  • the silicon oxide layer 14 comprises a portion 424 for field passivation and a portion 414 which is destined for the field effect transistor of the safety device.
  • the highly doped zone 20 of the p-conductivity type serves to prevent the formation of undesired channels below the field oxide 424 during operation of the semiconductor device.
  • the masking layer comprising the silicon nitride film 19 and the silicon oxide film 18 is removed at least partly so that the surface 11 of the semiconductor body is exposed selectively in regions where semiconductor zones for the circuit element 1 and the safety device 4 are to be provided (see Figure 5).
  • the first region 401 of the semiconductor body is destined for providing circuit elements, in this embodi-. ment the field effect transistor 1.
  • the second region 404 of the semiconductor body is destined for the safety device 4.
  • the second reginn 404 has two exposed parts which are destined for providing an emitter zone and a collector zone of the lateral bipolar transistor 5.
  • a thin gate insulator 114 comprising an approximately 500 A thick silicon oxide layer provided by thermal oxidation and a gate electrode 115 comprising an approximately 0.4 micron thick polycrystalline silicon layer provided by deposition, while using conventional methods.
  • the silicon gate electrode is highly doped with phosphorus (see Figure 5).
  • a doping impurity to provide the n-conductivity type is introduced into the exposed surface parts of the substrate 7 in regions 401, 404 for the simultaneous formation of the source region 112 and the drain region 113 of the field effect transistor 1 and the emitter zone and collector zone 8, 9 of the bipolar transistor 5.
  • the gate electrode 115 is also exposed to said doping operation.
  • the doping impurity providing the n-conductivity type consists of arsenic.
  • arsenic ions are implanted while using an energy of 100 KeV and a dose of 5 x 10 15 cm -2 (see Figure 5).
  • the semiconductor body is then subjected to a thermal treatment so as to activate the implanted dopant.
  • a thermal treatment so as to activate the implanted dopant.
  • an approximately 0.1 micron thick thermally grown silicon oxide layer 116 is formed on the exposed surface of the polycrystalline silicon gate electrode layer 115 and on exposed surfaces of the doped regions of the n-conductivity type (see Figure 6).
  • a silicon oxide layer 434 is provided on the whole surface of the semi- conductor body by chemical deposition from the vapour phase (see Figure 7).
  • a conductive layer 402 is provided on the surface of the semiconductor body by deposition from the vapour phase.
  • a metal layer for example, an aluminium layer, may be used for the layer 402.
  • the metal layer 402 is patterned so as to form a connection pattern comprising a first conductive layer 15 (see Figure 8) on the collector zone 9, a second conductive layer 16 on the emitter zone 8 and a third conductive layer 17 on the thick gate insulation layer 414.
  • the first and third conductive layers 15, 17 are conductively connected together and both belong to the first electrode 2 which is shown in Figure 1 and which is connected to the gate electrode 115 of the field effect . transistor 1.
  • the second conductive layer 16 is conductively connected to the emitter zone 8 of the bipolar safety transistor 5 and belongs to the second electrode 3 which is shown in Figure 1.
  • This electrode 3 may be connected to a reference potential, for example, ground.
  • the safety transistor will also limit the potential difference between the electrodes 2 and 3 to safe values without external connection of the electrode.
  • the safety device is advantageous for the safety device to be otbained without extra steps in the manufacture being required.
  • the safety device is provided by means of the same method as the circuit element.
  • the emitter and collector zones 8, 9 of the bipolar transistor and the source and drain regions 112, 113 of the field effect transistor are simultaneously formed.
  • the thin gate insulator 114 and the gate electrode 115 of the field effect transistor are provided in accordance with previously determined characteristics of the circuit element by means of conventional methods, for example, thermal oxidation and deposition.
  • the portion 414 of the thick gate insulation layer of the safety device 4 and the portion 424 of the field oxide layer furthermore are formed simultaneously by thermal oxidation while using the silicon nitride film 19 as a mask.
  • portion 414 is used as a sub- layer of the gate insulating layer of the auxiliary field effect transistor is that the threshold voltage of said auxiliary field effect transistor should be sufficiently high to prevent the safety device forming a leakage path between said electrodes 2 and 3 when normal operating voltages are applied to the electrodes 2 and 3.
  • the safety device should be in the off-state. This will be the case, for example, when the threshold voltage of the auxiliary transistor and the voltage at which the safety device switches to the on-state (point 205 in Figure 3) are higher than the supply voltage of the integrated circuit.
  • These two voltages are preferably each approximately equal to'or at least equal to the (preferably smallest) threshold voltage for parasitic channel formation in the field oxide region (so below the insulating layer 14; 424; 434).
  • the threshold voltage for parasitic channel formation below polycrystalline silicon tracks provided simultaneously with the gate electrode 115 but present on the thermal oxide 424 was approximately 12 volts.
  • the collector-emitter voltage of the safety device in theon-state (curve 203 in Figure 3) is also higher than the supply voltage. In that case the safety device will automatically return to the off-state after dissipation of an excess voltage surge.
  • the auxiliary field effect transistor is conductive only when the collector- base voltage is high enough to enable the occurrence of multiplication in the depletion layer.
  • the threshold voltage of the auxiliary field effect transistor is preferably at least equal to the collector-emitter voltage of the safety device in the on-state.
  • the thickness of the insulating layer or layers present in the safety device should preferably be larger than the thickness of the thinnest part of the insulating layer which is present below the conductive layers of electrode 2.
  • the insulating layer portion of the safety device should preferably withstand higher voltages than any dielectric and/or insulating layer portion which is to be protected against electrical breakdown.
  • the structure of the embodiment described is to be preferred.
  • the threshold voltage of the auxiiary field effect transistor will be lower than in the preferred embodiment and probably lower than is -necessary or desirable. Not counting this, however, another problem is prevented by using a double layer 414, 434 as a gate dielectric.
  • a double layer 414, 434 as a gate dielectric.
  • locally thermally grown oxide layers have the tendency of showing the so-called bird beak at the oxide edge.
  • gate electrode 17 should preferably bridge the whole gap between the emitter and collector zones 8, 9 so as to be sure that an excess voltage will induce a conductive channel in a controlled manner which connects the source region 8 readily with the depletion region of the drain regi-on 9. Consequently, it is nearly inevitable that the polysilicon gate will extend on the thin oxide of the bird beak. As already described above, the presence of such thin oxide layers in the safety device may seriously endanger the reliability of the safety device. For this and other reasons it is preferred to provide the gate electrode 17 of the auxiliary field effect transistor simultaneously with the conductor tracks which are present at a second connection level of the integrated circuit, which tracks may be used to contact the gate electrode 115 and the semiconductor zones 8, 9, 112 and 113.
  • the insulating layer which separates the conductive tracks of the first and second connection level from each other may be used to form a sub-layer of the gate dielectric of the auxilary field effect transistor.
  • the gate dielectric is composed of two insulating layers 414 and 434, respectively, the sublayer 414 being grown thermally and the sub-layer 434 being deposited.
  • the double layer dielectric 414, 434 is also used with a view to the threshold voltage which is desired for the auxilary field effect transistor and which is comparatively high as compared with, for example, the threshold voltage of field effect transistor 1.
  • the threshold voltage of the auxiliary transistor may further be increased by using a more highly doped zone in the base zone 10 below the insulating layer 414, 434 and the gate electrode 17. As in the example, such a highly doped zone may be provided simultaneously with the channel stopper region 20 below the field oxide.
  • the collector base avalanche breakdown voltage will be reduced. This is a suitable means to shift point 204 and also point 205 of Figure 3 towards lower voltages.
  • the more highly doped zone as used in the safety device of the example provides both an increase of the threshold voltage and a decrease of the avalanche breakdown voltage and switching voltage.
  • the threshold voltage can be increased independently by the selective provision of a p-type dopant near the source region, for example, by introduction of such a dopant through the same window as is used to obtain the emitter region 8.
  • the avalanche breakdown voltage and the switching voltage can be reduced nearly independently of the threshold voltage by the selective provision of a p-type dopant near the collector zone 9.
  • the more highly doped p-type zone is preferably provided so as to adjoin the collector-base junction and in such manner that the more highly doped zone will be depleted entirely or nearly entirely when voltages which are approximately equal to or higher than the collector-emitter voltage of the lateral bipolar transistor are applied.
  • the more highly doped zone is preferably present within the depletion region of the collector-base junction so that the more highly doped zone does not extend or does substantially not extend in the actual channel region of the auxiliary field effect transistor.
  • the safety device may also be used to protect output electrodes and/or supply electrodes of semiconductor devices from excess voltages.
  • the base region 10 is not necessarily formed by a part of the substrate region 7.
  • the base region 10 may be formed by a p-type island region (also termed tub or well similar to the island regions which are used to provide the n-channel transistors therein.
  • the collector region 9 may be connected to electrode 2 (conductive layer 15 or 402) via a resistor of, for instance, about 200 ⁇ .
  • the gate electrode 17 of the auxiliary field effect transistor still may be connected directly to electrode 2.
  • the effect of such resistor is that upon the occurrence of fast rising voltage surges at electrode 2 the gate to source voltage of the auxiliary field effect transistor will rise faster than the collector to base (or collector to emitter) voltage of the lateral bipolar transistor. In this manner it may beensured that the auxiliary field effect transistor switches to its readily conducting state prior to the occurrence of breakdown at the collector-base-junction of the lateral bipolar transistor.
  • the resistor may be integrated as diffused resistor or as a polycrystalline silicon resistor.
  • the conductivity types are given only by way of example and may be interchanged. Other materials may also be used.
  • the semiconductor material may also consist, for example, of germanium or an A III -B V compound. Silicon nitride or aluminium oxide may be used as an insulating layer.
  • the insulating layer in the field region may be obtained by means of conventional methods other than local oxidation.
  • the polysilicon tracks may be provided with a suitable metal silicide or they may be replaced by a suitable metal silicide.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP82200025A 1981-01-26 1982-01-12 Dispositif semiconducteur comportant un dispositif de sécurité Expired EP0057024B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8100347 1981-01-26
NL8100347A NL8100347A (nl) 1981-01-26 1981-01-26 Halfgeleiderinrichting met een beveiligingsinrichting.

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EP0057024A1 true EP0057024A1 (fr) 1982-08-04
EP0057024B1 EP0057024B1 (fr) 1984-11-21

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US (1) US4697199A (fr)
EP (1) EP0057024B1 (fr)
JP (1) JPS57143860A (fr)
AU (1) AU550015B2 (fr)
CA (1) CA1180468A (fr)
DE (1) DE3261244D1 (fr)
IE (1) IE53096B1 (fr)
NL (1) NL8100347A (fr)

Cited By (12)

* Cited by examiner, † Cited by third party
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EP0161446A2 (fr) * 1984-03-31 1985-11-21 Kabushiki Kaisha Toshiba Circuit intégré semi-conducteur comprenant un transistor de protection et un transistor MOS ayant une structure LDD
EP0185426A1 (fr) * 1984-12-21 1986-06-25 Rtc-Compelec Circuit intégré comprenant un dispositif de protection contre les décharges électrostatiques
EP0291242A2 (fr) * 1987-05-15 1988-11-17 Advanced Micro Devices, Inc. Système de protection pour circuits intégrés CMOS
EP0292327A2 (fr) * 1987-05-22 1988-11-23 Sony Corporation Circuits de protection contre une rupture électrostatique
WO1989007334A1 (fr) * 1988-02-02 1989-08-10 Analog Devices, Inc. Circuit integre pourvu d'organes reduisant les dommages dus aux decharges electrostatiques
US4868621A (en) * 1987-03-31 1989-09-19 Kabushiki Kaisha Toshiba Input protection circuit
EP0355501A2 (fr) * 1988-08-16 1990-02-28 Siemens Aktiengesellschaft Transistor bipolaire comme élément de protection pour circuits intégrés
EP0381280A1 (fr) * 1989-02-01 1990-08-08 Koninklijke Philips Electronics N.V. Procédé de fabrication d'un circuit intégré avec un élément de protection
US5128739A (en) * 1983-12-07 1992-07-07 Fujitsu Limited MIS type semiconductor device formed in a semiconductor substrate having a well region
US5141898A (en) * 1988-02-02 1992-08-25 Analog Devices, Incorporated Integrated circuit with means for reducing ESD damage
US5436183A (en) * 1990-04-17 1995-07-25 National Semiconductor Corporation Electrostatic discharge protection transistor element fabrication process
EP0851552A1 (fr) * 1996-12-31 1998-07-01 STMicroelectronics S.r.l. Circuit de protection pour une ligne d'alimentation dans un dispositif intégré à semi-conducteurs

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812891A (en) * 1987-12-17 1989-03-14 Maxim Integrated Products Bipolar lateral pass-transistor for CMOS circuits
US5089433A (en) * 1988-08-08 1992-02-18 National Semiconductor Corporation Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture
US5225896A (en) * 1989-02-01 1993-07-06 U.S. Philips Corporation Protection element and method of manufacturing same
JPH0821840B2 (ja) * 1989-12-07 1996-03-04 富士電機株式会社 パワー半導体装置のスナバ回路
US5465189A (en) * 1990-03-05 1995-11-07 Texas Instruments Incorporated Low voltage triggering semiconductor controlled rectifiers
TW203148B (fr) * 1991-03-27 1993-04-01 American Telephone & Telegraph
US5401997A (en) * 1992-01-22 1995-03-28 Integrated Device Technology, Inc. ESD protection for poly resistor on oxide
JP2512118Y2 (ja) * 1993-01-30 1996-09-25 寛 野垣内 内装用造作柱材
US5459083A (en) * 1993-03-01 1995-10-17 Motorola, Inc. Method for making BIMOS device having a bipolar transistor and a MOS triggering transistor
US5733794A (en) * 1995-02-06 1998-03-31 Motorola, Inc. Process for forming a semiconductor device with ESD protection
KR100214235B1 (ko) * 1995-05-24 1999-08-02 가네꼬 히사시 반도체 장치 및 그 제조방법
JPH09312391A (ja) * 1996-05-22 1997-12-02 Toshiba Corp 半導体装置およびその製造方法
US6153892A (en) * 1998-02-12 2000-11-28 Nec Corporation Semiconductor device and method for manufacture thereof
US20140266393A1 (en) * 2013-03-14 2014-09-18 Linear Technology Corporation Bipolar transistor with lowered 1/f noise
US10937785B2 (en) * 2016-01-29 2021-03-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1805843A1 (de) * 1967-11-02 1969-10-23 Ncr Co Elektrische Schutzschaltung
GB1337220A (en) * 1971-12-09 1973-11-14 Ibm Monolithic entegrated circuit
US3789503A (en) * 1970-06-26 1974-02-05 Hitachi Ltd Insulated gate type field effect device and method of making the same
FR2289051A1 (fr) * 1974-10-22 1976-05-21 Ibm Dispositifs a semi-conducteur du genre transistors a effet de champ et a porte isolee et circuits de protection cotre les surtensions
FR2342557A1 (fr) * 1976-02-24 1977-09-23 Philips Nv Dispositif semiconducteur a circuit de protection

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3395290A (en) * 1965-10-08 1968-07-30 Gen Micro Electronics Inc Protective circuit for insulated gate metal oxide semiconductor fieldeffect device
US3407339A (en) * 1966-05-02 1968-10-22 North American Rockwell Voltage protection device utilizing a field effect transistor
GB1170705A (en) * 1967-02-27 1969-11-12 Hitachi Ltd An Insulated Gate Type Field Effect Semiconductor Device having a Breakdown Preventing Circuit Device and a method of manufacturing the same
US3673427A (en) * 1970-02-02 1972-06-27 Electronic Arrays Input circuit structure for mos integrated circuits
JPS53145486A (en) * 1977-05-24 1978-12-18 Mitsubishi Electric Corp Protecting circuit using insulated gate field effect type transistors
JPS5563871A (en) * 1978-11-06 1980-05-14 Nec Corp Protector for field-effect transistor with insulated gate
JPS55165682A (en) * 1979-06-11 1980-12-24 Mitsubishi Electric Corp Mos field effect semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1805843A1 (de) * 1967-11-02 1969-10-23 Ncr Co Elektrische Schutzschaltung
US3789503A (en) * 1970-06-26 1974-02-05 Hitachi Ltd Insulated gate type field effect device and method of making the same
GB1337220A (en) * 1971-12-09 1973-11-14 Ibm Monolithic entegrated circuit
FR2289051A1 (fr) * 1974-10-22 1976-05-21 Ibm Dispositifs a semi-conducteur du genre transistors a effet de champ et a porte isolee et circuits de protection cotre les surtensions
FR2342557A1 (fr) * 1976-02-24 1977-09-23 Philips Nv Dispositif semiconducteur a circuit de protection

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Vol. 20, No. 4, September 1977, New York, US A. BHATTACHARYYA et al.: "Dual base Lateral Bipolar Transistor", pages 1313-1314 *pages 1313-1314 * *
IBM Technical Disclosure Bulletin, Vol. 23, No. 2, July 1980, New York, USA D.G. BANKER et al.: "Lateral npn Protect Device", pages 594-595 *pages 594-595 * *

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128739A (en) * 1983-12-07 1992-07-07 Fujitsu Limited MIS type semiconductor device formed in a semiconductor substrate having a well region
EP0161446A3 (fr) * 1984-03-31 1986-11-26 Kabushiki Kaisha Toshiba Circuit intégré semi-conducteur comprenant un transistor de protection et un transistor MOS ayant une structure LDD
EP0161446A2 (fr) * 1984-03-31 1985-11-21 Kabushiki Kaisha Toshiba Circuit intégré semi-conducteur comprenant un transistor de protection et un transistor MOS ayant une structure LDD
EP0185426A1 (fr) * 1984-12-21 1986-06-25 Rtc-Compelec Circuit intégré comprenant un dispositif de protection contre les décharges électrostatiques
FR2575333A1 (fr) * 1984-12-21 1986-06-27 Radiotechnique Compelec Dispositif de protection d'un circuit integre contre les decharges electrostatiques
US4868621A (en) * 1987-03-31 1989-09-19 Kabushiki Kaisha Toshiba Input protection circuit
EP0291242A3 (en) * 1987-05-15 1990-09-12 Advanced Micro Devices, Inc. Protection system for cmos integrated circuits
EP0291242A2 (fr) * 1987-05-15 1988-11-17 Advanced Micro Devices, Inc. Système de protection pour circuits intégrés CMOS
EP0292327A2 (fr) * 1987-05-22 1988-11-23 Sony Corporation Circuits de protection contre une rupture électrostatique
EP0292327A3 (fr) * 1987-05-22 1990-06-13 Sony Corporation Circuits de protection contre une rupture électrostatique
EP0397780A1 (fr) * 1988-02-02 1990-11-22 Analog Devices, Incorporated Circuit integre pourvu d'organes reduisant les dommages dus aux decharges electrostatiques
EP0397780A4 (en) * 1988-02-02 1991-09-18 Analog Devices, Incorporated Ic with means for reducing esd damage
WO1989007334A1 (fr) * 1988-02-02 1989-08-10 Analog Devices, Inc. Circuit integre pourvu d'organes reduisant les dommages dus aux decharges electrostatiques
US5141898A (en) * 1988-02-02 1992-08-25 Analog Devices, Incorporated Integrated circuit with means for reducing ESD damage
EP0355501A2 (fr) * 1988-08-16 1990-02-28 Siemens Aktiengesellschaft Transistor bipolaire comme élément de protection pour circuits intégrés
EP0355501A3 (en) * 1988-08-16 1990-10-17 Siemens Aktiengesellschaft Bipolar transistor as protection device for integrated circuits
EP0381280A1 (fr) * 1989-02-01 1990-08-08 Koninklijke Philips Electronics N.V. Procédé de fabrication d'un circuit intégré avec un élément de protection
US5436183A (en) * 1990-04-17 1995-07-25 National Semiconductor Corporation Electrostatic discharge protection transistor element fabrication process
EP0851552A1 (fr) * 1996-12-31 1998-07-01 STMicroelectronics S.r.l. Circuit de protection pour une ligne d'alimentation dans un dispositif intégré à semi-conducteurs
US6072682A (en) * 1996-12-31 2000-06-06 Stmicroelectronics S.R.L. Protection circuit for an electric supply line in a semiconductor integrated device

Also Published As

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NL8100347A (nl) 1982-08-16
JPH0230584B2 (fr) 1990-07-06
AU550015B2 (en) 1986-02-27
EP0057024B1 (fr) 1984-11-21
IE820142L (en) 1982-07-26
US4697199A (en) 1987-09-29
CA1180468A (fr) 1985-01-02
AU7974182A (en) 1982-08-05
IE53096B1 (en) 1988-06-22
DE3261244D1 (en) 1985-01-03
JPS57143860A (en) 1982-09-06

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