EP0039736A4 - CONDUCTOR-INSULATION-SEMICONDUCTOR DEVICES AND THEIR MANUFACTURING METHOD. - Google Patents

CONDUCTOR-INSULATION-SEMICONDUCTOR DEVICES AND THEIR MANUFACTURING METHOD.

Info

Publication number
EP0039736A4
EP0039736A4 EP19800902383 EP80902383A EP0039736A4 EP 0039736 A4 EP0039736 A4 EP 0039736A4 EP 19800902383 EP19800902383 EP 19800902383 EP 80902383 A EP80902383 A EP 80902383A EP 0039736 A4 EP0039736 A4 EP 0039736A4
Authority
EP
European Patent Office
Prior art keywords
producing
same
semiconductor devices
conductor
isolator semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP19800902383
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0039736A1 (en
Inventor
Philip A Dalton Jr
Lowell Carles Bergstedt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of EP0039736A1 publication Critical patent/EP0039736A1/en
Publication of EP0039736A4 publication Critical patent/EP0039736A4/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
EP19800902383 1979-11-14 1980-11-12 CONDUCTOR-INSULATION-SEMICONDUCTOR DEVICES AND THEIR MANUFACTURING METHOD. Ceased EP0039736A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9412179A 1979-11-14 1979-11-14
US94121 2002-03-08

Publications (2)

Publication Number Publication Date
EP0039736A1 EP0039736A1 (en) 1981-11-18
EP0039736A4 true EP0039736A4 (en) 1983-04-06

Family

ID=22243186

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19800902383 Ceased EP0039736A4 (en) 1979-11-14 1980-11-12 CONDUCTOR-INSULATION-SEMICONDUCTOR DEVICES AND THEIR MANUFACTURING METHOD.

Country Status (3)

Country Link
EP (1) EP0039736A4 (enrdf_load_stackoverflow)
JP (1) JPS56501509A (enrdf_load_stackoverflow)
WO (1) WO1981001485A1 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049520A (en) * 1990-06-06 1991-09-17 Micron Technology, Inc. Method of partially eliminating the bird's beak effect without adding any process steps

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2137592A1 (enrdf_load_stackoverflow) * 1971-05-08 1972-12-29 Matsushita Electric Ind Co Ltd
FR2321194A1 (fr) * 1975-08-14 1977-03-11 Nippon Telegraph & Telephone Transistor a effet de champ a declencheur isole
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
DE2911726A1 (de) * 1978-03-27 1979-10-11 Ncr Co Halbleitervorrichtung und verfahren zu deren herstellung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1575741A (en) * 1977-01-17 1980-09-24 Philips Electronic Associated Integrated circuits
US4212683A (en) * 1978-03-27 1980-07-15 Ncr Corporation Method for making narrow channel FET
US4229755A (en) * 1978-08-15 1980-10-21 Rockwell International Corporation Fabrication of very large scale integrated circuits containing N-channel silicon gate nonvolatile memory elements

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2137592A1 (enrdf_load_stackoverflow) * 1971-05-08 1972-12-29 Matsushita Electric Ind Co Ltd
FR2321194A1 (fr) * 1975-08-14 1977-03-11 Nippon Telegraph & Telephone Transistor a effet de champ a declencheur isole
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
DE2911726A1 (de) * 1978-03-27 1979-10-11 Ncr Co Halbleitervorrichtung und verfahren zu deren herstellung

Also Published As

Publication number Publication date
JPS56501509A (enrdf_load_stackoverflow) 1981-10-15
WO1981001485A1 (en) 1981-05-28
EP0039736A1 (en) 1981-11-18

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE GB NL

17P Request for examination filed

Effective date: 19811017

DET De: translation of patent claims
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 19850204

RIN1 Information on inventor provided before grant (corrected)

Inventor name: BERGSTEDT, LOWELL CARLES

Inventor name: DALTON, PHILIP A., JR.