Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0135—Manufacturing their gate conductors
  • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0144—Manufacturing their gate insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• This invention relates generally to field effect semiconductor devices and methods for making such devices.
• IGFETs insulated gate field effect transistors
• the limit of resolution of such conventional photolithog- raphy is in the vicinity of about three microns, with a maximum mask alignment error of about one micron.
• Jones and Van Velthoven U.S. patent No. 4,212,683 issued July 15, 1980 and assigned to NCR Cor ⁇ poration discloses a method of fabricating low current depletion load devices (or other IGFET devices types) involving narrow (approximately 0.1 micron) device channels.
• narrow approximately stantially less than the minimum photolithographic feature size (e.g. the three microns mentioned above). The method taught in the Jones et al.
• Sefick and Jones U.S. Patent No. 4,145,233, issued March 20, 1979 to NCR Corporation discloses an alternative method for forming the same type of low current IGFET device as taught in the Jones et al. patent referred to above. The method disclosed in the Sefick et al.
• patent is the formation of a photoresist mask on a masking oxide layer disposed on the semicon- ductor substrate; overetching the oxide under the photoresist mask to produce an oxide mask aperture larger than the photoresist mask aperture; forming the central enhancement section by ion implantation through the photoresist mask aperture; removing the photoresist mask and performing a second ion implantation through the slightly larger oxide mask aperture to form narrow depletion channel regions flanking the central enhance ⁇ ment channel region; and then forming a single conduc ⁇ tor-insulator gate structure over both narrow channel regions and the central channel region.
• Fig. 1A Two low current devices 100 and 110 are shown formed side-by-side. The channel region only of each device is shown.
• Device 100 has a pair of low current channel regions 101 and 102 shown in dashed ' lines and a conduc ⁇ tive gate electrode 103 covering both channels.
• Device 110 has two low current channels 111 and 112 and a conductive gate electrode 113 covering both channels.
• the spacing between the two narrow channel regions of both devices 100 and 110 is shown to be three microns apart.
• the conductive gate electrodes 103 and 113 are shown to be the minimum of three microns apart.
• the width of the gate electrodes 103 and 113 must be about five microns to assure that complete coverage of the two narrow channel regions is provided in each device. Accordingly the overall dimensional width of the two devices 100 and 110 comprises thirteen microns.
• Fig. IB two devices 120 and 130 are shown as formed in accordance with the present invention.
• Device 120 has a single narrow channel region 121 covered by a conductive gate electrode 122.
• Device 130 has a single narrow channel region 131 covered by conductive gate electrode 132.
• the two conduc ⁇ tive gate electrodes are spaced by three microns and each conductive gate electrode is itself three microns wide.
• Fig. 1A is a schematic diagram of the geometry of a pair of low current IGFET devices formed in accord ⁇ ance with prior art techniques.
• the nitride and oxide layers are patterned using conventional photolith ⁇ ography to leave the nitride and oxide layers in active device regions of the semiconductor substrate 11. There ⁇ after a thick field oxide 16 is grown on the substrate, typically using a conventional wet oxidation process.
• the substrate outside the active device region 50 may be implanted with p-type impurities (e.g. boron) prior to growing thick field oxide 16 to assist in preventing the formation of parasitic transistor channels in the sub- strate under the thick field oxide 16.
• Figs. 8A and 8B the structure is depicted after a gate oxide layer 18 has been grown and a poly ⁇ silicon layer 19 has been deposited and doped to make it sufficiently conductive.
• the next step, as depicted in Figs. 9A and 9B, is to form a photoresist mask 36 over polysilicon layer 19 and to use mask 36 to form, in a partial manner, two separate gate electrode structures 19A and 19B, each overlying one of the narrow depletion channels 28A and 28B.
• Fig. 9C it will be seen that the structure at this point comprises a pair of strips of polysilicon 19A and 19B covering the narrow channel depletion regions 28A and 28B.
• Figs. 12A-16B and 12B-16B depict an alternative process for forming the pair of silicon gate structures overlying the narrow device channels 28A and 28B.
• This alternative process enables a simultaneous diffusion of source and drain regions and the gate electrodes by providing a thicker oxide layer 52 (shown in Fig. 14B) between the silicon gate electrodes 19A and 19B.
• This thicker oxide precludes any diffusion of dopant material into the substrate in the central enhancement channel section 27 during the source and drain diffusion step depicted in Figs. 16A and 16B.
• FIGs. 17A-19A and 17B-19B depict an alternative process of forming a pair of silicon gate structures overlying the narrow device channels 28A and 28B.
• This alternative process enables the production of a pair of devices having gate electrodes of a width more narrow than conventional photolithographic feature size such as is illustrated in Fig. IC.
• This alternative process utilizes special method steps, alternative ones of which are set forth in Owen U.S. Patent No. 4,026,740 and Nicholas U.S. Patent 4,124,933.
• this alternative process proceeds from the process steps shown in Figs.
• each of the narrow channels may have a- width of 0.05 to 0.1 micron as would be desired for low current depletion load devices, but could be used to form IGFET devices having any desired channel width less than conventional photolithographic feature size (about 3 microns).
• the exemplary processes described above could be employed in overall IC manufacturing processes wherein both depletion and enhancement type devices are formed on the same substrate. Some modification of the exemplary process steps disclosed above would be required in order to provide an overall process with that capability. For
• a pair of field effect transistors one having a narrow depletion channel and one having a narrow enhancement channel could be formed instead of two separate transistors of the same type. This could be accomplished by separately masking the two narrow channel regions and implanting only one at a time with appropriate dopants.

Landscapes

• Insulated Gate Type Field-Effect Transistor (AREA)
• Measuring Magnetic Variables (AREA)
• Investigating Or Analyzing Materials By The Use Of Magnetic Means (AREA)

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• 1980
  • 1980-11-12 JP JP50015780A patent/JPS56501509A/ja active Pending
  • 1980-11-12 EP EP19800902383 patent/EP0039736A4/en not_active Ceased
  • 1980-11-12 WO PCT/US1980/001523 patent/WO1981001485A1/en not_active Application Discontinuation

Patent Citations (3)

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