EP0020395A1 - Procede pour la fabrication de dispositifs semi-conducteurs - Google Patents

Procede pour la fabrication de dispositifs semi-conducteurs

Info

Publication number
EP0020395A1
EP0020395A1 EP79901089A EP79901089A EP0020395A1 EP 0020395 A1 EP0020395 A1 EP 0020395A1 EP 79901089 A EP79901089 A EP 79901089A EP 79901089 A EP79901089 A EP 79901089A EP 0020395 A1 EP0020395 A1 EP 0020395A1
Authority
EP
European Patent Office
Prior art keywords
substrate
semiconductor material
semiconductor
layer
monocrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP79901089A
Other languages
German (de)
English (en)
Inventor
Hanno Schaumburg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Intellectual Property and Standards GmbH
Original Assignee
Philips Corporate Intellectual Property GmbH
Philips Patentverwaltung GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Corporate Intellectual Property GmbH, Philips Patentverwaltung GmbH filed Critical Philips Corporate Intellectual Property GmbH
Publication of EP0020395A1 publication Critical patent/EP0020395A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/16Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58After-treatment
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58After-treatment
    • C23C14/5806Thermal treatment
    • C23C14/5813Thermal treatment using lasers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58After-treatment
    • C23C14/584Non-reactive treatment
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B1/00Single-crystal growth directly from the solid state
    • C30B1/02Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
    • C30B1/023Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing from solids with amorphous structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a method for producing semiconductor components with a polycrystalline or monocrystalline semiconductor material layer on a substrate.
  • the active semiconductor layer is applied to a substrate that is resistant to high temperatures, since, at least in the case of a monocrystalline semiconductor layer, this layer is applied to the substrate at high temperatures and because both the substrate and the further temperature treatments required for the production of semiconductor components , as well as the active semiconductor layer are heated to a high temperature in an oven.
  • the invention has for its object to design the method according to the preamble of claim 1, that the use of high temperature resistant substrates can be dispensed with, ie they can be replaced by less expensive materials.
  • substrates can be used which are not resistant to temperatures that are normally required for the application of, in particular, monocrystalline semiconductor material layers.
  • the method according to the invention also allows several layers of different doping and / or of different semiconductor material to be applied next to one another in a substrate, in which then semiconductor circuit elements with different properties can be produced.
  • a semiconductor material can also be used as the substrate.
  • FIG. 1 shows a substrate 1 made of aluminum doped with approximately 1% silicon, onto which an approximately 2 ⁇ m thick amorphous silicon layer 2 is sputtered.
  • the layer 2 can also be deposited on the substrate 1 from the gas phase at low temperatures.
  • the amorphous silicon layer 2 is then N-doped with arsenic by an ion implantation indicated by the arrow 3.
  • an intensive optical radiation is then directed onto the layer 2, which, thanks to a mask 5, remains limited to the two regions 21, in which the amorphous silicon is then locally heated by the optical radiation that it recrystallizes.
  • the radiation 4 is then moved over the surface of the regions 21 of the amorphous silicon layer 2 such that e.g. Form stripe-shaped, largely monocrystalline areas.
  • semiconductor circuit elements can then be produced by further method steps.
  • thermal treatments may be carried out which only heat the areas locally, since otherwise there is a risk that the parts of the layer 2 which have remained amorphous and thus insulating will likewise convert into polycrystalline or monocrystalline and thus conduct the material .
  • a substrate 1 made of aluminum with approximately 1% silicon is assumed, onto which approximately 2 ⁇ m thick layer 2 of amorphous silicon, which is weakly doped with boron, that is to say P-conducting, is deposited.
  • Arsenic is then introduced into this layer 2, as indicated by the arrow 3, by ion implantation, so that (see FIG. 4) an N + conductive zone 22 is formed on the surface of this layer.
  • the amorphous layer 2 is then converted into a polycrystalline silicon layer by an intensive optical radiation indicated by the arrow 4.
  • zone 22 then forms a PN junction with the rest of layer 2 and all PN junctions together form the solar cell.
  • a thin, radiation-permeable metal layer 6 is then vapor-deposited onto the surface of the layer 2, ie the zone 22.
  • the conductive substrate 1 and the metal layer 6 are then provided with connecting conductors 7.
  • a pulsed or continuously operated laser can, for example, be used as the source of the intensive optical radiation 3 in the exemplary embodiments described here.
  • a locally limited thermal treatment can also be carried out with the aid of a laser if semiconductor circuit elements whose production requires thermal treatment are to be produced in the monocrystalline regions (21, FIG. 2).
  • a material should always be used for the substrate 1 which does not yet form an alloy with the amorphous semiconductor material into a polycrystalline or monocrystalline semiconductor material.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thermal Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
  • Photovoltaic Devices (AREA)

Abstract

Pour realiser sur un substrat d'un dispositif a semi-conducteur une couche de materiau semi-conducteur (27) poly-ou monocristalline (une couche polycristalline dans le cas par exemple d'une cellule solaire), le materiau est depose sous forme amorphe sur le substrat par exemple vaporise, puis au moyen d'un traitement thermique par un rayonnement optique (4) applique sur le materiau, transforme en une couche poly- ou monocristalline.
EP79901089A 1978-08-30 1980-03-25 Procede pour la fabrication de dispositifs semi-conducteurs Withdrawn EP0020395A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19782837750 DE2837750A1 (de) 1978-08-30 1978-08-30 Verfahhren zum herstellen von halbleiterbauelementen
DE2837750 1978-08-30

Publications (1)

Publication Number Publication Date
EP0020395A1 true EP0020395A1 (fr) 1981-01-07

Family

ID=6048211

Family Applications (1)

Application Number Title Priority Date Filing Date
EP79901089A Withdrawn EP0020395A1 (fr) 1978-08-30 1980-03-25 Procede pour la fabrication de dispositifs semi-conducteurs

Country Status (3)

Country Link
EP (1) EP0020395A1 (fr)
DE (1) DE2837750A1 (fr)
WO (1) WO1980000510A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115341A (en) * 1979-02-28 1980-09-05 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
US4309225A (en) * 1979-09-13 1982-01-05 Massachusetts Institute Of Technology Method of crystallizing amorphous material with a moving energy beam
US4381201A (en) * 1980-03-11 1983-04-26 Fujitsu Limited Method for production of semiconductor devices
JPS56135969A (en) * 1980-03-27 1981-10-23 Fujitsu Ltd Manufacture of semiconductor device
EP0045551B1 (fr) * 1980-08-05 1984-10-31 L'Etat belge, représenté par le Secrétaire Général des Services de la Programmation de la Politique Scientifique Procédé de préparation de films polycristallins semi-conducteurs composés ou élémentaires et films ainsi obtenus
DE3816256A1 (de) * 1988-05-11 1989-11-23 Siemens Ag Verfahren zum herstellen einer aus einem ersten halbleitermaterial bestehenden einkristallinen schicht auf einem substrat aus einem andersartigen zweiten halbleitermaterial und verwendung der anordnung zur herstellung von optoelektronischen integrierten schaltungen
US9613805B1 (en) * 2015-12-11 2017-04-04 Infineon Technologies Ag Method for forming a semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3585088A (en) * 1968-10-18 1971-06-15 Ibm Methods of producing single crystals on supporting substrates
US3853648A (en) * 1972-08-14 1974-12-10 Material Sciences Corp Process for forming a metal oxide pattern
GB1393337A (en) * 1972-12-29 1975-05-07 Ibm Method of growing a single crystal film
US4059461A (en) * 1975-12-10 1977-11-22 Massachusetts Institute Of Technology Method for improving the crystallinity of semiconductor films by laser beam scanning and the products thereof
FR2390004A1 (en) * 1977-05-04 1978-12-01 Commissariat Energie Atomique Semiconductors, such as bipolar transistors - with amorphous layers locally crystallised by e.g. laser to reduce number of mfg. operations

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8000510A1 *

Also Published As

Publication number Publication date
DE2837750A1 (de) 1980-03-13
WO1980000510A1 (fr) 1980-03-20

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

AK Designated contracting states

Designated state(s): FR

18D Application deemed to be withdrawn

Effective date: 19801017

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SCHAUMBURG, HANNO