EP0013737A1 - Hiérarchie de mémoire à plusieurs étages pour un système de traitement des données - Google Patents

Hiérarchie de mémoire à plusieurs étages pour un système de traitement des données Download PDF

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Publication number
EP0013737A1
EP0013737A1 EP79105170A EP79105170A EP0013737A1 EP 0013737 A1 EP0013737 A1 EP 0013737A1 EP 79105170 A EP79105170 A EP 79105170A EP 79105170 A EP79105170 A EP 79105170A EP 0013737 A1 EP0013737 A1 EP 0013737A1
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EP
European Patent Office
Prior art keywords
memory
data
cash
register
main memory
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Granted
Application number
EP79105170A
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German (de)
English (en)
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EP0013737B1 (fr
Inventor
Anthony Joseph Capozzi
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Definitions

  • the invention relates to a multi-level memory hierarchy according to the preamble of claim 1.
  • the very fast processors of large data processing systems need ever larger and easily accessible storage systems.
  • the memory or at least part of the memory must operate at a speed which is quite close to that of the processors.
  • One solution to this problem is to use a two-tier or multi-tier memory hierarchy that includes a small first cash store and one or more large, relatively slower main stores.
  • the processor of the system communicates directly with the cash memory at essentially system speed. If data requested by the processor is not in the cash memory, it must be searched for in the main memory and transferred to the cash memory, where it generally replaces data blocks located there.
  • a typical multi-level storage system based on cash storage is described in US Pat. No. 3,896,419.
  • the system described uses a cash storage located in the processor as a table storage with fast access to data blocks previously fetched from the main storage.
  • no methods or processes for writing across a boundary from the channel to main memory are described in the system described.
  • the protocol does not allow partial writing beyond a double word limit, which limits the flexibility of the system.
  • Such operations are permitted in other systems, but all data mixes must be made in the cash store regardless of whether the addressed location is in the cash store or not.
  • the cash memory and generally also the central processing unit must be fully used during the write operation.
  • at least one page must be used in the cash memory that could otherwise be used for operation data.
  • the invention is therefore based on the object of providing a multi-stage memory system with improved operating speed and increased reliability for a data processing system with a memory controller Write operations over a double word boundary from channel to main memory are allowed to be accomplished to overcome the above-mentioned disadvantages of the prior art.
  • the two-stage storage system is equipped with an integrated controller for data transfer within the system.
  • the memory includes a relatively small, very fast cash memory for working with the processor at processor speed and a relatively large but slower main memory. If a channel is to be partially written into the main memory beyond a double word limit, it is first determined whether the address in the cash memory to which the data is to be written is located. When the address is in the cash store, the data from the channel is merged with the full page of data doublewords from the cash store in a data register and the updated mixed cash store page is then stored in main memory. At the same time, the page in the cash memory is invalidated.
  • the data is read from the channel via the IPU and data registers and stored in an overflow buffer (after that the IPU and the cash memory are free to perform other operations). Then the double words belonging to the partial writing are brought in from the main memory and stored in auxiliary registers in the memory system. Then they are mixed with the partial double words in the overflow buffer from the channel and the updated data is stored back in the main memory.
  • Figure 1 shows the data flow for a two-tier memory system incorporating the present invention.
  • the system basically consists of the main processor 11, which contains the instruction processing unit (IPU 13) and the connected channels 15.
  • a data path 17 connects the output of the IPU 13 to a cash memory 19.
  • a bidirectional data path 21 connects the IPU 13 to an EA data register 23.
  • Another bidirectional data path 25 connects the cash memory 19 and the EA data register 23.
  • Das EA data register 23 is connected to an overflow buffer 29 via a unidirectional data path 27 and to the error correction circuits 33, 33 via a bidirectional data path 31.
  • the overflow buffer 29 is connected to the error correction circuits 33 by a unidirectional data path 35.
  • the error correction circuits 33 are fed back to the EA data register 23 via the data path 31 and connected to the main memory 39 via a bidirectional data path 41. 1 therefore shows the general data paths that are permissible for data transmission between the various components of the system, in particular insofar as they are related to the present invention.
  • bits 2 through 12 would be the real address of a 2K page in memory
  • bits 13 through 17 would be a cash page address
  • bits 18 through 20 would be an eight byte row of a cash page
  • bits 21 through 23 Define bytes in a given line. The meaning of address division becomes clearer in connection with the description of the addressing device in connection with Fig. 4.
  • the main interest is bits 18 to 23, since each write operation from channel to memory is no longer than one page.
  • the system contains a processor directory lookup table (DLAT 102) and a channel directory lookup table 103.
  • the DLAT 102 contains in each entry a field for a virtual and for a real address as well as a polling and a status bit.
  • the channel search table 103 contains the entries for the virtual to the real address possibility of the channel.
  • the system also includes a key stack 105 with multiple entries that represent a given page in main memory 107.
  • the cash directory 109 contains several entries with multiple associative possibilities.
  • the cash directory 109 can e.g. Be as four-way associative and therefore the cash would - memory 111 four data areas contain.
  • Each area of cash memory 111 contains multiple cash memory pages and is addressed by the memory address register.
  • the system also includes a key checker 113, an input / output data register 115 and an overflow buffer 117.
  • the two components of the real address register 119 and 121 are referred to below as RA1 and RA2, respectively.
  • the controller also includes a comparator 123 and an error correction bit generator 125.
  • a main memory controller 127 and memory control register 129 provide for connection to the main memory 107.
  • Input / output data register 115 is described as an eight byte data transfer register that receives the processor data in a memory write operation and sends it to the processor in a memory read operation. The input / output data register 115 also moves the data between the circuit parts in the memory controller.
  • Error correction bit generator 125 provides proper parity on the data path between main memory 39 and cash memory 19.
  • Directory 109 and directory look-up tables 102 and 103 receive addresses via the memory address register. The addresses can be virtual or real.
  • RA1 register 119 and RA2 register 121 receive addresses from DLAT 102 and directory 109 and, in conjunction with the SAR register, address main memory 107 via memory control registers 129.
  • the cash memory directory 109 is addressed by the memory address register bits 13 through 17 and indicates a 64 byte page in the cash memory. Each entry contains an 11-bit real address and 3 status bits, one of which indicates the valid or invalid status, one of the modification status and one bit of the physical state of the cash storage entry. With four-way associativity, there are four cash storage pages in the.Cash memory 111, which belong to four different 2K pages.
  • the source of the real address is the real address fields from processor search table 102 or the memory address register through RA1 register 119.
  • the cash store directory indicates when the desired page is in cash store. If the real address can be found in the directory and its entry is valid, the data is in the cash memory. This is called a hit. If the real address is not in the directory or if its entry is invalid, then the data is not in the cash memory. This is known as a data error. In the event of an error, the main memory must be addressed in order to bring the desired data from there into the cash memory.
  • the 8K bit cash memory 111 is divided into four parts that define the four-way associativity with the directory 109. Each part of the cash memory contains 32 entries of 64 bytes each.
  • the cash memory receives data from the EA data register 115 and from the IPU data bus 135. The output from the cash memory goes to the EA data register 115. All four data areas of the cash memory are simultaneously from the memory address register with the SAR address bits 13 to 17 addressed which address the page component and with bits 18 to 20 which address the eight byte line component. A final selection is made by the associativity class from directory 109 in which the hit occurred.
  • the overflow buffer 117 stores only one page at a time and is used to buffer the page output from the cash memory in an output operation.
  • the buffer stores syndrome bits generated during main memory 107 fetch.
  • the syndrome bits are used to denote data corrected by the error correction bit generator 125 when reading from the memory.
  • the overflow buffer is also used to buffer channel data during partial memory operations. These double words, which are read out of the cash memory during a write operation before its content is changed, can be stored in a restart buffer, not shown.
  • the key stack 105 contains several entries, each of which represents a 2K page in memory. Each entry contains a memory protection key, an access protection bit and a reference bit as well as a change bit for the designated page.
  • the input for the key stack comes from the EA data collection line.
  • the output from the key stack 105 is compared to the signals on the key bus 137 or from the two key fields from the processor lookup table 102.
  • the key stack also receives an input from real address component 119, namely bits 2 through 12 thereof.
  • the main memory with a typical storage capacity of a few megabytes sends and receives data via the error correction bit generator 125.
  • data from the Main memory Based on inputs from the memory controller 127, from the real address units 119, 121 and from the memory address register, data from the Main memory selected. Data to and from main memory is transferred in eight byte units on an eight byte bi-directional data bus that connects error correction bit generator 125 to main memory.
  • inputs from the channel are always written directly to the main memory and invalidate an old cash memory page with the same address if it is in the cash memory at the time the channel is writing data to the main memory .
  • the processor Conversely, the processor always writes to the cash memory, which then possibly transfers data to the main memory.
  • the main memory clock and the channel clock thus generally run synchronously, for example with four pulses in a cycle time of 150 nsec.
  • the cash memory clock and the processor clock run together and can have a cycle of 4, 6 or 8 pulses.
  • the eight byte input / output data register 115 is used to move data to and from the processor / channel and memory.
  • the output of the data register can go to the cash memory input, the processor data collector, the overflow buffer (or restart buffer) and the error correction bit generator.
  • the data register can be loaded from the cash memory output, from the processor data bus, from the error correction bit generator, from the key group, from the restart buffer and from the overflow buffer.
  • the real address device consists of the RA1 register 119 and the RA2 register 121.
  • RA1 is loaded from the memory address register or from the real address fields of the directory search tables 102, 103.
  • RA2 is loaded from the real address entry from directory 109, which matches. If there is a hit in the DLAT and an error in the directory, the real address is moved from the RA1 register to the main memory 107 loaded and at the same time the SAR bits 13 to 17 are given to the main memory 107, the address bits from RA1 addressing a selected 2K side and bits 13 to 17 the selected 64 bytes (cash memory side).
  • the output from the real address component can also be given to the input of the directory for loading the real address, to the key stack for reading or storing the key and to the restart / overflow buffer to store real addresses.
  • FIG. 4 shows in detail the data traces that are traced from the channel to the main memory via the IPU during a write operation.
  • each bidirectional data path actually ends in a receiver / driver combination that is placed between the various devices.
  • the bidirectional path from the IPU for example to the system, goes on line 21 to the receiver / driver pair 201.
  • the output of R201 is then applied via gate 24 to cash memory 19 and data register 23.
  • the return path goes from the data register 23 via the driver 201 to the bidirectional path 21 and to the IPU 13.
  • the output from the data register 23 can also be sent through the gate circuit 24 to the cash memory 19.
  • a receiver / driver pair 203 connects the data register 23 and the overflow buffer 29 to the bi-directional path 31 which runs to the error correction circuits 33 which include a final driver / receiver pair 205.
  • Driver 203 receives inputs from the overflow buffer and data register 23 and provides an output to data register 23.
  • Receiver 205 provides an output to a memory data register 207, which in turn feeds error correction circuit 209.
  • the output from the error correction circuit 209 is passed to an error correction main register 211, which in turn feeds a subordinate error correction register 213.
  • the bidirectional highway 41 between The buffer 38 of the main memory 39 and the error correction circuits 33 ends in a receiver / driver pair 215.
  • the output from the subordinate error correction register 213 is applied to the driver 215, the output of which is returned to the memory data register 207.
  • Another output from the error correction main register 211 is given to a help register 217, the output of which is fed back to the memory data register 207.
  • Output from subordinate error correction register 213 is also applied to driver 205.
  • Cash memory 19 is an 8K byte four-way associativity memory in which each of the four sections contains 32 pages. Each page within the cash memory 19 contains 64 bytes, divided into eight different lines of cash memory. A double word consists of eight bytes and corresponds to a full line in a cash memory page.
  • the basic transfer includes a cash storage page, i. that is, 64 bytes of data transfer. For a full transfer of 64 bytes corresponding to a full cash memory page, when writing from the channel to the main memory 39 via the IPU, the data is written directly to the buffer 38 of the main memory 39 via the data register 23 and the error correction circuits 33, bypassing the overflow buffer 29 becomes.
  • the buffer 38 of the main memory 39 can e.g. B. be a full buffer of 64 bytes wide.
  • the channel data write command can include an operation of varying lengths from 1 to 64 bytes, there are variations in channel write other than full page writing. Such a variation exists e.g. B. from a partial write operation, the start and end addresses are on double word boundaries. In such a case, partial writes are loaded into the overflow buffer 29 via the data register 23 and then from there into the buffer 38 of the main memory 39 by the error correction circuits 33.
  • the more important aspect of the present invention comes into play when partial writing takes place beyond the double word limit, with either the addressed page being in the cash memory or not.
  • the entire page is read from the cash memory, mixed in the data register 23 with the partial data coming from the channel and loaded into the overflow buffer 29, from where it is fed into the buffer 38 of the main memory by the error correction circuit 33 39 is sent.
  • the mixed data from the data register 23 can also be sent directly into the memory by the error correction circuit 33.
  • a transmission space signal is raised at the appropriate time to synchronize the mixing of the channel data with the cash storage data. Since the cash memory is used to perform this mix, the IPU cannot continue the operation until the mix is complete and the IPU receives a ready signal.
  • the double words to be mixed must first be fetched from the main memory. Access to main memory begins while the channel data is loaded into the overflow buffer 29. In this case, the IPU receives the ready signal once the channel data are loaded into the overflow buffer 29, and then the IP U , channel and cash are free again to continue with other operations. The actual merging takes place in the error correction circuits 33 in connection with the overflow buffer 29 and the data register 23. This represents an essential advantage of the present invention, since (a) partial writes are permissible beyond double word limits and (b) most of the merging operation for data that are not in the cash storage can be carried out without the IPU being connected longer than necessary.
  • FIG. 5 An example of a write option from the channel into the main memory beyond a limit is described.
  • the example is given first when the data is in the cash memory and then when it is not in the cash memory.
  • the explanation is based on the start and end addresses shown in FIG. 5.
  • the addresses are based on the memory address register bits 18 through 23 and have the start address 011101 corresponding to double word 3, byte 5.
  • the end address is 110001 corresponding to double word 6, byte 1.
  • the location of these addresses is shown in Fig. 8, which is the equivalent a full cash store page, d. H. 64 bytes, comprising the eight double words O to 7, each double word having eight bytes of information.
  • the byte areas designated "X" refer to data that are not disturbed by the partial write operation of the channel and the "O" bytes designate data bytes that are part of the channel write operation.
  • the page that contains the data about the partial writing is in the cash memory.
  • a time sequence for this case is shown in FIG. 6 and is described in more detail in connection with the circuit diagram of FIG. 4.
  • the first signal is a memory occupancy signal represented by line F in Fig. 6. This signal is high for the full duration of the data transfer because the memory is occupied throughout the transfer. Since the data is in the cash memory, the entire cash memory page must be read from the cash memory, sent through the data register 23, where the partial write data from the channel is mixed below, and then stored in the overflow buffer until the entire cash memory page is selected. The overflow buffer is then unloaded and the data stored in memory. At the same time, the address corresponding to this cash storage page is invalidated.
  • the entire cash memory page must be read out because some data in this page may have been changed or updated during previous operations, ie the data in the main memory corresponding to this cash memory page is no longer valid. For this reason, the entire cash storage page must be updated and saved in the main storage.
  • the addressing of the data to be sent from the cash memory to the data register begins one clock cycle after the memory occupancy signal has been raised.
  • line B in FIG. 6 approximately three clock pulses after the first data address pulse has been raised, the first double word is read from the cash memory into the data register. Since this double word O cannot be mixed in the data register, it is transferred directly to the overflow buffer. This operation continues until the third subsequent system cycle, in which a channel warning pulse is sent, as shown by line C in FIG. 6, so that the channel gets ready to send its data.
  • a system cycle after sending the channel warning pulse the channel begins to send the data as shown by line D in Fig. 6, and the first data sent by the channel corresponds to the double word 3.
  • the next part of the operation is to unload the overflow buffer and write the data there to the main memory.
  • line A in FIG. 6 about 10 machine cycles are required for this, since the data must be passed through the receiver driver 203 to the driver receiver 205, through the memory data register 207, the error correction circuit 209 and the error correction main register 211.
  • the data is passed on through the subordinate error correction register 213, the receiver driver 215 and the bidirectional data bus 41 to the buffer 38 of the main memory 39.
  • the memory occupancy signal represented by the line F in FIG. 6 is dropped and a second IPU Ready pulse, represented by the line E, given.
  • this second ready pulse is only needed if a memory request has been received in the meantime. Such a memory request would be answered with an occupancy signal and the IPU would have to wait until it receives a ready pulse before it can get access to the memory again.
  • FIG. 7 show partial storage with the same start and end addresses as above, but here the page containing the data is not in the cash memory. Therefore, double word 3 and double word 6 of the corresponding page must first be fetched from the main memory so that the double words can be mixed completely as required. As shown in FIG. 7, only four double words, namely words 3 to 6, are affected by this operation, so that the time sequence has a further improvement compared to that shown in FIG. 6.
  • the memory allocation signal is raised again as the first signal.
  • the channel warning pulse is sent, as shown by line 10, Fig. 7, since data transmission is initially initiated by the channel because the cash memory is not being addressed. A machine cycle later the data transmission pulses are initiated, and shortly thereafter the first double word concerned is in the data register 23 as shown by line B in FIG. 7.
  • the main memory 39 was also addressed, the corresponding memory data was controlled and loaded into the main memory buffer 38.
  • the data is transferred from the channel to the overflow buffer 29. As shown by line D in FIG. 6, one cycle after the end of this transfer is given an IPU ready signal to enable the IPU, cash memory and other circuitry to perform other operations.
  • the overflow buffer 29 is loaded accordingly, the double words 3 and 6 are fetched from the main memory 39 in the eighth machine cycle, as shown by line A in FIG. 7. Since only two double words are brought before four more machine cycles are required because the D ouble words 4 and 5, although clocked, but not read. During this time, double word 3 is fetched from memory buffer 38 and placed in auxiliary register 217. The double word 6 is fetched from the buffer 38 and placed in the error correction main register 211. After this operation, starting approximately at the 13th machine cycle, the unloading of the overflow buffer 29 begins.
  • the double word 3 from the overflow buffer 29 and the double word 3 stored in the auxiliary buffer 217 are mixed in the memory data register 207 and then sent by the error correction circuit 209.
  • the double word 6 stored in the error correction main register 211 is transferred to the auxiliary register 217.
  • a subsequent operation continues with the transfer of the next double word 4 from the overflow buffer 29 through the receiver driver 203 to the driver receiver 205 and through the main memory data register 207. This operation continues until the double word 6 is used becomes. Then it is read out of the auxiliary register 217 and mixed with the double word 6 from the overflow buffer 29 in the main memory data register 207.
  • the memory takes approximately the same time to transfer data and discharge the buffer 38 as for the operation shown in FIG. Then, as represented by line E in FIG. 7, the memory occupancy signal is dropped. If a memory request has been received in the meantime, the system again generates another ready IPU pulse, as shown by line D in FIG. 7.

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EP79105170A 1979-01-26 1979-12-14 Hiérarchie de mémoire à plusieurs étages pour un système de traitement des données Expired EP0013737B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/006,980 US4298929A (en) 1979-01-26 1979-01-26 Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability
US6980 1979-01-26

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EP0013737A1 true EP0013737A1 (fr) 1980-08-06
EP0013737B1 EP0013737B1 (fr) 1983-01-12

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US (1) US4298929A (fr)
EP (1) EP0013737B1 (fr)
JP (1) JPS5821353B2 (fr)
AU (1) AU530891B2 (fr)
BR (1) BR8000314A (fr)
CA (1) CA1124888A (fr)
DE (1) DE2964509D1 (fr)
ES (1) ES487814A1 (fr)
IT (1) IT1165402B (fr)

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JPS5821353B2 (ja) 1983-04-28
JPS55101182A (en) 1980-08-01
CA1124888A (fr) 1982-06-01
DE2964509D1 (en) 1983-02-17
US4298929A (en) 1981-11-03
AU5386379A (en) 1980-07-31
EP0013737B1 (fr) 1983-01-12
IT7928240A0 (it) 1979-12-20
BR8000314A (pt) 1980-10-07
IT1165402B (it) 1987-04-22
AU530891B2 (en) 1983-08-04
ES487814A1 (es) 1980-09-16

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