EP0000909B1 - Transistor latéral - Google Patents

Transistor latéral Download PDF

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Publication number
EP0000909B1
EP0000909B1 EP78100655A EP78100655A EP0000909B1 EP 0000909 B1 EP0000909 B1 EP 0000909B1 EP 78100655 A EP78100655 A EP 78100655A EP 78100655 A EP78100655 A EP 78100655A EP 0000909 B1 EP0000909 B1 EP 0000909B1
Authority
EP
European Patent Office
Prior art keywords
region
base
collector
transistor
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78100655A
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German (de)
English (en)
Other versions
EP0000909A1 (fr
Inventor
Harlan Rogene Gates
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0000909A1 publication Critical patent/EP0000909A1/fr
Application granted granted Critical
Publication of EP0000909B1 publication Critical patent/EP0000909B1/fr
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0821—Combination of lateral and vertical transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Definitions

  • the invention relates to a lateral transistor according to the first part of claim 1, which can be produced in particular integrated together with complementary vertical transistors.
  • Lateral transistors in conjunction with complementary vertical transistors are used, for example, in the known 1 2 L structures (Integrated Injection Logic).
  • a complementary vertical transistor is also integrated in a lateral transistor, the collector zone of the lateral transistor being in position and of the base zone of the vertical transistor Corresponds to the type of conduction, and in which the emitter zone is introduced into the base zone of the vertical transistor.
  • the tolerances in the thickness of the epitaxial layer have an unfavorable effect on the properties of both the vertical and the lateral transistor, since the base zone of the vertical transistor is formed by the epitaxial layer itself and the intrinsic base zone of the lateral transistor by the entire thickness the collector zone comprising the epitaxial layer is determined.
  • the invention seeks to remedy this.
  • the invention as characterized in the claims, achieves the object of specifying a lateral transistor which can be produced with complementary, vertical transistors with the smallest space requirement and optimal properties, the base zone, the collector zone and the emitter zone of the lateral transistor in this Order are compatible with the collector contacting zone, the base zone and the base connection zone of the vertical transistor and in particular a defined base width of the lateral transistor can be achieved.
  • the invention can be seen essentially in that the
  • Epitaxial layer has the first conduction type, that the collector zone in the surface of the epitaxial layer is arranged at a distance from the sub-base zone and that the base zone extends through the collector zone which partially surrounds it and the epitaxial layer extends into the sub-base zone so that the active intrinsic base zone extends through the side faces the emitter zone and the collector zone (44) is defined.
  • Particular embodiments of the invention are characterized in the subclaims.
  • the sub-base zone serves for the low-resistance electrical connection of the base zone, the epitaxial layer being regarded as an extrinsic base zone, via which the active intrinsic base zone is connected to the surface.
  • the emitter zone is introduced into the base zone with the aid of the same mask window, preferably by implantation.
  • This double-diffused base-emitter structure enables an exact base width of the intrinsic base of the lateral transistor to be maintained. In this way, a lateral PNP transistor having optimal properties and a vertical NPN transistor also having optimal properties can be integrated in the same semiconductor body, the feature of the self-alignment of the zones with one another being ensured.
  • the figures 1 a to 1 i essentially sectional views of the structure of the exemplary embodiment in successive method steps.
  • a lateral PNP transistor according to the invention is produced simultaneously with a vertical NPN transistor.
  • a silicon dioxide layer 12 is first applied to the epitaxial layer, and a silicon nitride layer 14 is applied above it.
  • FIG. 1 b all mask windows 18, 20, 22, 24, 26 and 28 are etched into the silicon nitride layer 14 using an etching mask 16 made of photoresist.
  • the top view of this etching mask is shown in Fig. 1 c.
  • the windows in the area of which the silicon dioxide layer 12 is to be etched are defined with the aid of a blocking mask 50 made of photoresist.
  • the N-type contacting zones 34 and 36 to the N + -doped buried zones 6 and 8 and the base zone 36 of the lateral transistor are formed by implantation of, for example, phosphorus.
  • Low-resistance N-doped resistors (75 ohms / unit area) can be formed at the same time. The implantation is carried out with low energy, so that the mask windows 18, 20 and 28 defined by the silicon dioxide layer and the silicon nitride layer define the doped zones produced in the process.
  • 18, 20 and 28 oxide layers are formed in the area of these windows, which have a somewhat smaller thickness than the original silicon dioxide layer 12.
  • the N-doped zones 34, 36 and 38 diffuse further into the epitaxial layer 4, so that they meet with the diffusing buried zones 6 and 8.
  • the silicon dioxide layer 41 is only slightly reinforced in the area of the windows 22, 24 and 26, so that there is a braking effect for the ions which corresponds to that of the silicon dioxide layer 12 including the silicon nitride layer 14.
  • 1 e shows how the base zone 40 of the vertical NPN transistor, the collector zone 44 of the lateral PNP transistor and the upper isolation zones 42 are introduced using a photoresist mask.
  • the P-doped zones 40 and 44 have a high sheet resistance (1000 ohms / unit area), so that there is a low emitter base capacitance for the vertical NPN transistor and a high collector base breakdown voltage for the lateral PNP transistor. These zones are also suitable for realizing resistances.
  • all mask windows 18, 20, 22, 24, 26 and 28 are etched through the silicon dioxide layer 39, 41 using the silicon nitride layer 14 as an etching mask. No separate mask is required for this etching step.
  • FIG. 1 shows the top view of the mask windows 18, 20, 22, 24, 26 and 28 defined by the silicon nitride layer 14 in the silicon dioxide layer.
  • a heating process is carried out in which the implanted regions are activated and the N + and P + -doped zones are diffused out to their final depth.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Claims (6)

1. Transistor latéral dans lequel une couche épitaxique (4) est placée sur une région de sous-base (6) enterrée, fortement dopée, d'un premier type de conductivité, une région de collecteur (44) du second type de conductivité est placée sur la région de sous-base (6), une région de base du premier type de conductivité qui pénètre dans la région de sous-base (6) a été introduite au moyen d'un masque dans la région de collecteur, une région d'émetteur (62) du second type de conductivité a été introduite au moyen du même masque dans la région de base (36), et dans lequel la région de sous-base (6) s'étend latéralement jusqu'à la surface de la couche épitaxique (4) à travers une région de connexion à la base (34) du premier type de conductivité, caractérisé en ce que: la couche épitaxique (4) est du premier type de conductivité, la région de collecteur (44) se trouve dans la surface de la couche épitaxique (4), espacée de la région de sous-base (6), et la région de base (36) pénètre, à travers la région de collecteur (44) l'entourant partiellement, et à travers la couche épitaxique (4), jusque dans la région de sous-base de sorte que la région de base active, intrinsèque est définie par les côtés latéraux de la région d'émetteur (62) et la région de collecteur (44).
2. Transistor latéral selon la revendication 1, caractérisé en ce qu'une région de contact de collecteur (60) du second type de conductivité est placée dans la région de collecteur (44), latéralement par rapport à la région de base (36).
3. Transistor latéral selon l'une quelconque des revendications 1 ou 2, caractérisé en ce qu'une région de contact de base du premier type de conductivité est placée dans la région de connexion à la base (34).
4. Transistor latéral selon les revendications 1 à 3, caractérisé en ce qu'un transistor vertical, complémentaire à celui-ci, est intégré avec lui, les régions suivantes se correspondant quant à la position et au type de conductivité: la région de sous-base (6) du transistor latéral et la région de sous-collecteur (8) du transistor vertical, la région de collecteur (44) du transistor latéral et la région de base (40) du transistor vertical, la région de connexion à la base (34) du transistor latéral et la région de connexion au collecteur (38) du transistor vertical, et que la région d'émetteur (54) du transistor vertical est placée dans la région de base (44) de celui-ci.
5. Transistor latéral selon la revendication 4, caractérisé en ce que la région de contact de base (70) du transistor vertical est produite en même temps que la région d'émetteur (54) du transistor vertical.
6. Transistor latéral selon l'une quelconque des revendications 4 ou 5, caractérisé en ce que la région de contact de collecteur (60) du transistor latéral correspond, quant à la position et au type de conductivité, à la région de contact de base (68) du transistor vertical.
EP78100655A 1977-08-31 1978-08-16 Transistor latéral Expired EP0000909B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US830222 1977-08-31
US05/830,222 US4180827A (en) 1977-08-31 1977-08-31 NPN/PNP Fabrication process with improved alignment

Publications (2)

Publication Number Publication Date
EP0000909A1 EP0000909A1 (fr) 1979-03-07
EP0000909B1 true EP0000909B1 (fr) 1981-07-22

Family

ID=25256566

Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100655A Expired EP0000909B1 (fr) 1977-08-31 1978-08-16 Transistor latéral

Country Status (6)

Country Link
US (1) US4180827A (fr)
EP (1) EP0000909B1 (fr)
JP (1) JPS5438775A (fr)
CA (1) CA1118909A (fr)
DE (1) DE2860860D1 (fr)
IT (1) IT1109971B (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4283236A (en) * 1979-09-19 1981-08-11 Harris Corporation Method of fabricating lateral PNP transistors utilizing selective diffusion and counter doping
EP0093304B1 (fr) * 1982-04-19 1986-01-15 Matsushita Electric Industrial Co., Ltd. Circuit intégré semi-conducteur et son procédé de fabrication
US4492008A (en) * 1983-08-04 1985-01-08 International Business Machines Corporation Methods for making high performance lateral bipolar transistors
GB2148589B (en) * 1983-10-18 1987-04-23 Standard Telephones Cables Ltd Improvements in intergrated circuits
US6091884A (en) * 1991-08-19 2000-07-18 Index Systems, Inc. Enhancing operations of video tape cassette players
JPH09306924A (ja) * 1996-03-15 1997-11-28 Toshiba Corp 半導体装置の製造方法
US6551869B1 (en) * 2000-06-09 2003-04-22 Motorola, Inc. Lateral PNP and method of manufacture
US20060148188A1 (en) * 2005-01-05 2006-07-06 Bcd Semiconductor Manufacturing Limited Fabrication method for bipolar integrated circuits
KR100783278B1 (ko) * 2006-08-31 2007-12-06 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
US8791546B2 (en) * 2010-10-21 2014-07-29 Freescale Semiconductor, Inc. Bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3873989A (en) * 1973-05-07 1975-03-25 Fairchild Camera Instr Co Double-diffused, lateral transistor structure
JPS5155676A (en) * 1974-11-11 1976-05-15 Fujitsu Ltd Handotaisochino seizohoho
US4058419A (en) * 1974-12-27 1977-11-15 Tokyo Shibaura Electric, Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4054900A (en) * 1974-12-27 1977-10-18 Tokyo Shibaura Electric Co., Ltd. I.I.L. with region connecting base of double diffused injector to substrate/emitter of switching transistor
FR2337433A1 (fr) * 1975-12-29 1977-07-29 Tokyo Shibaura Electric Co Dispositif a semi-conducteur

Also Published As

Publication number Publication date
CA1118909A (fr) 1982-02-23
EP0000909A1 (fr) 1979-03-07
DE2860860D1 (de) 1981-10-29
IT1109971B (it) 1985-12-23
US4180827A (en) 1979-12-25
JPS5438775A (en) 1979-03-23
IT7826395A0 (it) 1978-08-02

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