EP0000909B1 - Lateral transistor - Google Patents

Lateral transistor Download PDF

Info

Publication number
EP0000909B1
EP0000909B1 EP78100655A EP78100655A EP0000909B1 EP 0000909 B1 EP0000909 B1 EP 0000909B1 EP 78100655 A EP78100655 A EP 78100655A EP 78100655 A EP78100655 A EP 78100655A EP 0000909 B1 EP0000909 B1 EP 0000909B1
Authority
EP
European Patent Office
Prior art keywords
region
base
collector
transistor
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78100655A
Other languages
German (de)
French (fr)
Other versions
EP0000909A1 (en
Inventor
Harlan Rogene Gates
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0000909A1 publication Critical patent/EP0000909A1/en
Application granted granted Critical
Publication of EP0000909B1 publication Critical patent/EP0000909B1/en
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0821—Combination of lateral and vertical transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Definitions

  • the invention relates to a lateral transistor according to the first part of claim 1, which can be produced in particular integrated together with complementary vertical transistors.
  • Lateral transistors in conjunction with complementary vertical transistors are used, for example, in the known 1 2 L structures (Integrated Injection Logic).
  • a complementary vertical transistor is also integrated in a lateral transistor, the collector zone of the lateral transistor being in position and of the base zone of the vertical transistor Corresponds to the type of conduction, and in which the emitter zone is introduced into the base zone of the vertical transistor.
  • the tolerances in the thickness of the epitaxial layer have an unfavorable effect on the properties of both the vertical and the lateral transistor, since the base zone of the vertical transistor is formed by the epitaxial layer itself and the intrinsic base zone of the lateral transistor by the entire thickness the collector zone comprising the epitaxial layer is determined.
  • the invention seeks to remedy this.
  • the invention as characterized in the claims, achieves the object of specifying a lateral transistor which can be produced with complementary, vertical transistors with the smallest space requirement and optimal properties, the base zone, the collector zone and the emitter zone of the lateral transistor in this Order are compatible with the collector contacting zone, the base zone and the base connection zone of the vertical transistor and in particular a defined base width of the lateral transistor can be achieved.
  • the invention can be seen essentially in that the
  • Epitaxial layer has the first conduction type, that the collector zone in the surface of the epitaxial layer is arranged at a distance from the sub-base zone and that the base zone extends through the collector zone which partially surrounds it and the epitaxial layer extends into the sub-base zone so that the active intrinsic base zone extends through the side faces the emitter zone and the collector zone (44) is defined.
  • Particular embodiments of the invention are characterized in the subclaims.
  • the sub-base zone serves for the low-resistance electrical connection of the base zone, the epitaxial layer being regarded as an extrinsic base zone, via which the active intrinsic base zone is connected to the surface.
  • the emitter zone is introduced into the base zone with the aid of the same mask window, preferably by implantation.
  • This double-diffused base-emitter structure enables an exact base width of the intrinsic base of the lateral transistor to be maintained. In this way, a lateral PNP transistor having optimal properties and a vertical NPN transistor also having optimal properties can be integrated in the same semiconductor body, the feature of the self-alignment of the zones with one another being ensured.
  • the figures 1 a to 1 i essentially sectional views of the structure of the exemplary embodiment in successive method steps.
  • a lateral PNP transistor according to the invention is produced simultaneously with a vertical NPN transistor.
  • a silicon dioxide layer 12 is first applied to the epitaxial layer, and a silicon nitride layer 14 is applied above it.
  • FIG. 1 b all mask windows 18, 20, 22, 24, 26 and 28 are etched into the silicon nitride layer 14 using an etching mask 16 made of photoresist.
  • the top view of this etching mask is shown in Fig. 1 c.
  • the windows in the area of which the silicon dioxide layer 12 is to be etched are defined with the aid of a blocking mask 50 made of photoresist.
  • the N-type contacting zones 34 and 36 to the N + -doped buried zones 6 and 8 and the base zone 36 of the lateral transistor are formed by implantation of, for example, phosphorus.
  • Low-resistance N-doped resistors (75 ohms / unit area) can be formed at the same time. The implantation is carried out with low energy, so that the mask windows 18, 20 and 28 defined by the silicon dioxide layer and the silicon nitride layer define the doped zones produced in the process.
  • 18, 20 and 28 oxide layers are formed in the area of these windows, which have a somewhat smaller thickness than the original silicon dioxide layer 12.
  • the N-doped zones 34, 36 and 38 diffuse further into the epitaxial layer 4, so that they meet with the diffusing buried zones 6 and 8.
  • the silicon dioxide layer 41 is only slightly reinforced in the area of the windows 22, 24 and 26, so that there is a braking effect for the ions which corresponds to that of the silicon dioxide layer 12 including the silicon nitride layer 14.
  • 1 e shows how the base zone 40 of the vertical NPN transistor, the collector zone 44 of the lateral PNP transistor and the upper isolation zones 42 are introduced using a photoresist mask.
  • the P-doped zones 40 and 44 have a high sheet resistance (1000 ohms / unit area), so that there is a low emitter base capacitance for the vertical NPN transistor and a high collector base breakdown voltage for the lateral PNP transistor. These zones are also suitable for realizing resistances.
  • all mask windows 18, 20, 22, 24, 26 and 28 are etched through the silicon dioxide layer 39, 41 using the silicon nitride layer 14 as an etching mask. No separate mask is required for this etching step.
  • FIG. 1 shows the top view of the mask windows 18, 20, 22, 24, 26 and 28 defined by the silicon nitride layer 14 in the silicon dioxide layer.
  • a heating process is carried out in which the implanted regions are activated and the N + and P + -doped zones are diffused out to their final depth.

Description

Die Erfindung betrifft einen lateralen Transistor gemäß dem ersten Teil des Anspruchs 1, der sich insbesondere zusammen mit komplementären vertikalen Transistoren integriert herstellen läßt.The invention relates to a lateral transistor according to the first part of claim 1, which can be produced in particular integrated together with complementary vertical transistors.

Laterale Transistoren in Verbindung mit komplementären vertikalen Transistoren werden beispielsweise in den bekannten 12L-Strukturen (Integrated Injection Logic) verwendet.Lateral transistors in conjunction with complementary vertical transistors are used, for example, in the known 1 2 L structures (Integrated Injection Logic).

Beispielsweise ist in der Veröffentlichung "IEEE Solid State Conference", 1976, von Y. Tokumaru, et al., unter dem Titel "12L with Self-Aligned Double Diffused Injector" auf den Seiten 100 und 101 eine Struktur mit einem lateralen PNP-Transistor und einem vertikalen NPN-Transistor beschrieben, die in einer P-dotierten Epitaxieschicht gebildet sind. Die Basiszone des NPN-Transistors wird dabei durch die Epitaxieschicht selbst gebildet. Hierbei handelt es sich um eine typische, kostengünstige, keine optimale Eigenschaften aufweisende bipolare Struktur, bei der sich die relativ großen Toleranzen in der Dicke der Epitaxieschicht und damit die großen Schwankungen in den Eigenschaften des vertikalen NPN-Transistors ungünstig auswirken.For example, in the publication "IEEE Solid State Conference", 1976, by Y. Tokumaru, et al., Entitled "1 2 L with Self-Aligned Double Diffused Injector" on pages 100 and 101, there is a structure with a lateral PNP -Transistor and a vertical NPN transistor described, which are formed in a P-doped epitaxial layer. The base zone of the NPN transistor is formed by the epitaxial layer itself. This is a typical, inexpensive, non-optimal bipolar structure in which the relatively large tolerances in the thickness of the epitaxial layer and thus the large fluctuations in the properties of the vertical NPN transistor have an unfavorable effect.

Aus der FR-A-2 337 433 ist es über den ersten Teil des Anspruchs 1 hinaus bekannt, daß bei einem lateralen Transistor ein zu ihm komplimentärer, vertikaler Transistor mitintegriert ist, wobei die Kollektorzone des lateralen Transistors der Basiszone des vertikalen Transistors in Lage und Leitungstyp entspricht, und bei dem in die Basiszone des vertikalen Transistors dessen Emitterzone eingebracht ist.From FR-A-2 337 433 it is known beyond the first part of claim 1 that a complementary vertical transistor is also integrated in a lateral transistor, the collector zone of the lateral transistor being in position and of the base zone of the vertical transistor Corresponds to the type of conduction, and in which the emitter zone is introduced into the base zone of the vertical transistor.

Auch hier wirken sich die Toleranzen in der Dicke der Epitaxieschicht auf die Eigenschaften sowohl des vertikalen als auch des lateralen Transistors ungünstig aus, da die Basiszone des vertikalen Transistors durch die Epitaxieschicht selbst gebildet wird und die intrinsische Basiszone des lateralen Transistors durch die ebenfalls die gesamte Dicke der Epitaxieschicht umfassende Kollektorzone bestimmt wird.Here, too, the tolerances in the thickness of the epitaxial layer have an unfavorable effect on the properties of both the vertical and the lateral transistor, since the base zone of the vertical transistor is formed by the epitaxial layer itself and the intrinsic base zone of the lateral transistor by the entire thickness the collector zone comprising the epitaxial layer is determined.

Hier will die Erfindung Abhilfe schaffen. Die Erfindung, wie sie in den Ansprüchen gekennzeichnet ist, löst die Aufgabe, einen lateralen Transistor anzugeben, der bei kleinstem Flächenbedarf und optimalen Eigenschaften gleichzeitig mit komplementären, vertikalen Transistoren herstellbar ist, wobei die Basiszone, die Kollektorzone und die Emitterzone des lateralen Transistors in dieser Reihenfolge mit der Kollektorkontaktierungszone, der Basiszone und der Basisanschlußzone des vertikalen Transistors kompatibel sind und insbesondere eine definierte Basisweite des lateralen Transistors erzielbar ist.The invention seeks to remedy this. The invention, as characterized in the claims, achieves the object of specifying a lateral transistor which can be produced with complementary, vertical transistors with the smallest space requirement and optimal properties, the base zone, the collector zone and the emitter zone of the lateral transistor in this Order are compatible with the collector contacting zone, the base zone and the base connection zone of the vertical transistor and in particular a defined base width of the lateral transistor can be achieved.

Zusammenfassend kann die Erfindung im wesentlichen darin gesehen werden, daß dieIn summary, the invention can be seen essentially in that the

Epitaxieschicht den ersten Leitungstyp aufweist, daß die Kollektorzone in der Oberfläche der Epitaxieschicht von der Subbasiszone beabstandet angeordnet ist und daß sich die Basiszone durch die sie teilweise umgebende Kollektorzone und die Epitaxieschicht hindurch bis in die Subbasiszone erstreckt, so daß die aktive intrinsische Basiszone durch die Seitenflächen der Emitterzone und der Kollektorzone (44) definiert ist. Besondere Ausführungsarten der Erfindung sind in den Unteransprüchen gekennzeichnet.Epitaxial layer has the first conduction type, that the collector zone in the surface of the epitaxial layer is arranged at a distance from the sub-base zone and that the base zone extends through the collector zone which partially surrounds it and the epitaxial layer extends into the sub-base zone so that the active intrinsic base zone extends through the side faces the emitter zone and the collector zone (44) is defined. Particular embodiments of the invention are characterized in the subclaims.

Die Subbasiszone dient dem niederohmigen elektrischen Anschluß der Basiszone, wobei die Epitaxieschicht als extrinsische Basiszone anzusehen ist, über die der Anschluß der aktiven intrinsischen Basiszone zur Oberfläche erfolgt. In die Basiszone wird mit Hilfe desselben Maskenfensters die Emitterzone, vorzugsweise durch Implantation eingebracht. Diese doppeltdiffundierte Basis-Emitterstruktur ermöglicht die Einhaltung einer genauen Basisweite der intrinsischen Basis des lateralen Transistors. Auf diese Weise läßt sich ein optimale Eigenschaften aufweisender lateraler PNP-Transistor mit einem ebenfalls optimale Eigenschaften aufweisenden vertikalen NPN-Transistor in dem gleichen Halbleiterkörper integrieren, wobei das Merkmal der Selbstausrichtung der Zonen zueinander gewährleistet wird.The sub-base zone serves for the low-resistance electrical connection of the base zone, the epitaxial layer being regarded as an extrinsic base zone, via which the active intrinsic base zone is connected to the surface. The emitter zone is introduced into the base zone with the aid of the same mask window, preferably by implantation. This double-diffused base-emitter structure enables an exact base width of the intrinsic base of the lateral transistor to be maintained. In this way, a lateral PNP transistor having optimal properties and a vertical NPN transistor also having optimal properties can be integrated in the same semiconductor body, the feature of the self-alignment of the zones with one another being ensured.

Im folgenden wird die Erfindung anhand von lediglich ein Ausführungsbeispiel darstellenden Zeichnungen näher erläutert.In the following, the invention is explained in more detail with reference to drawings showing only one embodiment.

Es zeigen die Fign. 1 a bis 1 i im wesentlichen Schnittansichten der Struktur des Ausführungsbeispiels in aufeinanderfolgenden Verfahrensschritten.The figures 1 a to 1 i essentially sectional views of the structure of the exemplary embodiment in successive method steps.

Hergestellt wird ein erfindungsgemäßer lateraler PNP-Transistor gleichzeitig mit einem vertikalen NPN-Transistor.A lateral PNP transistor according to the invention is produced simultaneously with a vertical NPN transistor.

Wie in Fig. 1 a dargestellt werden zunächst konventionelle Maskierungsprozesse, Dotierungsprozesse (Diffusion oder lonenimplantation) und Beschichtungstechniken angewandt, um N+-dotierte vergrabene Zonen 6 und 8 und P+-dotierte vergrabene Zonen 10 in der Grenzschicht zwischen einem Substrat 2 und einer darauf aufgebrachten N--dotierten Epitaxieschicht 4 zu bilden. Auf die Epitaxieschicht ist zunächst eine Siliziumdioxidschicht 12 und darüber eine Siliziumnitridschicht 14 aufgebracht.As shown in FIG. 1 a, conventional masking processes, doping processes (diffusion or ion implantation) and coating techniques are first applied to N + -doped buried zones 6 and 8 and P + -doped buried zones 10 in the boundary layer between a substrate 2 and one thereon applied N-doped epitaxial layer 4 to form. A silicon dioxide layer 12 is first applied to the epitaxial layer, and a silicon nitride layer 14 is applied above it.

In Fig. 1b sind unter Verwendung einer Ätzmaske 16 aus Fotolack sämtliche Maskenfenster 18, 20, 22, 24, 26 und 28 in die Siliziumnitridschicht 14 geätzt. Die Draufsicht dieser Ätzmaske ist in Fig. 1 c dargestellt.In FIG. 1 b, all mask windows 18, 20, 22, 24, 26 and 28 are etched into the silicon nitride layer 14 using an etching mask 16 made of photoresist. The top view of this etching mask is shown in Fig. 1 c.

Wie aus Fig. 1 d zu ersehen, werden mit Hilfe einer Sperrmaske 50 aus Fotolack die Fenster definiert, in deren Bereich die Siliziumdioxidschicht 12 zu ätzen ist. In den dabei entstehenden Fenstern werden durch Implantation von beispielsweise Phosphor die N-leitenden Kontaktierungszonen 34 und 36 zu den N+- dotierten vergrabenen Zonen 6 und 8 und die Basiszone 36 des lateralen Transistors gebildet. Dabei können gleichzeitig niederohmige N-dotierte Widerstände (75 Ohm/Flächeneinheit) gebildet werden. Die Implantation erfolgt mit niedriger Energie, so daß die durch die Siliziumdioxidschicht und die Siliziumnitridschicht definierten Maskenfenster 18, 20 und 28 die dabei erzeugten dotierten Zonen definieren. In einem nachfolgenden Reoxydationsprozeß werden im Bereich dieser Fenster 18, 20 und 28 Oxydschichten gebildet, die eine etwas geringere Dicke aufweisen als die ursprüngliche Siliziumdioxidschicht 12. Dabei diffundieren die N-dotierten Zonen 34, 36 und 38 weiter in die Epitaxieschicht 4 ein, so daß sie sich mit den ausdiffundierenden vergrabenen Zonen 6 und 8 treffen. Bei diesem Reoxydationsprozeß wird die Siliziumdioxydschicht 41 im Bereich der Fenster 22, 24 und 26 nur geringfügig verstärkt, so daß sich dort eine Bremswirkung für die Ionen ergibt, die der der Siliziumdioxidschicht 12 einschließlich der Siliziumnitridschicht 14 entspricht.As can be seen from FIG. 1 d, the windows in the area of which the silicon dioxide layer 12 is to be etched are defined with the aid of a blocking mask 50 made of photoresist. In the ent standing windows, the N-type contacting zones 34 and 36 to the N + -doped buried zones 6 and 8 and the base zone 36 of the lateral transistor are formed by implantation of, for example, phosphorus. Low-resistance N-doped resistors (75 ohms / unit area) can be formed at the same time. The implantation is carried out with low energy, so that the mask windows 18, 20 and 28 defined by the silicon dioxide layer and the silicon nitride layer define the doped zones produced in the process. In a subsequent reoxidation process, 18, 20 and 28 oxide layers are formed in the area of these windows, which have a somewhat smaller thickness than the original silicon dioxide layer 12. The N-doped zones 34, 36 and 38 diffuse further into the epitaxial layer 4, so that they meet with the diffusing buried zones 6 and 8. In this reoxidation process, the silicon dioxide layer 41 is only slightly reinforced in the area of the windows 22, 24 and 26, so that there is a braking effect for the ions which corresponds to that of the silicon dioxide layer 12 including the silicon nitride layer 14.

Aus Fig. 1 e ist zu ersehen, wie unter Verwendung einer Sperrmaske aus Fotolack die Basiszone 40 des vertikalen NPN-Transistors, die Kollektorzone 44 des lateralen PNP-Transistors und die oberen Isolationszonen 42 eingebracht werden. Die Implantation von beispielsweise Bor erfolgt durch die Siliziumdioxidschichten 39, 41 bzw. 12 und die Siliziumnitridschicht 14. Es ist darauf hinzuweisen, daß die Zonen 40 und 44 irhre zugeordneten Anschlußfenster 24 und 22 nicht zu überlappen brauchen und daß ihre Überschneidung mit den Kontaktierungszonen 38 und 34 unkritisch ist, da die P-dotierten Zonen 40 und 44 durch die N-dotierten Zonen 38 und 34 kompensiert werden. Ist man bestrebt, geringe Kapazitäten zwischen diesen P-und N-dotierten Zonen 40, 38 und 44, 34 zu erzielen, so können sie in einem Abstand zueinander angeordnet werden, was zu einer leichten Erhöhung des Flächenbedarfs führt. Die P-dotierten Zonen 40 und 44 weisen einen hohen Schichtwiderstand (1000 Ohm/Flächeneinheit) auf, so daß sich eine niedrige Emitter-Basiskapazität für den vertikalen NPN-Transistor und eine hohe Kollektor-Basis-Durchbruchsspannung für den lateralen PNP-Transistor ergibt. Diese Zonen sind außerdem geeignet, Widerstände zu verwirklichen.1 e shows how the base zone 40 of the vertical NPN transistor, the collector zone 44 of the lateral PNP transistor and the upper isolation zones 42 are introduced using a photoresist mask. The implantation of boron, for example, takes place through the silicon dioxide layers 39, 41 and 12 and the silicon nitride layer 14. It should be pointed out that the zones 40 and 44 do not need to overlap their associated connection windows 24 and 22 and that their overlap with the contacting zones 38 and 34 is not critical since the P-doped zones 40 and 44 are compensated for by the N-doped zones 38 and 34. If one strives to achieve small capacitances between these P- and N-doped zones 40, 38 and 44, 34, they can be arranged at a distance from one another, which leads to a slight increase in the area requirement. The P-doped zones 40 and 44 have a high sheet resistance (1000 ohms / unit area), so that there is a low emitter base capacitance for the vertical NPN transistor and a high collector base breakdown voltage for the lateral PNP transistor. These zones are also suitable for realizing resistances.

In Fig. 1 sind sämtliche Maskenfenster 18, 20, 22, 24, 26 und 28 durch die Siliziumdioxidschicht 39, 41 unter Verwendung der Siliziumnitridschicht 14 als Ätzmaske geätzt. Für diesen Ätzschritt ist keine gesonderte Maske erforderlich.In FIG. 1, all mask windows 18, 20, 22, 24, 26 and 28 are etched through the silicon dioxide layer 39, 41 using the silicon nitride layer 14 as an etching mask. No separate mask is required for this etching step.

Fig. 1 zeigt die Draufsicht der durch die Siliziumnitridschicht 14 definierten Maskenfenster 18, 20, 22, 24, 26 und 28 in der Siliziumdioxydschicht.1 shows the top view of the mask windows 18, 20, 22, 24, 26 and 28 defined by the silicon nitride layer 14 in the silicon dioxide layer.

In den beiden nächsten Prozeßschritten werden Sperrmasken aus Fotolack in Verbindung mit lonenimplantationen verwendet. Die Reihenfolge der Prozeßschritte kann umgekehrt werden.

  • 1. In Fig. 1 h wird eine Sperrmaske 66 aus Fotolack verwendet, um die N+-dotierte Emitterzone 54 des vertikalen NPN-Transistors, die Kollektoranschlußzone 56 des vertikalen Transistors und die Basisanschlußzone 70 des lateralen PNP-Transistors zu implantieren.
  • 2. Fig. 1 zeigt die Verwendung einer Sperrmaske 58 aus Fotolack, mit deren Hilfe die P+-dotierte Emitterzone 62 des lateralen PNP-Transistors, die Kollektoranschlußzone 60 des lateralen Transistors und die Basisanschlußzone 68 des vertikalen NPN-Transistors implantiert werden.
In the next two process steps, blocking masks made of photoresist are used in connection with ion implantations. The order of the process steps can be reversed.
  • 1. In Figure 1h, a photoresist mask 66 is used to implant the N + doped emitter region 54 of the vertical NPN transistor, the collector region 56 of the vertical transistor and the base region 70 of the lateral PNP transistor.
  • 2. Fig. 1 shows the use of a resist mask 58 made of photoresist, with the aid of which the P + -doped emitter zone 62 of the lateral PNP transistor, the collector connection zone 60 of the lateral transistor and the base connection zone 68 of the vertical NPN transistor are implanted.

Im Anschluß an diese lonenimplantationsprozesse wird ein Erwärmungsprozeß durchgeführt, bei dem die implantierten Bereiche aktiviert und die N+- und P+-dotierten Zonen bis zu ihrer endgültigen Tiefe ausdiffundiert werden.Following these ion implantation processes, a heating process is carried out in which the implanted regions are activated and the N + and P + -doped zones are diffused out to their final depth.

Claims (6)

1. A lateral transistor structure comprising an epitaxial layer (4) arranged over a highly doped, buried sub-base region (6) of a first conductivity type; a collector region (44) of the second conductivity type arranged over the sub-base region (6); a base region (36) of the first conductivity type formed in the collector region by means of a mask and which extends to the sub-base region (6), an emitter region (62) of the second conductivity type introduced into the base region (36) using the same mask, and a base reach through contact region (34) of the first conductivity type connecting the sub-base region (6) to the surface of the epitaxial layer (4), characterised in that the epitaxial layer (4) is of the first conductivity type, in that the collector region (44) is formed in the surface of the epitaxial layer (4) and is spaced from the sub-base region (6), and in that the base region (36) extends through the collector region (44), which surrounds the part of the base region extending through it, and through the epitaxial layer (4) to the sub-base region (6) so that the active intrinsic base region is defined by the lateral sides of the emitter region (62) and the collector region (44).
2. A lateral transistor structure as claimed in claim 1, characterised in that a collector contact region (60) of the second conductivity type is provided in the collector region (44) spaced laterally from the base region (36).
3. A lateral transistor structure as claimed in claim 1 or 2, characterised in that a base contact region of the first conductivity type is provided in the base reachthrough contact region (34).
4. A lateral transistor structure as claimed in claims 1, 2 or 3, characterised in that during integration of the lateral transistor a vertical transistor complementary thereto is also integrated, the following regions corresponding to each other with respect to position and conductivity type: the sub-base region (6) of the lateral transistor to the sub-collector region (8) of the vertical transistor; the collector region (44) of the lateral transistor to the base region (40) of the vertical transistor; the base reachthrough contact region (34) of the lateral transistor to the collector reachthrough contact region (38) of the vertical transistor; and that in the base region (40) of the vertical transistor its emitter region (54) is provided.
5. A lateral transistor structure is claimed in claim 4, characterised in that the base contact region (70) of the lateral transistor is made simultaneously with the emitter region (54) of the vertical transistor.
6. A lateral transistor structure as claimed in claim 4 or 5, characterised in that the collector contact region (60) of the lateral transistor corresponds in position and conductivity type to the base contact region (68) of the vertical transistor.
EP78100655A 1977-08-31 1978-08-16 Lateral transistor Expired EP0000909B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/830,222 US4180827A (en) 1977-08-31 1977-08-31 NPN/PNP Fabrication process with improved alignment
US830222 1977-08-31

Publications (2)

Publication Number Publication Date
EP0000909A1 EP0000909A1 (en) 1979-03-07
EP0000909B1 true EP0000909B1 (en) 1981-07-22

Family

ID=25256566

Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100655A Expired EP0000909B1 (en) 1977-08-31 1978-08-16 Lateral transistor

Country Status (6)

Country Link
US (1) US4180827A (en)
EP (1) EP0000909B1 (en)
JP (1) JPS5438775A (en)
CA (1) CA1118909A (en)
DE (1) DE2860860D1 (en)
IT (1) IT1109971B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4283236A (en) * 1979-09-19 1981-08-11 Harris Corporation Method of fabricating lateral PNP transistors utilizing selective diffusion and counter doping
DE3361832D1 (en) * 1982-04-19 1986-02-27 Matsushita Electric Ind Co Ltd Semiconductor ic and method of making the same
US4492008A (en) * 1983-08-04 1985-01-08 International Business Machines Corporation Methods for making high performance lateral bipolar transistors
GB2148589B (en) * 1983-10-18 1987-04-23 Standard Telephones Cables Ltd Improvements in intergrated circuits
US6091884A (en) * 1991-08-19 2000-07-18 Index Systems, Inc. Enhancing operations of video tape cassette players
JPH09306924A (en) * 1996-03-15 1997-11-28 Toshiba Corp Manufacture of semiconductor device
US6551869B1 (en) * 2000-06-09 2003-04-22 Motorola, Inc. Lateral PNP and method of manufacture
US20060148188A1 (en) * 2005-01-05 2006-07-06 Bcd Semiconductor Manufacturing Limited Fabrication method for bipolar integrated circuits
KR100783278B1 (en) * 2006-08-31 2007-12-06 동부일렉트로닉스 주식회사 Semiconductor device and method for fabricating the same
US8791546B2 (en) * 2010-10-21 2014-07-29 Freescale Semiconductor, Inc. Bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3873989A (en) * 1973-05-07 1975-03-25 Fairchild Camera Instr Co Double-diffused, lateral transistor structure
JPS5155676A (en) * 1974-11-11 1976-05-15 Fujitsu Ltd Handotaisochino seizohoho
US4054900A (en) * 1974-12-27 1977-10-18 Tokyo Shibaura Electric Co., Ltd. I.I.L. with region connecting base of double diffused injector to substrate/emitter of switching transistor
US4058419A (en) * 1974-12-27 1977-11-15 Tokyo Shibaura Electric, Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
FR2337433A1 (en) * 1975-12-29 1977-07-29 Tokyo Shibaura Electric Co Fast integrated injection logic circuit - has two transistors formed by specified zones and achieves low current consumption

Also Published As

Publication number Publication date
IT1109971B (en) 1985-12-23
CA1118909A (en) 1982-02-23
IT7826395A0 (en) 1978-08-02
DE2860860D1 (en) 1981-10-29
US4180827A (en) 1979-12-25
EP0000909A1 (en) 1979-03-07
JPS5438775A (en) 1979-03-23

Similar Documents

Publication Publication Date Title
EP0227970B1 (en) Method of simultaneous fabrication of self-aligned bipolar transistors and complementary mos transistors on a common silicon substrate
EP0036634B1 (en) Method of making a bipolar transistor structure
EP0007923B1 (en) Process for manufacturing a twice diffused lateral transistor and a complemtary vertical transistor integrated therewith
DE3720156C2 (en)
EP0001586B1 (en) Integrated semiconductor device with vertical npn and pnp structures and method for its production
DE1944793C3 (en) Method for manufacturing an integrated semiconductor device
DE2512737A1 (en) UPPER COLLECTOR SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING THE SAME
EP0000909B1 (en) Lateral transistor
DE2351985A1 (en) PLANAR DIFFUSION PROCESS FOR PRODUCING A MONOLITHICALLY INTEGRATED SOLID-WATER CIRCUIT
DE1564218A1 (en) Process for manufacturing transistors
DE1903870B2 (en) METHOD FOR PRODUCING MONOLITHIC SEMICONDUCTOR ARRANGEMENTS AND SEMICONDUCTOR ARRANGEMENT PRODUCED BY THE METHOD
DE1514855B2 (en) SEMI-CONDUCTOR DEVICE
DE3022122C2 (en)
DE2657293B2 (en) Electrical circuit arrangement in transistor-transistor logic circuit (TTL)
DE2261541B2 (en) Process for the production of a linear integrated semiconductor circuit for high performance
EP0008043B1 (en) Integrated bipolar semiconductor circuit
DE2600375C3 (en) Semiconductor arrangement with at least two complementary transistors and method for their production
DE1813130B2 (en) Method of manufacturing a zener diode
DE3005367C2 (en)
DE2527076B2 (en) Integrated semiconductor device and method for its manufacture
DE2428881A1 (en) SEMI-CONDUCTOR STRUCTURE
EP0002191B1 (en) Integrated semiconductor device in i2l-technique and method of manufacturing it
WO2000019535A1 (en) Semiconductor structure for semiconductor components
DE2627922A1 (en) SEMI-CONDUCTOR COMPONENT
DE3026779C2 (en)

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB

17P Request for examination filed
GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 2860860

Country of ref document: DE

Date of ref document: 19811029

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19840720

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19840905

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19890816

GBPC Gb: european patent ceased through non-payment of renewal fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19900427

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19900501

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT