EA201070632A1 - Устройство и способ обработки данных - Google Patents

Устройство и способ обработки данных

Info

Publication number
EA201070632A1
EA201070632A1 EA201070632A EA201070632A EA201070632A1 EA 201070632 A1 EA201070632 A1 EA 201070632A1 EA 201070632 A EA201070632 A EA 201070632A EA 201070632 A EA201070632 A EA 201070632A EA 201070632 A1 EA201070632 A1 EA 201070632A1
Authority
EA
Eurasian Patent Office
Prior art keywords
bits
symbol
code
data processing
code bits
Prior art date
Application number
EA201070632A
Other languages
English (en)
Other versions
EA022022B1 (ru
Inventor
Такаси Ёкокава
Макико Ямамото
Сатоси Окада
Луи Сакаи
Рьёдзи Икегая
Original Assignee
Сони Корпорейшн
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Сони Корпорейшн filed Critical Сони Корпорейшн
Publication of EA201070632A1 publication Critical patent/EA201070632A1/ru
Publication of EA022022B1 publication Critical patent/EA022022B1/ru

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3405—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
    • H04L27/3416—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3488—Multiresolution systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Image Processing (AREA)

Abstract

Настоящее изобретение касается устройства обработки данных и способа обработки данных, которые могут улучшить устойчивость к появлению ошибок в данных. В демультиплексоре 25 заменяют в соответствии с правилом сопоставления битов LDPC-кода и битов символов, которые представляют символы, mb битов из битов кода и используют биты кода после замены как биты b символов. Согласно правилу сопоставления, когда группы, в которые сгруппированы биты кода и биты символа в зависимости от вероятности появления ошибок, используют как группы битов кода и группы битов символа соответственно, определяют комбинацию любой группы битов кода и любой группы битов символа, которой должна быть сопоставлена группа битов кода, и количества битов кода и битов символа.
EA201070632A 2007-11-26 2008-11-26 Устройство и способ обработки данных EA022022B1 (ru)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2007304689 2007-11-26
JP2007304690 2007-11-26
JP2008070467 2008-03-18
JP2008155789 2008-06-13
PCT/JP2008/071390 WO2009069623A1 (ja) 2007-11-26 2008-11-26 データ処理装置、及びデータ処理方法

Publications (2)

Publication Number Publication Date
EA201070632A1 true EA201070632A1 (ru) 2011-02-28
EA022022B1 EA022022B1 (ru) 2015-10-30

Family

ID=40678518

Family Applications (1)

Application Number Title Priority Date Filing Date
EA201070632A EA022022B1 (ru) 2007-11-26 2008-11-26 Устройство и способ обработки данных

Country Status (13)

Country Link
US (1) US8578237B2 (ru)
EP (2) EP2216908B1 (ru)
JP (1) JP5288212B2 (ru)
KR (1) KR101564792B1 (ru)
CN (1) CN101911507B (ru)
AU (1) AU2008330666B2 (ru)
BR (1) BRPI0820159A2 (ru)
EA (1) EA022022B1 (ru)
MY (1) MY159881A (ru)
NZ (1) NZ585415A (ru)
TW (1) TWI459724B (ru)
WO (1) WO2009069623A1 (ru)
ZA (1) ZA201003523B (ru)

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Also Published As

Publication number Publication date
AU2008330666A1 (en) 2009-06-04
AU2008330666B2 (en) 2012-11-15
BRPI0820159A2 (pt) 2015-06-16
US8578237B2 (en) 2013-11-05
CN101911507A (zh) 2010-12-08
CN101911507B (zh) 2013-10-16
NZ585415A (en) 2013-05-31
EP2216908B1 (en) 2017-08-30
TW200947879A (en) 2009-11-16
WO2009069623A1 (ja) 2009-06-04
TWI459724B (zh) 2014-11-01
JP5288212B2 (ja) 2013-09-11
EP2216908A4 (en) 2015-03-04
ZA201003523B (en) 2011-10-26
EP2978137A1 (en) 2016-01-27
KR101564792B1 (ko) 2015-10-30
EP2216908A1 (en) 2010-08-11
US20100275101A1 (en) 2010-10-28
MY159881A (en) 2017-02-15
AU2008330666A2 (en) 2010-08-19
EA022022B1 (ru) 2015-10-30
JPWO2009069623A1 (ja) 2011-04-14
KR20100096099A (ko) 2010-09-01

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