BR112017018314A2 - dispositivo de perfuração de paridade para codificação da informação de sinalização de comprimento fixo, e método de perfuração de paridade utilizando o mesmo - Google Patents
dispositivo de perfuração de paridade para codificação da informação de sinalização de comprimento fixo, e método de perfuração de paridade utilizando o mesmoInfo
- Publication number
- BR112017018314A2 BR112017018314A2 BR112017018314-5A BR112017018314A BR112017018314A2 BR 112017018314 A2 BR112017018314 A2 BR 112017018314A2 BR 112017018314 A BR112017018314 A BR 112017018314A BR 112017018314 A2 BR112017018314 A2 BR 112017018314A2
- Authority
- BR
- Brazil
- Prior art keywords
- parity
- signaling information
- fixed length
- parity drilling
- same
- Prior art date
Links
- 238000005553 drilling Methods 0.000 title abstract 5
- 238000000034 method Methods 0.000 title abstract 2
- 230000011664 signaling Effects 0.000 title abstract 2
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
- H03M13/6393—Rate compatible low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Multimedia (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
tem-se a descrição de uma aparelhagem e método de perfuração de paridade para informação de sinalização de comprimento fixo. uma aparelhagem de perfuração de paridade de acordo com uma modalidade da presente invenção inclui a memória configurada para proporcionar com uma sequência de símbolos de bits de paridade para a perfuração de paridade para os bits de paridade de uma palavra co-dificada por ldpc, cujo comprimento é 16200 e cuja taxa de código é de 3/15, e um processador configurado para perfurar uma quantidade de bits correspondendo a um tamanho de perfuração final a partir da parte traseira da sequência de símbolos de bits de paridade.
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2015-0028062 | 2015-02-27 | ||
KR20150028062 | 2015-02-27 | ||
KR20150031949 | 2015-03-06 | ||
KR10-2015-0031949 | 2015-03-06 | ||
KR1020160020852A KR102453473B1 (ko) | 2015-02-27 | 2016-02-22 | 고정 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
KR10-2016-0020852 | 2016-02-22 | ||
PCT/KR2016/001875 WO2016137253A1 (ko) | 2015-02-27 | 2016-02-25 | 고정 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
Publications (2)
Publication Number | Publication Date |
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BR112017018314A2 true BR112017018314A2 (pt) | 2018-04-17 |
BR112017018314B1 BR112017018314B1 (pt) | 2023-10-31 |
Family
ID=56789603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112017018314-5A BR112017018314B1 (pt) | 2015-02-27 | 2016-02-25 | Aparelho e método de puncionamento de paridade, e aparelho de puncionamento de paridade inverso |
Country Status (6)
Country | Link |
---|---|
US (3) | US10284227B2 (pt) |
KR (1) | KR102634679B1 (pt) |
BR (1) | BR112017018314B1 (pt) |
CA (1) | CA2977627C (pt) |
MX (1) | MX2017010997A (pt) |
WO (1) | WO2016137253A1 (pt) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102453474B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
WO2016137254A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
KR102453472B1 (ko) | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
WO2016137204A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 고정 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
KR102453476B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 고정 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
HUE050708T2 (hu) * | 2016-04-08 | 2020-12-28 | Idac Holdings Inc | Különbözõ típusú forgalmak PHY rétegbeli multiplexelése 5G rendszerekben |
CN107959502B (zh) * | 2016-10-17 | 2021-04-20 | 上海数字电视国家工程研究中心有限公司 | 一种ldpc编码方法 |
EP3535886B1 (en) | 2016-11-02 | 2024-10-09 | InterDigital Patent Holdings, Inc. | Shared data channel design |
Family Cites Families (16)
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US6961388B2 (en) * | 2001-02-01 | 2005-11-01 | Qualcomm, Incorporated | Coding scheme for a wireless communication system |
US7702986B2 (en) * | 2002-11-18 | 2010-04-20 | Qualcomm Incorporated | Rate-compatible LDPC codes |
KR100895612B1 (ko) * | 2007-05-29 | 2009-05-06 | 연세대학교 산학협력단 | 블록 형태 저밀도 패러티 검사 부호의 천공 방법 |
US8266508B2 (en) | 2007-06-08 | 2012-09-11 | Telefonaktiebolaget L M Ericsson (Publ) | Computational efficient convolutional coding with rate matching |
KR101503058B1 (ko) | 2008-02-26 | 2015-03-18 | 삼성전자주식회사 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치 |
US8689093B2 (en) * | 2009-12-07 | 2014-04-01 | Samsung Electronics Co., Ltd | Method and apparatus for channel encoding and decoding in a communication system using a low-density parity check code |
KR101611169B1 (ko) * | 2011-01-18 | 2016-04-11 | 삼성전자주식회사 | 통신/방송 시스템에서 데이터 송수신 장치 및 방법 |
KR101922555B1 (ko) * | 2011-08-30 | 2018-11-28 | 삼성전자주식회사 | 방송/통신시스템에서 정보 송수신 방법 및 장치 |
WO2013032156A1 (en) | 2011-08-30 | 2013-03-07 | Samsung Electronics Co., Ltd. | Method and apparatus for transmitting and receiving information in a broadcasting/communication system |
KR20150005426A (ko) | 2013-07-05 | 2015-01-14 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
US10305632B2 (en) | 2013-09-17 | 2019-05-28 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
WO2015041482A1 (en) * | 2013-09-18 | 2015-03-26 | Samsung Electronics Co., Ltd. | Transmitting apparatus and puncturing method thereof |
KR102204137B1 (ko) * | 2014-06-27 | 2021-01-19 | 엘지디스플레이 주식회사 | 표시장치 및 이를 제조하는 방법 |
KR102453472B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
WO2016137255A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
US10326474B2 (en) * | 2015-03-02 | 2019-06-18 | Samsung Electronics Co., Ltd. | Transmitter and parity permutation method thereof |
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2016
- 2016-02-25 US US15/553,936 patent/US10284227B2/en active Active
- 2016-02-25 WO PCT/KR2016/001875 patent/WO2016137253A1/ko active Application Filing
- 2016-02-25 BR BR112017018314-5A patent/BR112017018314B1/pt active IP Right Grant
- 2016-02-25 MX MX2017010997A patent/MX2017010997A/es active IP Right Grant
- 2016-02-25 CA CA2977627A patent/CA2977627C/en active Active
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2019
- 2019-03-14 US US16/353,378 patent/US10812104B2/en active Active
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2020
- 2020-09-15 US US17/021,025 patent/US11316531B2/en active Active
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2022
- 2022-10-04 KR KR1020220126523A patent/KR102634679B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
US10284227B2 (en) | 2019-05-07 |
CA2977627C (en) | 2020-01-07 |
BR112017018314B1 (pt) | 2023-10-31 |
US11316531B2 (en) | 2022-04-26 |
KR102634679B1 (ko) | 2024-02-08 |
CA2977627A1 (en) | 2016-09-01 |
MX2017010997A (es) | 2017-10-18 |
US20180041225A1 (en) | 2018-02-08 |
KR20220141767A (ko) | 2022-10-20 |
WO2016137253A1 (ko) | 2016-09-01 |
US20200412380A1 (en) | 2020-12-31 |
US20190215009A1 (en) | 2019-07-11 |
US10812104B2 (en) | 2020-10-20 |
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