MX2017010997A - Dispositivo de perforacion de paridad para la codificacion de informacion de señalizacion de longitud fija y metodo de perforacion de paridad que lo utiliza. - Google Patents
Dispositivo de perforacion de paridad para la codificacion de informacion de señalizacion de longitud fija y metodo de perforacion de paridad que lo utiliza.Info
- Publication number
- MX2017010997A MX2017010997A MX2017010997A MX2017010997A MX2017010997A MX 2017010997 A MX2017010997 A MX 2017010997A MX 2017010997 A MX2017010997 A MX 2017010997A MX 2017010997 A MX2017010997 A MX 2017010997A MX 2017010997 A MX2017010997 A MX 2017010997A
- Authority
- MX
- Mexico
- Prior art keywords
- parity
- parity puncturing
- signaling information
- fixed
- same
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
- H03M13/6393—Rate compatible low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Multimedia (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Se describe un aparato de perforación de paridad y método para información de señalización de longitud fija; un aparato de perforación de paridad de acuerdo con una modalidad de la presente invención incluye una memoria configurada para proporcionar una cadena de bits de paridad para la perforación de paridad para los bits de paridad de una palabra de código LDPC cuya longitud es 16200 y cuya tasa de codificación es 3/15 y un procesador configurado para perforar un número de bits que corresponden a un tamaño de perforación final desde el lado posterior de la cadena de bits de paridad.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20150028062 | 2015-02-27 | ||
| KR20150031949 | 2015-03-06 | ||
| KR1020160020852A KR102453473B1 (ko) | 2015-02-27 | 2016-02-22 | 고정 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
| PCT/KR2016/001875 WO2016137253A1 (ko) | 2015-02-27 | 2016-02-25 | 고정 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| MX2017010997A true MX2017010997A (es) | 2017-10-18 |
| MX373706B MX373706B (es) | 2020-05-07 |
Family
ID=56789603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX2017010997A MX373706B (es) | 2015-02-27 | 2016-02-25 | Dispositivo de perforacion de paridad para la codificacion de informacion de señalizacion de longitud fija y metodo de perforacion de paridad que lo utiliza. |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US10284227B2 (es) |
| KR (1) | KR102634679B1 (es) |
| BR (1) | BR112017018314B1 (es) |
| CA (1) | CA2977627C (es) |
| MX (1) | MX373706B (es) |
| WO (1) | WO2016137253A1 (es) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102453472B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
| KR102453476B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 고정 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
| WO2016137204A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 고정 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
| WO2016137254A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
| KR102453474B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
| CN109155682B (zh) | 2016-04-08 | 2021-04-23 | Idac控股公司 | 关于5g系统内的不同类型业务量的phy层复用 |
| CN107959502B (zh) * | 2016-10-17 | 2021-04-20 | 上海数字电视国家工程研究中心有限公司 | 一种ldpc编码方法 |
| TWI767952B (zh) | 2016-11-02 | 2022-06-21 | 美商Idac控股公司 | 無線傳輸/接收單元(wtru)及用於解碼資料的方法 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6961388B2 (en) * | 2001-02-01 | 2005-11-01 | Qualcomm, Incorporated | Coding scheme for a wireless communication system |
| US7702986B2 (en) * | 2002-11-18 | 2010-04-20 | Qualcomm Incorporated | Rate-compatible LDPC codes |
| KR100895612B1 (ko) | 2007-05-29 | 2009-05-06 | 연세대학교 산학협력단 | 블록 형태 저밀도 패러티 검사 부호의 천공 방법 |
| US8266508B2 (en) | 2007-06-08 | 2012-09-11 | Telefonaktiebolaget L M Ericsson (Publ) | Computational efficient convolutional coding with rate matching |
| KR101503058B1 (ko) | 2008-02-26 | 2015-03-18 | 삼성전자주식회사 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치 |
| KR101740316B1 (ko) * | 2009-12-07 | 2017-05-29 | 삼성전자주식회사 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서 채널 부호화/복호화 방법 및 장치 |
| KR101611169B1 (ko) | 2011-01-18 | 2016-04-11 | 삼성전자주식회사 | 통신/방송 시스템에서 데이터 송수신 장치 및 방법 |
| WO2013032156A1 (en) | 2011-08-30 | 2013-03-07 | Samsung Electronics Co., Ltd. | Method and apparatus for transmitting and receiving information in a broadcasting/communication system |
| KR101922555B1 (ko) | 2011-08-30 | 2018-11-28 | 삼성전자주식회사 | 방송/통신시스템에서 정보 송수신 방법 및 장치 |
| KR20150005426A (ko) | 2013-07-05 | 2015-01-14 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
| US10305632B2 (en) | 2013-09-17 | 2019-05-28 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
| WO2015041482A1 (en) * | 2013-09-18 | 2015-03-26 | Samsung Electronics Co., Ltd. | Transmitting apparatus and puncturing method thereof |
| KR102204137B1 (ko) * | 2014-06-27 | 2021-01-19 | 엘지디스플레이 주식회사 | 표시장치 및 이를 제조하는 방법 |
| WO2016137255A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
| KR102453472B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
| US10326474B2 (en) * | 2015-03-02 | 2019-06-18 | Samsung Electronics Co., Ltd. | Transmitter and parity permutation method thereof |
-
2016
- 2016-02-25 US US15/553,936 patent/US10284227B2/en active Active
- 2016-02-25 CA CA2977627A patent/CA2977627C/en active Active
- 2016-02-25 BR BR112017018314-5A patent/BR112017018314B1/pt active IP Right Grant
- 2016-02-25 WO PCT/KR2016/001875 patent/WO2016137253A1/ko not_active Ceased
- 2016-02-25 MX MX2017010997A patent/MX373706B/es active IP Right Grant
-
2019
- 2019-03-14 US US16/353,378 patent/US10812104B2/en active Active
-
2020
- 2020-09-15 US US17/021,025 patent/US11316531B2/en active Active
-
2022
- 2022-10-04 KR KR1020220126523A patent/KR102634679B1/ko active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US11316531B2 (en) | 2022-04-26 |
| CA2977627A1 (en) | 2016-09-01 |
| BR112017018314B1 (pt) | 2023-10-31 |
| WO2016137253A1 (ko) | 2016-09-01 |
| KR102634679B1 (ko) | 2024-02-08 |
| US20180041225A1 (en) | 2018-02-08 |
| US20200412380A1 (en) | 2020-12-31 |
| BR112017018314A2 (pt) | 2018-04-17 |
| US10284227B2 (en) | 2019-05-07 |
| US10812104B2 (en) | 2020-10-20 |
| CA2977627C (en) | 2020-01-07 |
| KR20220141767A (ko) | 2022-10-20 |
| US20190215009A1 (en) | 2019-07-11 |
| MX373706B (es) | 2020-05-07 |
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