BR112019009552A2 - aparelho e método de transmissão, e, aparelho e método de recepção. - Google Patents
aparelho e método de transmissão, e, aparelho e método de recepção. Download PDFInfo
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- BR112019009552A2 BR112019009552A2 BR112019009552A BR112019009552A BR112019009552A2 BR 112019009552 A2 BR112019009552 A2 BR 112019009552A2 BR 112019009552 A BR112019009552 A BR 112019009552A BR 112019009552 A BR112019009552 A BR 112019009552A BR 112019009552 A2 BR112019009552 A2 BR 112019009552A2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
Abstract
a presente invenção refere-se a um dispositivo de transmissão, a um método de transmissão, a um dispositivo de recepção e a um método de recepção, de acordo com os quais boa qualidade de comunicações pode ser garantida durante a transmissão de dados usando os códigos ldpc. a codificação ldpc é realizada com base em matrizes de verificação para os códigos ldpc com um comprimento de código n de 69.120 bits e uma taxa de codificação r de 7/16 ou 8/16. os códigos ldpc incluem os bits de informação e os bits de paridade. as matrizes de verificação incluem as matrizes de informação correspondentes aos bits de informação e as matrizes de paridade correspondentes aos bits de paridade. as matrizes de informação são descritas por uma tabela de valor inicial da matriz de verificação. a tabela de valor inicial da matriz de verificação indica a posição de um elemento em uma matriz de informação, para cada 360 colunas, e é uma tabela predeterminada. a presente invenção é aplicável, por exemplo, na transmissão de dados, etc., usando os códigos ldpc.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016224604A JP6885027B2 (ja) | 2016-11-18 | 2016-11-18 | 送信装置、及び、送信方法 |
PCT/JP2017/039857 WO2018092615A1 (ja) | 2016-11-18 | 2017-11-06 | 送信装置、送信方法、受信装置、及び、受信方法 |
Publications (1)
Publication Number | Publication Date |
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BR112019009552A2 true BR112019009552A2 (pt) | 2019-07-30 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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BR112019009552A BR112019009552A2 (pt) | 2016-11-18 | 2017-11-06 | aparelho e método de transmissão, e, aparelho e método de recepção. |
Country Status (8)
Country | Link |
---|---|
US (1) | US10812222B2 (pt) |
EP (1) | EP3544190B1 (pt) |
JP (4) | JP6885027B2 (pt) |
KR (1) | KR102326752B1 (pt) |
BR (1) | BR112019009552A2 (pt) |
PH (1) | PH12019501035A1 (pt) |
TW (1) | TWI672030B (pt) |
WO (1) | WO2018092615A1 (pt) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP6880791B2 (ja) * | 2017-02-06 | 2021-06-02 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6891518B2 (ja) * | 2017-02-06 | 2021-06-18 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6852427B2 (ja) * | 2017-02-06 | 2021-03-31 | ソニー株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6897204B2 (ja) * | 2017-02-20 | 2021-06-30 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6895053B2 (ja) * | 2017-02-20 | 2021-06-30 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
Family Cites Families (29)
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US7260764B2 (en) | 2002-11-26 | 2007-08-21 | Qualcomm Incorporated | Multi-channel transmission and reception with block coding in a communication system |
JP4224777B2 (ja) | 2003-05-13 | 2009-02-18 | ソニー株式会社 | 復号方法および復号装置、並びにプログラム |
US7596743B2 (en) | 2005-09-28 | 2009-09-29 | Ati Technologies Inc. | Method and apparatus for error management |
JP4688841B2 (ja) * | 2007-03-20 | 2011-05-25 | 日本放送協会 | 符号化器及び復号器、並びに送信装置及び受信装置 |
JP4898858B2 (ja) * | 2009-03-02 | 2012-03-21 | パナソニック株式会社 | 符号化器、復号化器及び符号化方法 |
US8595588B2 (en) * | 2009-11-13 | 2013-11-26 | Panasonic Corporation | Encoding method, decoding method, coder and decoder |
WO2012098898A1 (ja) * | 2011-01-21 | 2012-07-26 | パナソニック株式会社 | 符号化方法、復号方法 |
CN106059641B (zh) * | 2011-02-21 | 2019-11-26 | 太阳专利托管公司 | 预编码方法、预编码装置 |
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EP2955853A4 (en) * | 2013-02-08 | 2016-08-24 | Sony Corp | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD |
WO2014123017A1 (ja) * | 2013-02-08 | 2014-08-14 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
KR102104937B1 (ko) * | 2013-06-14 | 2020-04-27 | 삼성전자주식회사 | Ldpc 부호의 부호화 장치, 그의 부호화 방법, 복호화 장치 및 그의 복호화 방법 |
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EP3070850B1 (en) * | 2013-11-15 | 2019-07-17 | Nippon Hoso Kyokai | Encoder and decoder for an ldpc code of rate 93/120 and length 44880 |
JP2015130602A (ja) * | 2014-01-08 | 2015-07-16 | ソニー株式会社 | データ処理装置及びデータ処理方法 |
US9602137B2 (en) | 2014-02-19 | 2017-03-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
JP2015156530A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015170911A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015170912A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
KR101776267B1 (ko) * | 2015-02-24 | 2017-09-07 | 삼성전자주식회사 | 송신 장치 및 그의 리피티션 방법 |
KR101776273B1 (ko) * | 2015-02-25 | 2017-09-07 | 삼성전자주식회사 | 송신 장치 및 그의 부가 패리티 생성 방법 |
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-
2016
- 2016-11-18 JP JP2016224604A patent/JP6885027B2/ja active Active
-
2017
- 2017-11-06 EP EP17872084.3A patent/EP3544190B1/en active Active
- 2017-11-06 BR BR112019009552A patent/BR112019009552A2/pt unknown
- 2017-11-06 WO PCT/JP2017/039857 patent/WO2018092615A1/ja unknown
- 2017-11-06 KR KR1020197013049A patent/KR102326752B1/ko active IP Right Grant
- 2017-11-06 US US16/349,071 patent/US10812222B2/en active Active
- 2017-11-08 TW TW106138566A patent/TWI672030B/zh active
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2019
- 2019-05-10 PH PH12019501035A patent/PH12019501035A1/en unknown
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2021
- 2021-05-12 JP JP2021080770A patent/JP7156440B2/ja active Active
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2022
- 2022-10-04 JP JP2022160301A patent/JP7367827B2/ja active Active
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2023
- 2023-10-11 JP JP2023175766A patent/JP2023171551A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US10812222B2 (en) | 2020-10-20 |
EP3544190A1 (en) | 2019-09-25 |
KR20190084044A (ko) | 2019-07-15 |
EP3544190A4 (en) | 2019-10-30 |
JP2022173552A (ja) | 2022-11-18 |
PH12019501035A1 (en) | 2019-12-02 |
JP7156440B2 (ja) | 2022-10-19 |
JP2023171551A (ja) | 2023-12-01 |
EP3544190B1 (en) | 2021-05-26 |
JP6885027B2 (ja) | 2021-06-09 |
KR102326752B1 (ko) | 2021-11-17 |
TWI672030B (zh) | 2019-09-11 |
JP2018082366A (ja) | 2018-05-24 |
JP2021119715A (ja) | 2021-08-12 |
US20190280816A1 (en) | 2019-09-12 |
TW201824831A (zh) | 2018-07-01 |
JP7367827B2 (ja) | 2023-10-24 |
WO2018092615A1 (ja) | 2018-05-24 |
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B350 | Update of information on the portal [chapter 15.35 patent gazette] | ||
B06W | Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette] | ||
B15K | Others concerning applications: alteration of classification |
Free format text: A CLASSIFICACAO ANTERIOR ERA: H03M 13/19 Ipc: H03M 13/11 (2006.01), H03M 13/19 (2006.01), H03M 1 |