DE69942356D1 - Verfahren zur Bereitstellung einer flachen Grabenisolation von Transistoren - Google Patents
Verfahren zur Bereitstellung einer flachen Grabenisolation von TransistorenInfo
- Publication number
- DE69942356D1 DE69942356D1 DE69942356T DE69942356T DE69942356D1 DE 69942356 D1 DE69942356 D1 DE 69942356D1 DE 69942356 T DE69942356 T DE 69942356T DE 69942356 T DE69942356 T DE 69942356T DE 69942356 D1 DE69942356 D1 DE 69942356D1
- Authority
- DE
- Germany
- Prior art keywords
- transistors
- providing
- trench isolation
- shallow trench
- shallow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000002955 isolation Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7104298P | 1998-01-13 | 1998-01-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69942356D1 true DE69942356D1 (de) | 2010-06-24 |
Family
ID=22098896
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69942356T Expired - Lifetime DE69942356D1 (de) | 1998-01-13 | 1999-01-13 | Verfahren zur Bereitstellung einer flachen Grabenisolation von Transistoren |
Country Status (6)
Country | Link |
---|---|
US (1) | US6228741B1 (de) |
EP (1) | EP0954022B1 (de) |
JP (1) | JPH11284064A (de) |
KR (1) | KR19990067929A (de) |
DE (1) | DE69942356D1 (de) |
TW (1) | TW426934B (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2352874B (en) * | 1999-07-01 | 2002-10-09 | Lucent Technologies Inc | An integrated circuit and a process for manufacturing the integrated circuit |
US6251747B1 (en) * | 1999-11-02 | 2001-06-26 | Philips Semiconductors, Inc. | Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
KR100419753B1 (ko) * | 1999-12-30 | 2004-02-21 | 주식회사 하이닉스반도체 | 반도체소자의 소자분리막 형성방법 |
KR100355875B1 (ko) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | 반도체 소자 분리 방법 |
US6503813B1 (en) * | 2000-06-16 | 2003-01-07 | International Business Machines Corporation | Method and structure for forming a trench in a semiconductor substrate |
US6531265B2 (en) * | 2000-12-14 | 2003-03-11 | International Business Machines Corporation | Method to planarize semiconductor surface |
NZ544187A (en) | 2005-12-15 | 2008-07-31 | Ind Res Ltd | Deazapurine analogs of 1'-aza-l-nucleosides |
US7514336B2 (en) * | 2005-12-29 | 2009-04-07 | Agere Systems Inc. | Robust shallow trench isolation structures and a method for forming shallow trench isolation structures |
ES2362805T3 (es) | 2006-09-07 | 2011-07-13 | Industrial Research Limited | Inhibidores aminoacíclicos de nucleósido fosforilasas e hidrolasas. |
BR112013009029B1 (pt) | 2010-10-15 | 2021-06-29 | Biocryst Pharmaceuticals, Inc. | Métodos e composições para inibição de polimerase |
US8859388B2 (en) | 2012-07-13 | 2014-10-14 | International Business Machines Corporation | Sealed shallow trench isolation region |
MA43812A (fr) | 2016-03-06 | 2018-11-28 | Biocryst Pharm Inc | Procédés et compositions pour le traitement d'une infection par le virus zika |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6053045A (ja) | 1983-09-02 | 1985-03-26 | Hitachi Ltd | 絶縁分離方法 |
JPS6064445A (ja) | 1983-09-20 | 1985-04-13 | Fujitsu Ltd | 素子分離用絶縁体層を有する半導体装置の製造方法 |
JP2870054B2 (ja) | 1989-10-25 | 1999-03-10 | ソニー株式会社 | 半導体装置の製造方法 |
US5786263A (en) * | 1995-04-04 | 1998-07-28 | Motorola, Inc. | Method for forming a trench isolation structure in an integrated circuit |
TW388096B (en) | 1996-06-10 | 2000-04-21 | Texas Instruments Inc | Integrated circuit insulator and method |
US5721173A (en) | 1997-02-25 | 1998-02-24 | Kabushiki Kaisha Toshiba | Method of forming a shallow trench isolation structure |
US5976947A (en) * | 1997-08-18 | 1999-11-02 | Micron Technology, Inc. | Method for forming dielectric within a recess |
US6074927A (en) * | 1998-06-01 | 2000-06-13 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with trench wall spacer |
US5976951A (en) * | 1998-06-30 | 1999-11-02 | United Microelectronics Corp. | Method for preventing oxide recess formation in a shallow trench isolation |
-
1999
- 1999-01-11 US US09/228,583 patent/US6228741B1/en not_active Expired - Lifetime
- 1999-01-13 DE DE69942356T patent/DE69942356D1/de not_active Expired - Lifetime
- 1999-01-13 EP EP99300264A patent/EP0954022B1/de not_active Expired - Lifetime
- 1999-01-13 JP JP11006782A patent/JPH11284064A/ja active Pending
- 1999-01-13 KR KR1019990001110A patent/KR19990067929A/ko not_active Application Discontinuation
- 1999-03-12 TW TW088100431A patent/TW426934B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0954022B1 (de) | 2010-05-12 |
KR19990067929A (ko) | 1999-08-25 |
JPH11284064A (ja) | 1999-10-15 |
EP0954022A1 (de) | 1999-11-03 |
US6228741B1 (en) | 2001-05-08 |
TW426934B (en) | 2001-03-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69740022D1 (de) | Verfahren zur Herstellung eines Isolationsgraben einer integrierten Schaltung | |
DE69822219D1 (de) | Verfahren zur übertragung von information bezüglich des synchronisationszustandes einer basisstation | |
DE69835276D1 (de) | Verfahren zur Herstellung einer selbst-planarisierten dielektrischen Schicht für eine seichte Grabenisolation | |
DE69515926T2 (de) | Verfahren zur Züchtung einer Halbleiterverbindungsschicht | |
DE69909205D1 (de) | Verfahren zur Herstellung vertikaler Transistoren | |
DE69738681D1 (de) | Verfahren zur Herstellung einer Anordnung mit Graben-MOS-Gate | |
DE69932526D1 (de) | Verfahren zur homogenisierung | |
DE69808091D1 (de) | Verfahren zur epoxidation von propylen | |
DE60039744D1 (de) | Verfahren zur Hersltellung einer Siliziumschicht | |
DE69836401D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE69935469D1 (de) | Verfahren zur schnellen Ausführung einer Entschlüsselung oder einer Authentifizierung | |
DE69534870D1 (de) | Verfahren zur Herstellung eines flachen Grabens zur Isolierung von zwei nebeneinanderliegenden tiefen Gräben unter Verwendung eines Silizidierungsprozesses | |
DE59908716D1 (de) | Verfahren zur Vermeidung einer Gewässerkontamination mit ortsfremden Organismen | |
DE69918636D1 (de) | Verfahren zur herstellung einer halbleitervorrichtung | |
DE69913030D1 (de) | Verfahren zur Regelung einer Verbrennung | |
DE69942812D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE69942356D1 (de) | Verfahren zur Bereitstellung einer flachen Grabenisolation von Transistoren | |
DE59900006D1 (de) | Verfahren zur Isolierung von gekrümmten Flächen | |
DE69723493D1 (de) | Grabenisolierung einer Halbleiteranordnung und Verfahren zu seiner Herstellung | |
DE69634675D1 (de) | Verfahren zur Isolierung einer Halbleiteranordnung | |
DE69903790D1 (de) | Verfahren zur herstelung von sojamilch | |
DE69940737D1 (de) | Verfahren zur herstellung einer halbleiteranordnung | |
DE69820026D1 (de) | Verfahren zur Berechnung von Phasenverschiebungs-Koeffizienten einer M-Folge | |
DE69940761D1 (de) | Verfahren zur Transistorsherstellung | |
DE69942186D1 (de) | Verfahren zur herstellung einer halbleiteranordnung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |