DE69740022D1 - Verfahren zur Herstellung eines Isolationsgraben einer integrierten Schaltung - Google Patents

Verfahren zur Herstellung eines Isolationsgraben einer integrierten Schaltung

Info

Publication number
DE69740022D1
DE69740022D1 DE69740022T DE69740022T DE69740022D1 DE 69740022 D1 DE69740022 D1 DE 69740022D1 DE 69740022 T DE69740022 T DE 69740022T DE 69740022 T DE69740022 T DE 69740022T DE 69740022 D1 DE69740022 D1 DE 69740022D1
Authority
DE
Germany
Prior art keywords
producing
integrated circuit
isolation trench
trench
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69740022T
Other languages
English (en)
Inventor
Somnath S Nag
Amitava Chatterjee
Ih-Chin Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69740022D1 publication Critical patent/DE69740022D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE69740022T 1996-06-10 1997-06-09 Verfahren zur Herstellung eines Isolationsgraben einer integrierten Schaltung Expired - Lifetime DE69740022D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1968896P 1996-06-10 1996-06-10

Publications (1)

Publication Number Publication Date
DE69740022D1 true DE69740022D1 (de) 2010-11-25

Family

ID=21794537

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69740022T Expired - Lifetime DE69740022D1 (de) 1996-06-10 1997-06-09 Verfahren zur Herstellung eines Isolationsgraben einer integrierten Schaltung

Country Status (6)

Country Link
US (1) US6313010B1 (de)
EP (2) EP2287901A3 (de)
JP (1) JP4195734B2 (de)
KR (1) KR100655845B1 (de)
DE (1) DE69740022D1 (de)
TW (1) TW388096B (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235856B1 (en) * 1997-12-18 2007-06-26 Micron Technology, Inc. Trench isolation for semiconductor devices
US6228741B1 (en) 1998-01-13 2001-05-08 Texas Instruments Incorporated Method for trench isolation of semiconductor devices
JP3262059B2 (ja) * 1998-02-12 2002-03-04 日本電気株式会社 半導体装置の製造方法
US6194038B1 (en) 1998-03-20 2001-02-27 Applied Materials, Inc. Method for deposition of a conformal layer on a substrate
JPH11284060A (ja) 1998-03-27 1999-10-15 Hitachi Ltd 半導体装置及びその製造方法
US6759306B1 (en) * 1998-07-10 2004-07-06 Micron Technology, Inc. Methods of forming silicon dioxide layers and methods of forming trench isolation regions
DE60042998D1 (de) * 1999-10-12 2009-11-05 St Microelectronics Srl Verfahren zur Planarisierung von flachen Grabenisolationsstrukturen
CN100382277C (zh) * 1999-12-24 2008-04-16 Nxp有限公司 半导体器件的制造方法
KR100419753B1 (ko) * 1999-12-30 2004-02-21 주식회사 하이닉스반도체 반도체소자의 소자분리막 형성방법
US6762129B2 (en) * 2000-04-19 2004-07-13 Matsushita Electric Industrial Co., Ltd. Dry etching method, fabrication method for semiconductor device, and dry etching apparatus
US6559026B1 (en) * 2000-05-25 2003-05-06 Applied Materials, Inc Trench fill with HDP-CVD process including coupled high power density plasma deposition
US6437417B1 (en) * 2000-08-16 2002-08-20 Micron Technology, Inc. Method for making shallow trenches for isolation
JP4847671B2 (ja) * 2000-10-19 2011-12-28 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング 誘導結合プラズマを用いて基板をエッチングする装置および方法
US6458722B1 (en) * 2000-10-25 2002-10-01 Applied Materials, Inc. Controlled method of silicon-rich oxide deposition using HDP-CVD
US6596653B2 (en) 2001-05-11 2003-07-22 Applied Materials, Inc. Hydrogen assisted undoped silicon oxide deposition process for HDP-CVD
US6740601B2 (en) 2001-05-11 2004-05-25 Applied Materials Inc. HDP-CVD deposition process for filling high aspect ratio gaps
DE10127622B4 (de) * 2001-06-07 2009-10-22 Qimonda Ag Verfahren zur Herstellung eines mit HDPCVD-Oxid gefüllten Isolationsgrabens
US6812064B2 (en) * 2001-11-07 2004-11-02 Micron Technology, Inc. Ozone treatment of a ground semiconductor die to improve adhesive bonding to a substrate
US6812153B2 (en) * 2002-04-30 2004-11-02 Applied Materials Inc. Method for high aspect ratio HDP CVD gapfill
US7628897B2 (en) * 2002-10-23 2009-12-08 Applied Materials, Inc. Reactive ion etching for semiconductor device feature topography modification
JP2004193585A (ja) 2002-11-29 2004-07-08 Fujitsu Ltd 半導体装置の製造方法と半導体装置
US7097886B2 (en) * 2002-12-13 2006-08-29 Applied Materials, Inc. Deposition process for high aspect ratio trenches
US6808748B2 (en) * 2003-01-23 2004-10-26 Applied Materials, Inc. Hydrogen assisted HDP-CVD deposition process for aggressive gap-fill technology
US7081414B2 (en) * 2003-05-23 2006-07-25 Applied Materials, Inc. Deposition-selective etch-deposition process for dielectric film gapfill
US6958112B2 (en) 2003-05-27 2005-10-25 Applied Materials, Inc. Methods and systems for high-aspect-ratio gapfill using atomic-oxygen generation
US7205240B2 (en) 2003-06-04 2007-04-17 Applied Materials, Inc. HDP-CVD multistep gapfill process
US7354834B2 (en) * 2003-06-04 2008-04-08 Dongbu Electronics Co., Ltd. Semiconductor devices and methods to form trenches in semiconductor devices
US6903031B2 (en) 2003-09-03 2005-06-07 Applied Materials, Inc. In-situ-etch-assisted HDP deposition using SiF4 and hydrogen
US7087497B2 (en) * 2004-03-04 2006-08-08 Applied Materials Low-thermal-budget gapfill process
JP2005340327A (ja) 2004-05-25 2005-12-08 Renesas Technology Corp 半導体装置及びその製造方法
US7183227B1 (en) 2004-07-01 2007-02-27 Applied Materials, Inc. Use of enhanced turbomolecular pump for gapfill deposition using high flows of low-mass fluent gas
JP4961668B2 (ja) * 2005-01-11 2012-06-27 富士電機株式会社 半導体装置の製造方法
KR100767333B1 (ko) * 2006-05-24 2007-10-17 한국과학기술연구원 계면 제어층을 포함하는 비휘발성 전기적 상변화 메모리소자 및 이의 제조방법
JP2008060266A (ja) * 2006-08-30 2008-03-13 Oki Electric Ind Co Ltd 素子分離膜の形成方法と不揮発性半導体メモリ
US7678715B2 (en) 2007-12-21 2010-03-16 Applied Materials, Inc. Low wet etch rate silicon nitride film
US8497211B2 (en) 2011-06-24 2013-07-30 Applied Materials, Inc. Integrated process modulation for PSG gapfill
JP5859758B2 (ja) * 2011-07-05 2016-02-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
DE69226253T2 (de) * 1992-01-24 1998-12-17 Applied Materials Inc Plasmaätzverfahren und Reaktor zur Plasmabearbeitung
US5397962A (en) * 1992-06-29 1995-03-14 Texas Instruments Incorporated Source and method for generating high-density plasma with inductive power coupling
US5494857A (en) 1993-07-28 1996-02-27 Digital Equipment Corporation Chemical mechanical planarization of shallow trenches in semiconductor substrates
US5614055A (en) * 1993-08-27 1997-03-25 Applied Materials, Inc. High density plasma CVD and etching reactor
JP3438446B2 (ja) * 1995-05-15 2003-08-18 ソニー株式会社 半導体装置の製造方法
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
KR100214068B1 (ko) * 1995-11-21 1999-08-02 김영환 반도체 장치의 소자분리막 형성방법
WO1997024761A1 (en) * 1995-12-27 1997-07-10 Lam Research Corporation Methods and apparatus for filling trenches in a semiconductor wafer
US5851899A (en) * 1996-08-08 1998-12-22 Siemens Aktiengesellschaft Gapfill and planarization process for shallow trench isolation
US5728621A (en) * 1997-04-28 1998-03-17 Chartered Semiconductor Manufacturing Pte Ltd Method for shallow trench isolation

Also Published As

Publication number Publication date
JPH1056058A (ja) 1998-02-24
EP2287901A3 (de) 2014-05-07
EP0813240B1 (de) 2010-10-13
TW388096B (en) 2000-04-21
EP2287901A2 (de) 2011-02-23
US6313010B1 (en) 2001-11-06
JP4195734B2 (ja) 2008-12-10
EP0813240A1 (de) 1997-12-17
KR980006113A (ko) 1998-03-30
KR100655845B1 (ko) 2007-04-11

Similar Documents

Publication Publication Date Title
DE69740022D1 (de) Verfahren zur Herstellung eines Isolationsgraben einer integrierten Schaltung
DE69432068D1 (de) Verfahren zur Herstellung einer Isolationsgrabenstruktur für eine integrierte Schaltung.
DE59506266D1 (de) Verfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur
DE69902860T2 (de) Verfahren zur Herstellung eines integrierten Halbleiterbauelements
DE69816978D1 (de) Verfahren zur herstellung eines integrierten magnetoelastischen wandlers
DE69708268T2 (de) Verfahren zur herstellung einer optischen schicht
DE69838709D1 (de) Verfahren zur herstellung eines beschleunigungsaufnehmers
DE69730940D1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE69627951D1 (de) Verfahren zur Herstellung einer elektronenemittierende Vorrichtung
DE59902175D1 (de) Verfahren zur Herstellung eines optoelektronischen Bauelements
ATE242757T1 (de) Verfahren zur herstellung mehrwertiger alkohole
DE69525273T2 (de) Verfahren zur Herstellung einer integrierten Schaltung
DE69707145D1 (de) Verfahren zur herstellung eines aldehyds
DE69120488D1 (de) Verfahren zur Herstellung eines Isolierungsbereiches von Halbleiterbauelementen
DE69726861D1 (de) Verfahren zur herstellung einer elektronenemittierenden vorrichtung
DE69736900D1 (de) Verfahren zur herstellung einer epitaxialscheibe aus silizium
DE19758977B8 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE59608080D1 (de) Verfahren zur herstellung einer integrierten cmos-schaltung
DE69920420D1 (de) Verfahren zur herstellung eines oxirans
DE69719711D1 (de) Verfahren zur Herstellung eines Bipolartransistors mit dielektrischer Isolation
DE59608424D1 (de) Verfahren zur Herstellung einer integrierten CMOS-Schaltung
DE69528543D1 (de) Verfahren zur Herstellung einer Antifuse
DE69722661D1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE69718134D1 (de) Verfahren zur Herstellung einer hochintegrierten Schaltung
DE69535348D1 (de) Verfahren zur Herstellung einer verbesserten dielektrischen Schicht für eine integrierte Schaltung