DE69940761D1 - Verfahren zur Transistorsherstellung - Google Patents

Verfahren zur Transistorsherstellung

Info

Publication number
DE69940761D1
DE69940761D1 DE69940761T DE69940761T DE69940761D1 DE 69940761 D1 DE69940761 D1 DE 69940761D1 DE 69940761 T DE69940761 T DE 69940761T DE 69940761 T DE69940761 T DE 69940761T DE 69940761 D1 DE69940761 D1 DE 69940761D1
Authority
DE
Germany
Prior art keywords
transistor fabrication
fabrication
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69940761T
Other languages
English (en)
Inventor
Rajesh Rengarajan
Jochen Beintner
Ulrike Gruening
Hans-Oliver Joachim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE69940761D1 publication Critical patent/DE69940761D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69940761T 1998-10-20 1999-09-09 Verfahren zur Transistorsherstellung Expired - Lifetime DE69940761D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/175,267 US6323103B1 (en) 1998-10-20 1998-10-20 Method for fabricating transistors

Publications (1)

Publication Number Publication Date
DE69940761D1 true DE69940761D1 (de) 2009-06-04

Family

ID=22639626

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69940761T Expired - Lifetime DE69940761D1 (de) 1998-10-20 1999-09-09 Verfahren zur Transistorsherstellung

Country Status (7)

Country Link
US (1) US6323103B1 (de)
EP (1) EP0996151B1 (de)
JP (1) JP2000124330A (de)
KR (1) KR100665428B1 (de)
CN (1) CN1294646C (de)
DE (1) DE69940761D1 (de)
TW (1) TW492153B (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323103B1 (en) 1998-10-20 2001-11-27 Siemens Aktiengesellschaft Method for fabricating transistors
US6809014B2 (en) * 2001-03-14 2004-10-26 Micron Technology, Inc. Method to fabricate surface p-channel CMOS
KR100438772B1 (ko) * 2001-08-07 2004-07-05 삼성전자주식회사 버블 디펙트를 방지할 수 있는 반도체 소자의 제조방법
US6734109B2 (en) * 2001-08-08 2004-05-11 International Business Machines Corporation Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon
US7064034B2 (en) 2002-07-02 2006-06-20 Sandisk Corporation Technique for fabricating logic elements using multiple gate layers
JP2004047608A (ja) * 2002-07-10 2004-02-12 Toshiba Corp 半導体装置及びその製造方法
US6773975B1 (en) * 2002-12-20 2004-08-10 Cypress Semiconductor Corporation Formation of a shallow trench isolation structure in integrated circuits
US7132323B2 (en) 2003-11-14 2006-11-07 International Business Machines Corporation CMOS well structure and method of forming the same
JP4671775B2 (ja) 2004-06-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100558047B1 (ko) * 2004-12-28 2006-03-07 주식회사 하이닉스반도체 반도체 장치의 제조방법
US7807523B2 (en) * 2005-07-01 2010-10-05 Synopsys, Inc. Sequential selective epitaxial growth
US7510928B2 (en) 2006-05-05 2009-03-31 Tru-Si Technologies, Inc. Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
KR101193453B1 (ko) * 2006-07-31 2012-10-24 비쉐이-실리코닉스 실리콘 카바이드 쇼트키 다이오드를 위한 몰리브덴 장벽 금속 및 제조방법
US7981800B1 (en) 2006-08-25 2011-07-19 Cypress Semiconductor Corporation Shallow trench isolation structures and methods for forming the same
CN101304000B (zh) * 2007-05-11 2010-07-07 中芯国际集成电路制造(上海)有限公司 一种改善集成电路制程中硅位错的方法
US8232177B2 (en) * 2009-09-30 2012-07-31 International Business Machines Corporation Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure
JP5557632B2 (ja) * 2010-07-14 2014-07-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
TWI614898B (zh) * 2013-12-06 2018-02-11 達爾國際股份有限公司 終止區結構及其製造方法
DE112019002436B4 (de) * 2018-06-18 2024-02-22 Hitachi Astemo, Ltd. Halbleitervorrichtung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151635A (en) 1971-06-16 1979-05-01 Signetics Corporation Method for making a complementary silicon gate MOS structure
US3892609A (en) 1971-10-07 1975-07-01 Hughes Aircraft Co Production of mis integrated devices with high inversion voltage to threshold voltage ratios
US4411058A (en) 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
JPS5919347A (ja) * 1982-07-23 1984-01-31 Matsushita Electric Ind Co Ltd 半導体集積回路およびその製造方法
US4599789A (en) 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4939154A (en) 1987-03-25 1990-07-03 Seiko Instruments Inc. Method of fabricating an insulated gate semiconductor device having a self-aligned gate
JP3125943B2 (ja) 1991-09-17 2001-01-22 日本電信電話株式会社 半導体装置の製造方法
US5874317A (en) * 1996-06-12 1999-02-23 Advanced Micro Devices, Inc. Trench isolation for integrated circuits
JP3658903B2 (ja) * 1996-12-25 2005-06-15 ノーリツ鋼機株式会社 写真フィルム
US5866465A (en) * 1997-04-03 1999-02-02 Micron Technology, Inc. Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass
TW441005B (en) * 1998-04-13 2001-06-16 United Microelectronics Corp Method for producing dual gate oxide layer device
US6323103B1 (en) 1998-10-20 2001-11-27 Siemens Aktiengesellschaft Method for fabricating transistors

Also Published As

Publication number Publication date
US6323103B1 (en) 2001-11-27
KR100665428B1 (ko) 2007-01-04
EP0996151A2 (de) 2000-04-26
KR20000029167A (ko) 2000-05-25
EP0996151B1 (de) 2009-04-22
EP0996151A3 (de) 2000-06-07
JP2000124330A (ja) 2000-04-28
TW492153B (en) 2002-06-21
CN1251470A (zh) 2000-04-26
CN1294646C (zh) 2007-01-10

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition