DE69939300D1 - Verfahren zur Herstellung einer Halbleiterstruktur mit einer leitenden Sicherung - Google Patents

Verfahren zur Herstellung einer Halbleiterstruktur mit einer leitenden Sicherung

Info

Publication number
DE69939300D1
DE69939300D1 DE69939300T DE69939300T DE69939300D1 DE 69939300 D1 DE69939300 D1 DE 69939300D1 DE 69939300 T DE69939300 T DE 69939300T DE 69939300 T DE69939300 T DE 69939300T DE 69939300 D1 DE69939300 D1 DE 69939300D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor structure
conductive fuse
fuse
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69939300T
Other languages
English (en)
Inventor
Kenneth C Arndt
Jeffrey P Gambino
Jack A Mandelma
Chandrasekhar Narayan
Raines F Schnabel
Ronald J Schutz
Dirk Tobben
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Application granted granted Critical
Publication of DE69939300D1 publication Critical patent/DE69939300D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • EFIXED CONSTRUCTIONS
    • E01CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
    • E01FADDITIONAL WORK, SUCH AS EQUIPPING ROADS OR THE CONSTRUCTION OF PLATFORMS, HELICOPTER LANDING STAGES, SIGNS, SNOW FENCES, OR THE LIKE
    • E01F9/00Arrangement of road signs or traffic signals; Arrangements for enforcing caution
    • EFIXED CONSTRUCTIONS
    • E01CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
    • E01HSTREET CLEANING; CLEANING OF PERMANENT WAYS; CLEANING BEACHES; DISPERSING OR PREVENTING FOG IN GENERAL CLEANING STREET OR RAILWAY FURNITURE OR TUNNEL WALLS
    • E01H1/00Removing undesirable matter from roads or like surfaces, with or without moistening of the surface
    • E01H1/02Brushing apparatus, e.g. with auxiliary instruments for mechanically loosening dirt
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Civil Engineering (AREA)
  • Structural Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69939300T 1998-06-26 1999-06-17 Verfahren zur Herstellung einer Halbleiterstruktur mit einer leitenden Sicherung Expired - Lifetime DE69939300D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/105,647 US6037648A (en) 1998-06-26 1998-06-26 Semiconductor structure including a conductive fuse and process for fabrication thereof

Publications (1)

Publication Number Publication Date
DE69939300D1 true DE69939300D1 (de) 2008-09-25

Family

ID=22307017

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69939300T Expired - Lifetime DE69939300D1 (de) 1998-06-26 1999-06-17 Verfahren zur Herstellung einer Halbleiterstruktur mit einer leitenden Sicherung

Country Status (6)

Country Link
US (1) US6037648A (de)
EP (1) EP0981161B1 (de)
JP (1) JP2000058655A (de)
KR (1) KR100350545B1 (de)
DE (1) DE69939300D1 (de)
TW (1) TW415077B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121074A (en) * 1998-11-05 2000-09-19 Siemens Aktiengesellschaft Fuse layout for improved fuse blow process window
US6180503B1 (en) * 1999-07-29 2001-01-30 Vanguard International Semiconductor Corporation Passivation layer etching process for memory arrays with fusible links
US6495901B2 (en) 2001-01-30 2002-12-17 Infineon Technologies Ag Multi-level fuse structure
US6566171B1 (en) 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
KR100425452B1 (ko) * 2001-07-04 2004-03-30 삼성전자주식회사 반도체 소자의 리페어 퓨즈 개구 방법
US6753210B2 (en) * 2002-09-17 2004-06-22 Taiwan Semiconductor Manufacturing Company Metal fuse for semiconductor devices
KR100695872B1 (ko) * 2005-06-22 2007-03-19 삼성전자주식회사 반도체 장치의 퓨즈 및 그 형성 방법
KR100703983B1 (ko) * 2006-02-07 2007-04-09 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20090045484A1 (en) 2007-08-16 2009-02-19 International Business Machines Corporation Methods and systems involving electrically reprogrammable fuses
KR20090128102A (ko) * 2008-06-10 2009-12-15 삼성전자주식회사 반도체 장치의 퓨즈 구조물 및 그의 형성 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200453A (ja) * 1983-04-27 1984-11-13 Hitachi Ltd 半導体装置の製造方法
JPS6065545A (ja) * 1983-09-21 1985-04-15 Hitachi Micro Comput Eng Ltd 半導体装置の製造方法
JPS6289338A (ja) * 1985-10-16 1987-04-23 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPS6480038A (en) * 1987-09-19 1989-03-24 Hitachi Ltd Manufacture of semiconductor integrated circuit device
US5300456A (en) * 1993-06-17 1994-04-05 Texas Instruments Incorporated Metal-to-metal antifuse structure
JPH0737988A (ja) * 1993-07-20 1995-02-07 Hitachi Ltd 半導体集積回路装置の製造方法
US5578517A (en) * 1994-10-24 1996-11-26 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming a highly transparent silicon rich nitride protective layer for a fuse window
US5550399A (en) * 1994-11-03 1996-08-27 Kabushiki Kaisha Toshiba Integrated circuit with windowed fuse element and contact pad
TW278229B (en) * 1994-12-29 1996-06-11 Siemens Ag Fuse structure for an integrated circuit device and method for manufacturing a fuse structure
EP0762498A3 (de) * 1995-08-28 1998-06-24 International Business Machines Corporation Fenster für Sicherung mit kontrollierter Sicherungsoxiddicke
US5723358A (en) * 1996-04-29 1998-03-03 Vlsi Technology, Inc. Method of manufacturing amorphous silicon antifuse structures

Also Published As

Publication number Publication date
EP0981161A2 (de) 2000-02-23
KR20000006375A (ko) 2000-01-25
TW415077B (en) 2000-12-11
EP0981161A3 (de) 2002-06-12
EP0981161B1 (de) 2008-08-13
KR100350545B1 (ko) 2002-08-28
US6037648A (en) 2000-03-14
JP2000058655A (ja) 2000-02-25

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition