DE69841823D1 - Verfahren zur Herstellung einer Oxid-Ummantelung in einem Graben in einem Halbleitersubstrat - Google Patents

Verfahren zur Herstellung einer Oxid-Ummantelung in einem Graben in einem Halbleitersubstrat

Info

Publication number
DE69841823D1
DE69841823D1 DE69841823T DE69841823T DE69841823D1 DE 69841823 D1 DE69841823 D1 DE 69841823D1 DE 69841823 T DE69841823 T DE 69841823T DE 69841823 T DE69841823 T DE 69841823T DE 69841823 D1 DE69841823 D1 DE 69841823D1
Authority
DE
Germany
Prior art keywords
trench
forming
semiconductor substrate
oxide cladding
cladding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69841823T
Other languages
English (en)
Inventor
Munir D Naeem
Matthew J Sendelbach
Ting-Hao Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Application granted granted Critical
Publication of DE69841823D1 publication Critical patent/DE69841823D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
DE69841823T 1998-01-28 1998-12-23 Verfahren zur Herstellung einer Oxid-Ummantelung in einem Graben in einem Halbleitersubstrat Expired - Lifetime DE69841823D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/014,805 US6066566A (en) 1998-01-28 1998-01-28 High selectivity collar oxide etch processes

Publications (1)

Publication Number Publication Date
DE69841823D1 true DE69841823D1 (de) 2010-09-23

Family

ID=21767856

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69841823T Expired - Lifetime DE69841823D1 (de) 1998-01-28 1998-12-23 Verfahren zur Herstellung einer Oxid-Ummantelung in einem Graben in einem Halbleitersubstrat

Country Status (6)

Country Link
US (1) US6066566A (de)
EP (1) EP0933804B1 (de)
JP (1) JP2994374B2 (de)
KR (1) KR100619104B1 (de)
DE (1) DE69841823D1 (de)
TW (1) TW459034B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652909B1 (ko) * 1998-03-06 2006-12-01 에이에스엠 아메리카, 인코포레이티드 하이 스텝 커버리지를 갖는 실리콘 증착 방법
US6399506B2 (en) * 1999-04-07 2002-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for planarizing an oxide layer
US6461529B1 (en) * 1999-04-26 2002-10-08 International Business Machines Corporation Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme
US6319788B1 (en) * 1999-12-14 2001-11-20 Infineon Technologies North America Corp. Semiconductor structure and manufacturing methods
KR100372894B1 (ko) * 2000-07-28 2003-02-19 삼성전자주식회사 반도체 장치의 콘택홀 형성 방법
DE60106011T2 (de) * 2001-07-23 2006-03-02 Infineon Technologies Ag Verfahren zur Bildung einer Isolierschicht und Verfahren zur Herstellung eines Grabenkondensators
US6559030B1 (en) * 2001-12-13 2003-05-06 International Business Machines Corporation Method of forming a recessed polysilicon filled trench
DE10225941A1 (de) * 2002-06-11 2004-01-08 Infineon Technologies Ag Verfahren zur Füllung von Graben- und Reliefgeometrien in Halbleiterstrukturen
US6706586B1 (en) * 2002-10-23 2004-03-16 International Business Machines Corporation Method of trench sidewall enhancement
DE102005045373A1 (de) 2005-09-22 2007-04-05 Siemens Ag Kathetervorrichtung
US7560360B2 (en) * 2006-08-30 2009-07-14 International Business Machines Corporation Methods for enhancing trench capacitance and trench capacitor
JP5309601B2 (ja) * 2008-02-22 2013-10-09 富士通セミコンダクター株式会社 半導体装置の製造方法
US9443730B2 (en) 2014-07-18 2016-09-13 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US9837271B2 (en) 2014-07-18 2017-12-05 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US10460932B2 (en) 2017-03-31 2019-10-29 Asm Ip Holding B.V. Semiconductor device with amorphous silicon filled gaps and methods for forming
TWI716818B (zh) * 2018-02-28 2021-01-21 美商應用材料股份有限公司 形成氣隙的系統及方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3033104B2 (ja) * 1989-11-17 2000-04-17 ソニー株式会社 エッチング方法
US5118384A (en) * 1990-04-03 1992-06-02 International Business Machines Corporation Reactive ion etching buffer mask
JP3038950B2 (ja) * 1991-02-12 2000-05-08 ソニー株式会社 ドライエッチング方法
JPH05152429A (ja) * 1991-11-28 1993-06-18 Nec Corp 半導体装置の製造方法
US5463225A (en) * 1992-06-01 1995-10-31 General Electric Company Solid state radiation imager with high integrity barrier layer and method of fabricating
US5283453A (en) * 1992-10-02 1994-02-01 International Business Machines Corporation Trench sidewall structure
US5468339A (en) * 1992-10-09 1995-11-21 Advanced Micro Devices, Inc. Plasma etch process
US5468340A (en) * 1992-10-09 1995-11-21 Gupta; Subhash Highly selective high aspect ratio oxide etch method and products made by the process
US5429978A (en) * 1994-06-22 1995-07-04 Industrial Technology Research Institute Method of forming a high density self-aligned stack in trench
US5677219A (en) * 1994-12-29 1997-10-14 Siemens Aktiengesellschaft Process for fabricating a DRAM trench capacitor
US5543348A (en) * 1995-03-29 1996-08-06 Kabushiki Kaisha Toshiba Controlled recrystallization of buried strap in a semiconductor memory device
EP0735581A1 (de) * 1995-03-30 1996-10-02 Siemens Aktiengesellschaft DRAM-Grabenkondensator mit isolierendem Ring
US5656535A (en) * 1996-03-04 1997-08-12 Siemens Aktiengesellschaft Storage node process for deep trench-based DRAM
EP0821409A3 (de) * 1996-07-23 2004-09-08 International Business Machines Corporation Ätzverfahren für Isolationsring einer DRAM-Zelle

Also Published As

Publication number Publication date
KR19990068156A (ko) 1999-08-25
KR100619104B1 (ko) 2006-09-01
EP0933804B1 (de) 2010-08-11
EP0933804A2 (de) 1999-08-04
JPH11265882A (ja) 1999-09-28
TW459034B (en) 2001-10-11
US6066566A (en) 2000-05-23
JP2994374B2 (ja) 1999-12-27
EP0933804A3 (de) 2001-01-10

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)