DE69835190D1 - Schaltung zur Taktrückgewinnung - Google Patents

Schaltung zur Taktrückgewinnung

Info

Publication number
DE69835190D1
DE69835190D1 DE69835190T DE69835190T DE69835190D1 DE 69835190 D1 DE69835190 D1 DE 69835190D1 DE 69835190 T DE69835190 T DE 69835190T DE 69835190 T DE69835190 T DE 69835190T DE 69835190 D1 DE69835190 D1 DE 69835190D1
Authority
DE
Germany
Prior art keywords
circuit
clock recovery
clock
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69835190T
Other languages
English (en)
Other versions
DE69835190T2 (de
Inventor
Takanori Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE69835190D1 publication Critical patent/DE69835190D1/de
Application granted granted Critical
Publication of DE69835190T2 publication Critical patent/DE69835190T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H04L7/0276—Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Dram (AREA)
DE69835190T 1997-08-12 1998-08-12 Schaltung zur Taktrückgewinnung Expired - Lifetime DE69835190T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21778297 1997-08-12
JP21778297A JP3039466B2 (ja) 1997-08-12 1997-08-12 クロックリカバリ回路

Publications (2)

Publication Number Publication Date
DE69835190D1 true DE69835190D1 (de) 2006-08-24
DE69835190T2 DE69835190T2 (de) 2007-07-05

Family

ID=16709653

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69835190T Expired - Lifetime DE69835190T2 (de) 1997-08-12 1998-08-12 Schaltung zur Taktrückgewinnung

Country Status (6)

Country Link
US (1) US6298104B1 (de)
EP (1) EP0897229B1 (de)
JP (1) JP3039466B2 (de)
KR (1) KR100324188B1 (de)
DE (1) DE69835190T2 (de)
TW (1) TW384572B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664792B1 (en) * 1998-09-29 2003-12-16 Intel Corporation Method and apparatus for battery power pre-check at system power-on
US6292507B1 (en) * 1999-09-01 2001-09-18 Lexmark International, Inc. Method and apparatus for compensating a spread spectrum clock generator
JP3386031B2 (ja) 2000-03-06 2003-03-10 日本電気株式会社 同期遅延回路及び半導体集積回路装置
KR100400225B1 (ko) * 2001-06-27 2003-10-01 삼성전자주식회사 잡음에 강한 버스트 모드 수신 장치 및 그의 클럭 신호 및데이타 복원 방법
US6630851B2 (en) * 2001-06-29 2003-10-07 Fujitsu Limited Low latency clock distribution
KR100467322B1 (ko) * 2002-09-18 2005-01-24 한국전자통신연구원 버스트 모드 클럭신호 재생장치 및 방법
US9946679B2 (en) 2011-10-05 2018-04-17 Analog Devices, Inc. Distributed audio coordination over a two-wire communication bus
US10649948B2 (en) * 2011-10-05 2020-05-12 Analog Devices, Inc. Two-wire communication systems and applications
CN105119794B (zh) 2011-10-05 2019-04-30 美国亚德诺半导体公司 用于高速数据和电力分配的双线通信系统
US9772665B2 (en) 2012-10-05 2017-09-26 Analog Devices, Inc. Power switching in a two-wire conductor system
US9059724B2 (en) * 2013-07-08 2015-06-16 Analog Devices, Inc. Differential decoder
JP2018074375A (ja) * 2016-10-28 2018-05-10 富士通株式会社 クロック再生回路，半導体集積回路装置およびｒｆタグ

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5127026A (en) * 1990-04-05 1992-06-30 Gazelle Microcircuits, Inc. Circuit and method for extracting clock signal from a serial data stream
US5579352A (en) * 1994-04-06 1996-11-26 National Semiconductor Corporation Simplified window de-skewing in a serial data receiver
JPH0818414A (ja) * 1994-04-26 1996-01-19 Hitachi Ltd 信号処理用遅延回路
US5566204A (en) * 1994-05-02 1996-10-15 Raytheon Company Fast acquisition clock recovery system
US5455540A (en) * 1994-10-26 1995-10-03 Cypress Semiconductor Corp. Modified bang-bang phase detector with ternary output
JPH08204524A (ja) 1995-01-27 1996-08-09 Hitachi Ltd クロック位相制御回路とこれを用いたデジタル信号処理回路
US5696800A (en) * 1995-03-22 1997-12-09 Intel Corporation Dual tracking differential manchester decoder and clock recovery circuit
JPH08330949A (ja) 1995-06-05 1996-12-13 Sharp Corp 同期クロック信号の発生装置

Also Published As

Publication number Publication date
JP3039466B2 (ja) 2000-05-08
TW384572B (en) 2000-03-11
EP0897229B1 (de) 2006-07-12
KR100324188B1 (ko) 2002-06-22
DE69835190T2 (de) 2007-07-05
EP0897229A2 (de) 1999-02-17
EP0897229A3 (de) 2003-06-18
KR19990023499A (ko) 1999-03-25
US6298104B1 (en) 2001-10-02
JPH1168729A (ja) 1999-03-09

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