DE69724245D1 - Verfahren zur plazierung von taktpuffern in einem taktverteilungssystem - Google Patents

Verfahren zur plazierung von taktpuffern in einem taktverteilungssystem

Info

Publication number
DE69724245D1
DE69724245D1 DE69724245T DE69724245T DE69724245D1 DE 69724245 D1 DE69724245 D1 DE 69724245D1 DE 69724245 T DE69724245 T DE 69724245T DE 69724245 T DE69724245 T DE 69724245T DE 69724245 D1 DE69724245 D1 DE 69724245D1
Authority
DE
Germany
Prior art keywords
clock
distribution system
placing
buffers
clock distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69724245T
Other languages
English (en)
Other versions
DE69724245T2 (de
Inventor
M Scherer
Frederick Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69724245D1 publication Critical patent/DE69724245D1/de
Application granted granted Critical
Publication of DE69724245T2 publication Critical patent/DE69724245T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
DE69724245T 1996-04-15 1997-04-15 Verfahren zur plazierung von taktpuffern in einem taktverteilungssystem Expired - Lifetime DE69724245T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/632,966 US5790841A (en) 1996-04-15 1996-04-15 Method for placement of clock buffers in a clock distribution system
US632966 1996-04-15
PCT/US1997/005422 WO1997039414A2 (en) 1996-04-15 1997-04-15 Method for placement of clock buffers in a clock distribution system

Publications (2)

Publication Number Publication Date
DE69724245D1 true DE69724245D1 (de) 2003-09-25
DE69724245T2 DE69724245T2 (de) 2004-06-03

Family

ID=24537725

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69724245T Expired - Lifetime DE69724245T2 (de) 1996-04-15 1997-04-15 Verfahren zur plazierung von taktpuffern in einem taktverteilungssystem

Country Status (5)

Country Link
US (2) US5790841A (de)
EP (1) EP0894308B1 (de)
AU (1) AU2433397A (de)
DE (1) DE69724245T2 (de)
WO (1) WO1997039414A2 (de)

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US6014038A (en) * 1997-03-21 2000-01-11 Lightspeed Semiconductor Corporation Function block architecture for gate array
US5966522A (en) * 1997-03-28 1999-10-12 International Business Machines Corporation Multi-phase clock distribution method and system for complex integrated-circuit devices
JP3000961B2 (ja) * 1997-06-06 2000-01-17 日本電気株式会社 半導体集積回路
US6397169B1 (en) * 1998-06-30 2002-05-28 Synopsys, Inc. Adaptive cell separation and circuit changes driven by maximum capacitance rules
JP3052951B1 (ja) * 1999-02-16 2000-06-19 日本電気株式会社 クロックツリ―シンセシス配置配線装置および方法
US6311314B1 (en) * 1999-04-27 2001-10-30 Hewlett-Packard Company System and method for evaluating the loading of a clock driver
JP2001117967A (ja) * 1999-10-22 2001-04-27 Nec Corp クロック分配設計方法、及び、木構造のバッファ回路
US6434731B1 (en) 1999-10-26 2002-08-13 International Business Machines Corporation Automated placement of signal distribution to diminish skew among same capacitance targets in integrated circuits
US6463547B1 (en) * 1999-12-08 2002-10-08 Compaq Information Technologies Group Lp Dual on-chip and in-package clock distribution system
US6966045B2 (en) * 1999-12-27 2005-11-15 Kabushiki Kaisha Toshiba Method and computer program product for estimating wire loads
US6532580B1 (en) * 2000-02-18 2003-03-11 Hewlett-Packard Company In-place method for inserting repeater buffers in an integrated circuit
US6408426B1 (en) * 2000-02-19 2002-06-18 Hewlett-Packard Company Method for determining locations of interconnect repeater farms during physical design of integrated circuits
JP2001257268A (ja) * 2000-03-13 2001-09-21 Nec Microsystems Ltd レイアウト方法
US6513149B1 (en) * 2000-03-31 2003-01-28 International Business Machines Corporation Routing balanced clock signals
JP3420195B2 (ja) * 2000-09-26 2003-06-23 エヌイーシーマイクロシステム株式会社 クロック配線の設計方法
US6480994B1 (en) * 2001-02-15 2002-11-12 Lsi Logic Corporation Balanced clock placement for integrated circuits containing megacells
US6594807B1 (en) * 2001-03-06 2003-07-15 Lsi Logic Corporation Method for minimizing clock skew for an integrated circuit
JP5193406B2 (ja) * 2001-06-13 2013-05-08 富士通セミコンダクター株式会社 クロック分配回路の設計方法，設計装置および設計プログラム並びに同プログラムを記録したコンピュータ読取可能な記録媒体
CN100378734C (zh) * 2001-08-29 2008-04-02 英芬能技术公司 集成电路芯片设计
US20030101423A1 (en) * 2001-11-29 2003-05-29 Tyler Thorp Clock grid skew reduction using a wire tree architecture
US6728944B2 (en) * 2001-11-29 2004-04-27 Intenational Business Machines Corporation Method, system, and computer program product for improving wireability near dense clock nets
KR100429891B1 (ko) * 2002-07-29 2004-05-03 삼성전자주식회사 클럭 스큐를 최소화하기 위한 격자형 클럭 분배망
AU2002357880A1 (en) * 2002-12-17 2004-07-29 International Business Machines Corporation Asic clock floor planning method and structure
US7096442B2 (en) * 2003-07-10 2006-08-22 Lsi Logic Corporation Optimizing IC clock structures by minimizing clock uncertainty
US20060053403A1 (en) * 2004-09-09 2006-03-09 Cowan Christopher R System and method for routing clock signals from a clock trunk
JP4645238B2 (ja) * 2005-03-09 2011-03-09 日本電気株式会社 半導体装置
US20080155490A1 (en) * 2006-12-22 2008-06-26 Tianwen Tang Method for Reducing Coupling Noise, Reducing Signal Skew, and Saving Layout Area for an Integrated Circuit
US7979732B2 (en) * 2007-07-03 2011-07-12 International Business Machines Corporation Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit
US8010926B2 (en) * 2008-01-30 2011-08-30 International Business Machines Corporation Clock power minimization with regular physical placement of clock repeater components
US8104014B2 (en) * 2008-01-30 2012-01-24 International Business Machines Corporation Regular local clock buffer placement and latch clustering by iterative optimization
JP5401256B2 (ja) * 2009-10-16 2014-01-29 ルネサスエレクトロニクス株式会社 半導体装置の設計方法
US8239799B2 (en) * 2010-01-07 2012-08-07 Freescale Semiconductor, Inc. Placing filler cells in device design based on designation of sensitive feature in standard cell
US8593177B2 (en) 2012-03-19 2013-11-26 Advanced Micro Devices, Inc. Integrated circuit with timing aware clock-tree and method for designing such an integrated circuit
US9372499B2 (en) 2014-01-21 2016-06-21 Advanced Micro Devices, Inc. Low insertion delay clock doubler and integrated circuit clock distribution system using same
US9319037B2 (en) 2014-02-03 2016-04-19 Advanced Micro Devices, Inc. Self-adjusting clock doubler and integrated circuit clock distribution system using same
US9858177B2 (en) 2015-10-30 2018-01-02 International Business Machines Corporation Automated test generation for multi-interface enterprise virtualization management environment
US9892222B1 (en) * 2016-08-11 2018-02-13 International Business Machines Corporation Automated attribute propagation and hierarchical consistency checking for non-standard extensions
US10572373B2 (en) 2017-04-20 2020-02-25 International Business Machines Corporation Automated test generation for multi-interface and multi-platform enterprise virtualization management environment
US10642949B2 (en) * 2017-06-07 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Cell placement site optimization
DE102017127276A1 (de) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek
US11615230B2 (en) 2020-12-17 2023-03-28 Advanced Micro Devices, Inc. Wide range clock monitor system
US20230075565A1 (en) * 2021-09-07 2023-03-09 International Business Machines Corporation Signal pre-routing in an integrated circuit design

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Publication number Priority date Publication date Assignee Title
US5012427A (en) * 1988-01-30 1991-04-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method of manufacturing the same
JPH0736422B2 (ja) * 1988-08-19 1995-04-19 株式会社東芝 クロック供給回路
JPH0824143B2 (ja) * 1989-02-08 1996-03-06 株式会社東芝 集積回路の配置配線方式
JP2756325B2 (ja) * 1989-12-07 1998-05-25 株式会社日立製作所 クロック供給回路
JP2695078B2 (ja) * 1991-06-10 1997-12-24 株式会社東芝 データ処理装置クロック信号の分配方法
US5430397A (en) * 1993-01-27 1995-07-04 Hitachi, Ltd. Intra-LSI clock distribution circuit
US5467033A (en) * 1993-07-02 1995-11-14 Tandem Computers Incorporated Chip clock skew control method and apparatus
US5481209A (en) * 1993-09-20 1996-01-02 Lsi Logic Corporation Clock distribution and control in an integrated circuit
JP3112784B2 (ja) * 1993-09-24 2000-11-27 日本電気株式会社 クロック信号分配回路
JP2540762B2 (ja) * 1993-11-10 1996-10-09 日本電気株式会社 クロック信号供給方法
US5564022A (en) * 1994-02-09 1996-10-08 Intel Corporation Method and apparatus for automatically inserting clock buffers into a logic block to reduce clock skew
US5774371A (en) * 1994-08-03 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and layout designing method for the same
US5656963A (en) * 1995-09-08 1997-08-12 International Business Machines Corporation Clock distribution network for reducing clock skew
US5880607A (en) * 1996-05-01 1999-03-09 Sun Microsystems, Inc. Clock distribution network with modular buffers

Also Published As

Publication number Publication date
EP0894308A2 (de) 1999-02-03
EP0894308B1 (de) 2003-08-20
US5790841A (en) 1998-08-04
WO1997039414A3 (en) 1998-03-12
AU2433397A (en) 1997-11-07
DE69724245T2 (de) 2004-06-03
WO1997039414A2 (en) 1997-10-23
US6266803B1 (en) 2001-07-24

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