DE69708879D1 - Z-achsenzwischenverbindungsverfahren und schaltung - Google Patents
Z-achsenzwischenverbindungsverfahren und schaltungInfo
- Publication number
- DE69708879D1 DE69708879D1 DE69708879T DE69708879T DE69708879D1 DE 69708879 D1 DE69708879 D1 DE 69708879D1 DE 69708879 T DE69708879 T DE 69708879T DE 69708879 T DE69708879 T DE 69708879T DE 69708879 D1 DE69708879 D1 DE 69708879D1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- connection method
- intermediate connection
- axis intermediate
- axis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4635—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01021—Scandium [Sc]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/685,125 US5873161A (en) | 1996-07-23 | 1996-07-23 | Method of making a Z axis interconnect circuit |
PCT/US1997/011587 WO1998004107A1 (en) | 1996-07-23 | 1997-07-01 | Z-axis interconnect method and circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69708879D1 true DE69708879D1 (de) | 2002-01-17 |
DE69708879T2 DE69708879T2 (de) | 2002-08-08 |
Family
ID=24750877
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69708879T Expired - Fee Related DE69708879T2 (de) | 1996-07-23 | 1997-07-01 | Z-achsenzwischenverbindungsverfahren und schaltung |
Country Status (6)
Country | Link |
---|---|
US (1) | US5873161A (de) |
EP (1) | EP0914757B1 (de) |
JP (1) | JP2000514955A (de) |
KR (1) | KR20000067943A (de) |
DE (1) | DE69708879T2 (de) |
WO (1) | WO1998004107A1 (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6097099A (en) * | 1995-10-20 | 2000-08-01 | Texas Instruments Incorporated | Electro-thermal nested die-attach design |
US5776824A (en) * | 1995-12-22 | 1998-07-07 | Micron Technology, Inc. | Method for producing laminated film/metal structures for known good die ("KG") applications |
US5996221A (en) * | 1996-12-12 | 1999-12-07 | Lucent Technologies Inc. | Method for thermocompression bonding structures |
JP3094948B2 (ja) * | 1997-05-26 | 2000-10-03 | 日本電気株式会社 | 半導体素子搭載用回路基板とその半導体素子との接続方法 |
US6226862B1 (en) | 1998-04-30 | 2001-05-08 | Sheldahl, Inc. | Method for manufacturing printed circuit board assembly |
JP3250216B2 (ja) * | 1998-08-13 | 2002-01-28 | ソニーケミカル株式会社 | フレキシブルプリント配線板及びその製造方法 |
JP3428488B2 (ja) * | 1999-04-12 | 2003-07-22 | 株式会社村田製作所 | 電子部品の製造方法 |
SE521704C2 (sv) * | 1999-10-29 | 2003-11-25 | Ericsson Telefon Ab L M | Förfarande för att anordna koppling mellan olika skikt i ett kretskort samt kretskort |
EP1173051B1 (de) * | 2000-01-25 | 2007-05-23 | Sony Chemical & Information Device Corporation | Flexible gedruckte leiterplatte und ihre herstellungsmethode |
JP2001230551A (ja) * | 2000-02-14 | 2001-08-24 | Ibiden Co Ltd | プリント配線板並びに多層プリント配線板及びその製造方法 |
US6638847B1 (en) * | 2000-04-19 | 2003-10-28 | Advanced Interconnect Technology Ltd. | Method of forming lead-free bump interconnections |
JP4593752B2 (ja) * | 2000-09-29 | 2010-12-08 | イビデン株式会社 | 多層回路基板の製造方法 |
US6703566B1 (en) * | 2000-10-25 | 2004-03-09 | Sae Magnetics (H.K.), Ltd. | Bonding structure for a hard disk drive suspension using anisotropic conductive film |
SE520174C2 (sv) * | 2000-12-29 | 2003-06-03 | Ericsson Telefon Ab L M | Förfarande och anordning för anordnande av vior i mönsterkort |
US6866741B2 (en) * | 2001-01-08 | 2005-03-15 | Fujitsu Limited | Method for joining large substrates |
US6634543B2 (en) * | 2002-01-07 | 2003-10-21 | International Business Machines Corporation | Method of forming metallic z-interconnects for laminate chip packages and boards |
WO2003061949A1 (en) * | 2002-01-18 | 2003-07-31 | Avery Dennison Corporation | Sheet having microsized architecture |
US20030155656A1 (en) * | 2002-01-18 | 2003-08-21 | Chiu Cindy Chia-Wen | Anisotropically conductive film |
WO2003062133A2 (en) * | 2002-01-18 | 2003-07-31 | Avery Dennison Corporation | Covered microchamber structures |
US20040040651A1 (en) * | 2002-08-28 | 2004-03-04 | Kuraray Co., Ltd. | Multi-layer circuit board and method of making the same |
US20060249303A1 (en) * | 2005-05-04 | 2006-11-09 | Johnson Kenneth W | Connectorless electronic interface between rigid and compliant members using hemi-ellipsoidal surface features |
US7663216B2 (en) * | 2005-11-02 | 2010-02-16 | Sandisk Corporation | High density three dimensional semiconductor die package |
KR100719905B1 (ko) * | 2005-12-29 | 2007-05-18 | 삼성전자주식회사 | Sn-Bi계 솔더 합금 및 이를 이용한 반도체 소자 |
US7710045B2 (en) * | 2006-03-17 | 2010-05-04 | 3M Innovative Properties Company | Illumination assembly with enhanced thermal conductivity |
JP4881376B2 (ja) * | 2006-04-24 | 2012-02-22 | アルプス電気株式会社 | 配線基板の製造方法 |
US7666008B2 (en) * | 2006-09-22 | 2010-02-23 | Onanon, Inc. | Conductive elastomeric and mechanical pin and contact system |
KR100771467B1 (ko) * | 2006-10-30 | 2007-10-30 | 삼성전기주식회사 | 회로기판 및 그 제조방법 |
US7981703B2 (en) * | 2007-05-29 | 2011-07-19 | Occam Portfolio Llc | Electronic assemblies without solder and methods for their manufacture |
US7892441B2 (en) * | 2007-06-01 | 2011-02-22 | General Dynamics Advanced Information Systems, Inc. | Method and apparatus to change solder pad size using a differential pad plating |
US9442133B1 (en) * | 2011-08-21 | 2016-09-13 | Bruker Nano Inc. | Edge electrode for characterization of semiconductor wafers |
US9176167B1 (en) * | 2011-08-21 | 2015-11-03 | Bruker Nano Inc. | Probe and method of manufacture for semiconductor wafer characterization |
FR3057103B1 (fr) * | 2016-09-30 | 2022-11-11 | Safran Electronics & Defense | Dispositif electronique comprenant un module raccorde a un pcb et unite electronique comportant un tel dispositif |
US10178755B2 (en) * | 2017-05-09 | 2019-01-08 | Unimicron Technology Corp. | Circuit board stacked structure and method for forming the same |
US11171101B2 (en) * | 2020-03-31 | 2021-11-09 | Raytheon Company | Process for removing bond film from cavities in printed circuit boards |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3646670A (en) * | 1968-07-19 | 1972-03-07 | Hitachi Chemical Co Ltd | Method for connecting conductors |
US3832769A (en) * | 1971-05-26 | 1974-09-03 | Minnesota Mining & Mfg | Circuitry and method |
GB1353671A (en) * | 1971-06-10 | 1974-05-22 | Int Computers Ltd | Methods of forming circuit interconnections |
US4648179A (en) * | 1983-06-30 | 1987-03-10 | International Business Machines Corporation | Process of making interconnection structure for semiconductor device |
JPS6442193A (en) * | 1987-08-07 | 1989-02-14 | Rohm Co Ltd | Wiring board |
CA1307594C (en) * | 1988-06-10 | 1992-09-15 | Kenneth B. Gilleo | Multilayer electronic circuit and method of manufacture |
US5031308A (en) * | 1988-12-29 | 1991-07-16 | Japan Radio Co., Ltd. | Method of manufacturing multilayered printed-wiring-board |
US5046238A (en) * | 1990-03-15 | 1991-09-10 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
JPH0567869A (ja) * | 1991-09-05 | 1993-03-19 | Matsushita Electric Ind Co Ltd | 電装部品接合方法並びにモジユール及び多層基板 |
US5282312A (en) * | 1991-12-31 | 1994-02-01 | Tessera, Inc. | Multi-layer circuit construction methods with customization features |
US5309629A (en) * | 1992-09-01 | 1994-05-10 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
JP3057924B2 (ja) * | 1992-09-22 | 2000-07-04 | 松下電器産業株式会社 | 両面プリント基板およびその製造方法 |
US5401913A (en) * | 1993-06-08 | 1995-03-28 | Minnesota Mining And Manufacturing Company | Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board |
US5736681A (en) * | 1993-09-03 | 1998-04-07 | Kabushiki Kaisha Toshiba | Printed wiring board having an interconnection penetrating an insulating layer |
US5487215A (en) * | 1994-02-18 | 1996-01-30 | Multifastener Corporation | Self-adjusting head |
CA2157259C (en) * | 1994-08-31 | 2000-08-29 | Koetsu Tamura | Electronic device assembly and a manufacturing method of the same |
-
1996
- 1996-07-23 US US08/685,125 patent/US5873161A/en not_active Expired - Fee Related
-
1997
- 1997-07-01 KR KR1019997000428A patent/KR20000067943A/ko not_active Application Discontinuation
- 1997-07-01 WO PCT/US1997/011587 patent/WO1998004107A1/en not_active Application Discontinuation
- 1997-07-01 JP JP10506067A patent/JP2000514955A/ja active Pending
- 1997-07-01 EP EP97933265A patent/EP0914757B1/de not_active Expired - Lifetime
- 1997-07-01 DE DE69708879T patent/DE69708879T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0914757A1 (de) | 1999-05-12 |
KR20000067943A (ko) | 2000-11-25 |
EP0914757B1 (de) | 2001-12-05 |
JP2000514955A (ja) | 2000-11-07 |
US5873161A (en) | 1999-02-23 |
WO1998004107A1 (en) | 1998-01-29 |
DE69708879T2 (de) | 2002-08-08 |
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