DE69708845D1 - Halbleitervorrichtung mit komplementärem Takt und Schaltung zur Detektion des Eingangssignalzustandes dafür - Google Patents

Halbleitervorrichtung mit komplementärem Takt und Schaltung zur Detektion des Eingangssignalzustandes dafür

Info

Publication number
DE69708845D1
DE69708845D1 DE69708845T DE69708845T DE69708845D1 DE 69708845 D1 DE69708845 D1 DE 69708845D1 DE 69708845 T DE69708845 T DE 69708845T DE 69708845 T DE69708845 T DE 69708845T DE 69708845 D1 DE69708845 D1 DE 69708845D1
Authority
DE
Germany
Prior art keywords
detecting
circuit
semiconductor device
input signal
signal state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69708845T
Other languages
English (en)
Other versions
DE69708845T2 (de
Inventor
Masao Taguchi
Hiroyoshi Tomita
Yasurou Matsuzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69708845D1 publication Critical patent/DE69708845D1/de
Publication of DE69708845T2 publication Critical patent/DE69708845T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
DE69708845T 1997-04-21 1997-09-29 Halbleitervorrichtung mit komplementärem Takt und Schaltung zur Detektion des Eingangssignalzustandes dafür Expired - Lifetime DE69708845T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10337597 1997-04-21

Publications (2)

Publication Number Publication Date
DE69708845D1 true DE69708845D1 (de) 2002-01-17
DE69708845T2 DE69708845T2 (de) 2002-04-11

Family

ID=14352362

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69708845T Expired - Lifetime DE69708845T2 (de) 1997-04-21 1997-09-29 Halbleitervorrichtung mit komplementärem Takt und Schaltung zur Detektion des Eingangssignalzustandes dafür

Country Status (4)

Country Link
EP (1) EP0878908B1 (de)
KR (1) KR100269569B1 (de)
DE (1) DE69708845T2 (de)
TW (1) TW367654B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100513807B1 (ko) * 2000-11-30 2005-09-13 주식회사 하이닉스반도체 지연고정루프 회로

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173949A (ja) * 1984-02-20 1985-09-07 Fujitsu Ltd クロツク供給方式
JPH01164142A (ja) * 1987-12-19 1989-06-28 Fujitsu Ltd クロック同期方式
JPH02174421A (ja) * 1988-12-27 1990-07-05 Nec Corp Ｐｌｌ回路
US5101127A (en) * 1989-03-23 1992-03-31 Texas Instruments Incorporated Digital integrated frequency discriminator of external clock and internally generated signal backup
US4982116A (en) * 1989-12-26 1991-01-01 Linear Technology Corporation Clock selection circuit
US5418472A (en) * 1993-10-08 1995-05-23 Advanced Micro Devices, Inc. Input level detection circuit

Also Published As

Publication number Publication date
EP0878908B1 (de) 2001-12-05
TW367654B (en) 1999-08-21
KR100269569B1 (ko) 2000-10-16
DE69708845T2 (de) 2002-04-11
KR19980079412A (ko) 1998-11-25
EP0878908A3 (de) 1999-01-20
EP0878908A2 (de) 1998-11-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE