DE69636268D1 - Informationsverarbeitungsgerät zur Datenübertragung zu/von mehreren Registern durch Kurzwortbefehle - Google Patents

Informationsverarbeitungsgerät zur Datenübertragung zu/von mehreren Registern durch Kurzwortbefehle

Info

Publication number
DE69636268D1
DE69636268D1 DE69636268T DE69636268T DE69636268D1 DE 69636268 D1 DE69636268 D1 DE 69636268D1 DE 69636268 T DE69636268 T DE 69636268T DE 69636268 T DE69636268 T DE 69636268T DE 69636268 D1 DE69636268 D1 DE 69636268D1
Authority
DE
Germany
Prior art keywords
processing apparatus
information processing
data transmission
multiple registers
short word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69636268T
Other languages
English (en)
Other versions
DE69636268T2 (de
Inventor
Nobuo Higaki
Nobuki Tominaga
Shinya Miyaji
Shuichi Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69636268D1 publication Critical patent/DE69636268D1/de
Publication of DE69636268T2 publication Critical patent/DE69636268T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
DE69636268T 1995-09-22 1996-09-20 Informationsverarbeitungsgerät zur Datenübertragung zu/von mehreren Registern durch Kurzwortbefehle Expired - Lifetime DE69636268T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24475795 1995-09-22
JP7244757A JP2889845B2 (ja) 1995-09-22 1995-09-22 情報処理装置

Publications (2)

Publication Number Publication Date
DE69636268D1 true DE69636268D1 (de) 2006-08-03
DE69636268T2 DE69636268T2 (de) 2006-11-09

Family

ID=17123452

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69636268T Expired - Lifetime DE69636268T2 (de) 1995-09-22 1996-09-20 Informationsverarbeitungsgerät zur Datenübertragung zu/von mehreren Registern durch Kurzwortbefehle

Country Status (7)

Country Link
US (1) US5796970A (de)
EP (1) EP0764900B1 (de)
JP (1) JP2889845B2 (de)
KR (1) KR100413651B1 (de)
CN (1) CN1146784C (de)
DE (1) DE69636268T2 (de)
TW (1) TW430769B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3630804B2 (ja) * 1995-11-30 2005-03-23 三洋電機株式会社 データ処理装置
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US6389449B1 (en) 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
JP2001202243A (ja) * 1999-04-30 2001-07-27 Hitachi Ltd データ処理装置
EP1050797A1 (de) * 1999-05-03 2000-11-08 STMicroelectronics S.A. Befehlausführung in einem Rechnersystem
JP2001236206A (ja) * 1999-10-01 2001-08-31 Hitachi Ltd データのロード方法及びその記憶方法、データワードのロード方法及びその記憶方法、並びに、浮動小数点数の比較方法
AU2001226324A1 (en) * 2000-01-18 2001-07-31 Clearwater Networks, Inc. Method and apparatus for improved computer load and store operations
WO2002006959A1 (en) 2000-07-14 2002-01-24 Clearwater Networks, Inc. Instruction fetch and dispatch in multithreaded system
US6820191B2 (en) * 2000-12-05 2004-11-16 Faraday Technology Corp. Apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor
KR100379151B1 (ko) * 2001-01-04 2003-04-07 패러데이 테크놀로지 코퍼레이션 프로세서 내부의 블록 데이터 전송 명령을 실행하는 장치및 방법
GB2397667A (en) * 2003-01-27 2004-07-28 Imagination Tech Ltd Multiple register load using a very long instruction word
GB2402759B (en) * 2003-06-12 2005-12-21 Advanced Risc Mach Ltd Data processing apparatus and method for transferring data values between a register file and a memory
GB2402763B (en) * 2003-06-13 2006-03-01 Advanced Risc Mach Ltd Data access program instruction encoding
US20230051855A1 (en) * 2021-08-13 2023-02-16 Infineon Technologies Ag Call and return instructions for configurable register context save and restore

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4109310A (en) * 1973-08-06 1978-08-22 Xerox Corporation Variable field length addressing system having data byte interchange
US4241399A (en) * 1978-10-25 1980-12-23 Digital Equipment Corporation Calling instructions for a data processing system
US4338663A (en) * 1978-10-25 1982-07-06 Digital Equipment Corporation Calling instructions for a data processing system
JPS6151243A (ja) * 1984-08-20 1986-03-13 Toshiba Corp レジスタ式演算処理装置
JP2545789B2 (ja) * 1986-04-14 1996-10-23 株式会社日立製作所 情報処理装置
JP2902402B2 (ja) * 1987-09-30 1999-06-07 三菱電機株式会社 データ処理装置
JPH0748179B2 (ja) * 1988-10-12 1995-05-24 日本電気株式会社 データ処理装置
JPH0353328A (ja) * 1989-07-20 1991-03-07 Hitachi Ltd レジスタ退避回復方法ならびに処理装置
JP2504235B2 (ja) * 1989-11-16 1996-06-05 三菱電機株式会社 デ―タ処理装置
JPH03260727A (ja) * 1990-03-09 1991-11-20 Mitsubishi Electric Corp レジスタ指定装置
JP2669158B2 (ja) * 1991-01-22 1997-10-27 三菱電機株式会社 データ処理装置
JP3110866B2 (ja) * 1992-06-01 2000-11-20 株式会社東芝 マイクロプロセッサ
JP3220881B2 (ja) * 1992-12-29 2001-10-22 株式会社日立製作所 情報処理装置
WO1996008767A2 (en) * 1994-09-16 1996-03-21 Philips Electronics N.V. Microcontroller system with a multiple-register stacking instruction

Also Published As

Publication number Publication date
KR970016973A (ko) 1997-04-28
CN1153346A (zh) 1997-07-02
TW430769B (en) 2001-04-21
DE69636268T2 (de) 2006-11-09
KR100413651B1 (ko) 2004-05-20
EP0764900A2 (de) 1997-03-26
EP0764900B1 (de) 2006-06-21
CN1146784C (zh) 2004-04-21
JP2889845B2 (ja) 1999-05-10
EP0764900A3 (de) 2002-11-06
JPH0991134A (ja) 1997-04-04
US5796970A (en) 1998-08-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP