DE69632655D1 - Pipeline-Datenverarbeitungsanordnung zur Durchführung einer Mehrzahl von untereinander datenabhängigen Datenprozessen - Google Patents

Pipeline-Datenverarbeitungsanordnung zur Durchführung einer Mehrzahl von untereinander datenabhängigen Datenprozessen

Info

Publication number
DE69632655D1
DE69632655D1 DE69632655T DE69632655T DE69632655D1 DE 69632655 D1 DE69632655 D1 DE 69632655D1 DE 69632655 T DE69632655 T DE 69632655T DE 69632655 T DE69632655 T DE 69632655T DE 69632655 D1 DE69632655 D1 DE 69632655D1
Authority
DE
Germany
Prior art keywords
data
mutually
processing arrangement
pipeline
processes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69632655T
Other languages
English (en)
Other versions
DE69632655T2 (de
Inventor
Masaitsu Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69632655D1 publication Critical patent/DE69632655D1/de
Application granted granted Critical
Publication of DE69632655T2 publication Critical patent/DE69632655T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
DE69632655T 1995-03-03 1996-03-01 Pipeline-Datenverarbeitungsanordnung zur Durchführung einer Mehrzahl von untereinander datenabhängigen Datenprozessen Expired - Lifetime DE69632655T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4386095 1995-03-03
JP4386095 1995-03-03

Publications (2)

Publication Number Publication Date
DE69632655D1 true DE69632655D1 (de) 2004-07-15
DE69632655T2 DE69632655T2 (de) 2004-09-30

Family

ID=12675461

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69632655T Expired - Lifetime DE69632655T2 (de) 1995-03-03 1996-03-01 Pipeline-Datenverarbeitungsanordnung zur Durchführung einer Mehrzahl von untereinander datenabhängigen Datenprozessen

Country Status (5)

Country Link
US (1) US5822561A (de)
EP (1) EP0730223B1 (de)
KR (1) KR0180580B1 (de)
DE (1) DE69632655T2 (de)
TW (1) TW448403B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778250A (en) * 1994-05-23 1998-07-07 Cirrus Logic, Inc. Method and apparatus for dynamically adjusting the number of stages of a multiple stage pipeline
US6615338B1 (en) * 1998-12-03 2003-09-02 Sun Microsystems, Inc. Clustered architecture in a VLIW processor
US7114056B2 (en) 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor
US6279100B1 (en) 1998-12-03 2001-08-21 Sun Microsystems, Inc. Local stall control method and structure in a microprocessor
US7117342B2 (en) 1998-12-03 2006-10-03 Sun Microsystems, Inc. Implicitly derived register specifiers in a processor
US6427159B1 (en) 1999-08-03 2002-07-30 Koninklijke Philips Electronics N.V. Arithmetic unit, digital signal processor, method of scheduling multiplication in an arithmetic unit, method of selectively delaying adding and method of selectively adding during a first or second clock cycle
EP1113357A3 (de) * 1999-12-30 2001-11-14 Texas Instruments Incorporated Verfahren und Vorrichtung zur Durchführung eines Verzögerungsbefehls mit veränderlicher Verzögerungszeit
US6862677B1 (en) * 2000-02-16 2005-03-01 Koninklijke Philips Electronics N.V. System and method for eliminating write back to register using dead field indicator
US6629167B1 (en) * 2000-02-18 2003-09-30 Hewlett-Packard Development Company, L.P. Pipeline decoupling buffer for handling early data and late data
AU2001264560A1 (en) * 2000-06-02 2001-12-17 Sun Microsystems, Inc. Synchronizing partially pipelined instructions in vliw processors
US7093107B2 (en) * 2000-12-29 2006-08-15 Stmicroelectronics, Inc. Bypass circuitry for use in a pipelined processor
JP2007528549A (ja) * 2004-03-10 2007-10-11 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子回路
JP2010198128A (ja) * 2009-02-23 2010-09-09 Toshiba Corp プロセッサシステム
KR20120017294A (ko) 2010-08-18 2012-02-28 삼성전자주식회사 어플리케이션을 효율적으로 처리하는 스케쥴링 시스템 및 스케쥴링 방법
US8958550B2 (en) * 2011-09-13 2015-02-17 Combined Conditional Access Development & Support. LLC (CCAD) Encryption operation with real data rounds, dummy data rounds, and delay periods
TWI596024B (zh) * 2016-05-24 2017-08-21 you-quan Hong A vehicle tail gate lighting warning control system and its lighting warning device
CN107153740A (zh) * 2017-05-18 2017-09-12 国家测绘地理信息局第四地形测量队 一种基于AutoCAD图库联动及数据集成式地下管线数据处理系统
CN113220347B (zh) * 2021-03-30 2024-03-22 深圳市创成微电子有限公司 基于多级流水线的指令处理方法、浮点型dsp以及音频设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855947A (en) * 1987-05-27 1989-08-08 Amdahl Corporation Microprogrammable pipeline interlocks based on the validity of pipeline states
EP0312764A3 (de) * 1987-10-19 1991-04-10 International Business Machines Corporation Datenprozessor mit mehrfachen Ausführungseinheiten zur parallelen Ausführung von mehreren Befehlsklassen
US4893233A (en) * 1988-04-18 1990-01-09 Motorola, Inc. Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
JP2816248B2 (ja) * 1989-11-08 1998-10-27 株式会社日立製作所 データプロセッサ
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
JP2875864B2 (ja) * 1990-08-24 1999-03-31 富士通株式会社 パイプライン処理方式
JPH04275628A (ja) * 1991-03-01 1992-10-01 Mitsubishi Electric Corp 演算処理装置
JPH07113891B2 (ja) * 1991-03-04 1995-12-06 松下電器産業株式会社 パイプライン処理装置
JP2925818B2 (ja) * 1991-04-05 1999-07-28 株式会社東芝 並列処理制御装置
EP0663083B1 (de) * 1992-09-29 2000-12-20 Seiko Epson Corporation System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
US5564056A (en) * 1994-03-01 1996-10-08 Intel Corporation Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming

Also Published As

Publication number Publication date
KR0180580B1 (ko) 1999-05-15
EP0730223B1 (de) 2004-06-09
TW448403B (en) 2001-08-01
EP0730223A1 (de) 1996-09-04
US5822561A (en) 1998-10-13
DE69632655T2 (de) 2004-09-30
KR960035300A (ko) 1996-10-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP