DE69633695D1 - Konfigurierbare Kontaktleiste zur bequemen parallellen Prüfung von integrierten Schaltungen - Google Patents

Konfigurierbare Kontaktleiste zur bequemen parallellen Prüfung von integrierten Schaltungen

Info

Publication number
DE69633695D1
DE69633695D1 DE69633695T DE69633695T DE69633695D1 DE 69633695 D1 DE69633695 D1 DE 69633695D1 DE 69633695 T DE69633695 T DE 69633695T DE 69633695 T DE69633695 T DE 69633695T DE 69633695 D1 DE69633695 D1 DE 69633695D1
Authority
DE
Germany
Prior art keywords
integrated circuits
contact strip
parallel testing
configurable contact
convenient parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69633695T
Other languages
English (en)
Other versions
DE69633695T2 (de
Inventor
Michael Joseph Brannigan
Mark Alan Lysinger
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE69633695D1 publication Critical patent/DE69633695D1/de
Publication of DE69633695T2 publication Critical patent/DE69633695T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE69633695T 1995-05-31 1996-04-26 Konfigurierbare Testkontakte zum Erleichtern der parallelen Prüfung von integrierten Schaltungen Expired - Fee Related DE69633695T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45618195A 1995-05-31 1995-05-31
US456181 1995-05-31

Publications (2)

Publication Number Publication Date
DE69633695D1 true DE69633695D1 (de) 2004-12-02
DE69633695T2 DE69633695T2 (de) 2005-04-28

Family

ID=23811782

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69633695T Expired - Fee Related DE69633695T2 (de) 1995-05-31 1996-04-26 Konfigurierbare Testkontakte zum Erleichtern der parallelen Prüfung von integrierten Schaltungen

Country Status (3)

Country Link
US (2) US5896039A (de)
EP (1) EP0745859B1 (de)
DE (1) DE69633695T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6240535B1 (en) 1995-12-22 2001-05-29 Micron Technology, Inc. Device and method for testing integrated circuit dice in an integrated circuit module
US5859442A (en) * 1996-12-03 1999-01-12 Micron Technology, Inc. Circuit and method for configuring a redundant bond pad for probing a semiconductor
KR100283030B1 (ko) * 1997-12-31 2001-03-02 윤종용 반도체 장치의 레이 아웃 구조
DE19839807C1 (de) 1998-09-01 1999-10-07 Siemens Ag Verfahren zum Betrieb einer integrierten Schaltung
US6424161B2 (en) 1998-09-03 2002-07-23 Micron Technology, Inc. Apparatus and method for testing fuses
DE19901460C1 (de) 1999-01-15 2000-08-31 Siemens Ag Integrierte Halbleiterschaltung und Verfahren zur Überprüfung des Übertragungsverhaltens von Pad-Zellen
JP2000349130A (ja) * 1999-06-03 2000-12-15 Nec Ic Microcomput Syst Ltd 半導体集積回路基板とその製造方法およびその特性チェック方法
KR100331553B1 (ko) * 1999-09-16 2002-04-06 윤종용 여러번의 프로빙 및 안정된 본딩을 허용하는 패드를 갖는 집적회로 장치
US6573113B1 (en) * 2001-09-04 2003-06-03 Lsi Logic Corporation Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads
US7249294B2 (en) * 2002-06-24 2007-07-24 Hynix Semiconductor Inc. Semiconductor memory device with reduced package test time
US6842022B2 (en) 2002-09-20 2005-01-11 Agilent Technologies, Inc. System and method for heterogeneous multi-site testing
GB0329516D0 (en) * 2003-12-19 2004-01-28 Univ Kent Canterbury Integrated circuit with debug support interface
US7370257B2 (en) * 2005-04-08 2008-05-06 Lsi Logic Corporation Test vehicle data analysis
US8779790B2 (en) * 2009-06-26 2014-07-15 Freescale Semiconductor, Inc. Probing structure for evaluation of slow slew-rate square wave signals in low power circuits
US8339152B2 (en) * 2010-03-30 2012-12-25 Freescale Semiconductor, Inc. Test structure activated by probe needle

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781683A (en) * 1971-03-30 1973-12-25 Ibm Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration
US4243937A (en) * 1979-04-06 1981-01-06 General Instrument Corporation Microelectronic device and method for testing same
US4288911A (en) * 1979-12-21 1981-09-15 Harris Corporation Method for qualifying biased integrated circuits on a wafer level
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
JPS61265829A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体集積回路
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
US4782283A (en) * 1986-08-22 1988-11-01 Aida Corporation Apparatus for scan testing CMOS integrated systems
US4853628A (en) * 1987-09-10 1989-08-01 Gazelle Microcircuits, Inc. Apparatus for measuring circuit parameters of a packaged semiconductor device
US5053700A (en) * 1989-02-14 1991-10-01 Amber Engineering, Inc. Method for wafer scale testing of redundant integrated circuit dies
JP2839547B2 (ja) * 1989-05-02 1998-12-16 株式会社東芝 半導体集積回路装置
JP2577495B2 (ja) * 1990-08-21 1997-01-29 株式会社東芝 半導体評価回路
US5371457A (en) * 1991-02-12 1994-12-06 Lipp; Robert J. Method and apparatus to test for current in an integrated circuit
US5389556A (en) * 1992-07-02 1995-02-14 Lsi Logic Corporation Individually powering-up unsingulated dies on a wafer
US5406199A (en) * 1993-07-28 1995-04-11 At&T Corp. Test fixture carrying a channel card for logic level translation

Also Published As

Publication number Publication date
EP0745859B1 (de) 2004-10-27
DE69633695T2 (de) 2005-04-28
US5896040A (en) 1999-04-20
EP0745859A2 (de) 1996-12-04
EP0745859A3 (de) 1997-08-06
US5896039A (en) 1999-04-20

Similar Documents

Publication Publication Date Title
DE69734379D1 (de) Vorrichtung zur Prüfung von integrierten Schaltungen
DE69127060D1 (de) Tester für integrierte Schaltungen
DE69636183D1 (de) Vorrichtung zur Prüfung von Halbleitersubstraten
DE69616081T2 (de) Verbindungsschema für integrierte schaltungen
DE69709363T2 (de) Echocompensator für nicht-lineare schaltungen
DE69301393D1 (de) Fassung zum testen von integrierten schaltkreisen
DE69115776D1 (de) Prüfvorrichtung für integrierte schaltungen
DE69822917D1 (de) Abtast- und Halteschaltung
DE69633695D1 (de) Konfigurierbare Kontaktleiste zur bequemen parallellen Prüfung von integrierten Schaltungen
KR960015836A (ko) 집적회로 시험장치
DE3764850D1 (de) Messprobe fuer werkstuecke und dazu gehoerige elektrische schaltungen.
DE69517693T2 (de) Standardzellenbibliothek für den Entwurf von integrierten Schaltungen
DE19680290T1 (de) Schaltungstestvorrichtung
DE69616130T2 (de) Schaltungsplatte mit niedrigem Ausdehnungskoeffizient zur Prüfung von integrierten Schaltungen
DE69717216T2 (de) Schaltplatinenprüfvorrichtung und Verfahren dafür
DE69823769D1 (de) Niederspannungs-Abtast- und Halteschaltungen
DE69223786T2 (de) Strommessanordnung zum Testen von integrierten Schaltungen
DE69634644D1 (de) Schaltung zur Zählerprüfung
DE69720725D1 (de) Verbesserte Ausgangsschaltung für integrierte Schaltungen
DE69515383D1 (de) Abtast- und Halteschaltung
DE69430036T2 (de) Testvorrichtung für integrierte Schaltungen
DE69630018D1 (de) Logische schaltung für niedrige spannungen
DE69610737T2 (de) Bondflächen-Option für integrierte Schaltungen
ATA66995A (de) Messverfahren und schaltungsanordnung zur ortung von dauererdschlüssen
DE69600376T2 (de) Passivierungs-Detektionsverfahren für integrierte Schaltungen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee