DE69624386T2 - Halbleiteranordnung und verfahren zur herstellung - Google Patents

Halbleiteranordnung und verfahren zur herstellung

Info

Publication number
DE69624386T2
DE69624386T2 DE69624386T DE69624386T DE69624386T2 DE 69624386 T2 DE69624386 T2 DE 69624386T2 DE 69624386 T DE69624386 T DE 69624386T DE 69624386 T DE69624386 T DE 69624386T DE 69624386 T2 DE69624386 T2 DE 69624386T2
Authority
DE
Germany
Prior art keywords
region
layer
gate electrode
channel formation
formation region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69624386T
Other languages
German (de)
English (en)
Other versions
DE69624386D1 (de
Inventor
Toshiaki Iwamatsu
Shigenobu Maeda
Yasuo Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69624386D1 publication Critical patent/DE69624386D1/de
Publication of DE69624386T2 publication Critical patent/DE69624386T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
DE69624386T 1996-11-15 1996-11-15 Halbleiteranordnung und verfahren zur herstellung Expired - Fee Related DE69624386T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/003369 WO1998022983A1 (en) 1996-11-15 1996-11-15 Semiconductor device and process for manufacturing the same

Publications (2)

Publication Number Publication Date
DE69624386D1 DE69624386D1 (de) 2002-11-21
DE69624386T2 true DE69624386T2 (de) 2003-06-12

Family

ID=14154104

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69624386T Expired - Fee Related DE69624386T2 (de) 1996-11-15 1996-11-15 Halbleiteranordnung und verfahren zur herstellung

Country Status (4)

Country Link
EP (1) EP0948057B1 (enExample)
KR (1) KR100287399B1 (enExample)
DE (1) DE69624386T2 (enExample)
WO (1) WO1998022983A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100626009B1 (ko) * 2004-06-30 2006-09-20 삼성에스디아이 주식회사 박막 트랜지스터 구조체 및 이를 구비하는 평판디스플레이 장치
JP4826127B2 (ja) * 2005-04-25 2011-11-30 ソニー株式会社 固体撮像装置及びその製造方法
KR100722106B1 (ko) * 2006-06-09 2007-05-25 삼성에스디아이 주식회사 박막 트랜지스터 및 그 제조방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2507567B2 (ja) * 1988-11-25 1996-06-12 三菱電機株式会社 絶縁体基板上の半導体層に形成されたｍｏｓ型電界効果トランジスタ
JP2547663B2 (ja) * 1990-10-03 1996-10-23 三菱電機株式会社 半導体装置
JP2636963B2 (ja) * 1990-11-28 1997-08-06 三菱電機株式会社 半導体装置
JPH08125187A (ja) * 1994-10-24 1996-05-17 Nippon Telegr & Teleph Corp <Ntt> Ｓｏｉ構造ｍｏｓ型半導体装置およびその製造方法

Also Published As

Publication number Publication date
KR20000022518A (ko) 2000-04-25
EP0948057A4 (enExample) 1999-10-06
EP0948057B1 (en) 2002-10-16
EP0948057A1 (en) 1999-10-06
WO1998022983A1 (en) 1998-05-28
KR100287399B1 (ko) 2001-05-02
DE69624386D1 (de) 2002-11-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee