DE69619646T2 - Schnittstellenarchitektur zur Verbindung mit einem PCI-Bus - Google Patents

Schnittstellenarchitektur zur Verbindung mit einem PCI-Bus

Info

Publication number
DE69619646T2
DE69619646T2 DE69619646T DE69619646T DE69619646T2 DE 69619646 T2 DE69619646 T2 DE 69619646T2 DE 69619646 T DE69619646 T DE 69619646T DE 69619646 T DE69619646 T DE 69619646T DE 69619646 T2 DE69619646 T2 DE 69619646T2
Authority
DE
Germany
Prior art keywords
data
bus
module
address
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69619646T
Other languages
German (de)
English (en)
Other versions
DE69619646D1 (de
Inventor
Randall Don Briggs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69619646D1 publication Critical patent/DE69619646D1/de
Application granted granted Critical
Publication of DE69619646T2 publication Critical patent/DE69619646T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
DE69619646T 1996-01-11 1996-08-16 Schnittstellenarchitektur zur Verbindung mit einem PCI-Bus Expired - Fee Related DE69619646T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/584,413 US5793997A (en) 1996-01-11 1996-01-11 Interface architecture for connection to a peripheral component interconnect bus

Publications (2)

Publication Number Publication Date
DE69619646D1 DE69619646D1 (de) 2002-04-11
DE69619646T2 true DE69619646T2 (de) 2002-08-01

Family

ID=24337226

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69619646T Expired - Fee Related DE69619646T2 (de) 1996-01-11 1996-08-16 Schnittstellenarchitektur zur Verbindung mit einem PCI-Bus

Country Status (4)

Country Link
US (1) US5793997A (enExample)
EP (1) EP0784278B1 (enExample)
JP (1) JPH09198341A (enExample)
DE (1) DE69619646T2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023736A (en) * 1997-12-19 2000-02-08 International Business Machines Corporation System for dynamically configuring I/O device adapters where a function configuration register contains ready/not ready flags corresponding to each I/O device adapter
US6101557A (en) * 1998-05-29 2000-08-08 International Business Machines Corporation Method and system for remote function control and delegation within multifunction bus supported devices
US6820157B1 (en) 1998-06-30 2004-11-16 International Business Machines Corporation Apparatus, program product and method of replacing failed hardware device through concurrent maintenance operation
US6243774B1 (en) 1998-06-30 2001-06-05 International Business Machines Corporation Apparatus program product and method of managing computer resources supporting concurrent maintenance operations
US6529978B1 (en) 2000-02-23 2003-03-04 International Business Machines Corporation Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings
US9836424B2 (en) 2001-08-24 2017-12-05 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
KR100750036B1 (ko) 2001-08-24 2007-08-16 인텔 코오퍼레이션 플로우 제어를 구현하는 범용 입출력 아키텍쳐, 프로토콜및 관련 방법
US6809547B2 (en) * 2001-12-24 2004-10-26 Broadcom, Corp. Multi-function interface and applications thereof
US7107382B2 (en) * 2003-04-03 2006-09-12 Emulex Design & Manufacturing Corporation Virtual peripheral component interconnect multiple-function device
US20050262391A1 (en) * 2004-05-10 2005-11-24 Prashant Sethi I/O configuration messaging within a link-based computing system
US7568056B2 (en) * 2005-03-28 2009-07-28 Nvidia Corporation Host bus adapter that interfaces with host computer bus to multiple types of storage devices
CN112667541B (zh) * 2020-12-15 2023-06-02 厦门智多晶科技有限公司 一种ip动态配置电路和fpga

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4641261A (en) * 1984-05-21 1987-02-03 Rca Corporation Universal interface circuit for microprocessor peripherals
JPH02226454A (ja) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> コンピユータ・システムおよびそのデータ転送方法
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
US5550989A (en) * 1993-05-28 1996-08-27 International Business Machines Corporation Bridge circuit that can eliminate invalid data during information transfer between buses of different bitwidths
GB2286910B (en) * 1994-02-24 1998-11-25 Intel Corp Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer
US5664124A (en) * 1994-11-30 1997-09-02 International Business Machines Corporation Bridge between two buses of a computer system that latches signals from the bus for use on the bridge and responds according to the bus protocols

Also Published As

Publication number Publication date
US5793997A (en) 1998-08-11
EP0784278A1 (en) 1997-07-16
JPH09198341A (ja) 1997-07-31
EP0784278B1 (en) 2002-03-06
DE69619646D1 (de) 2002-04-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee