DE69529960D1 - Phasendetektor mit ternärem Ausgang - Google Patents

Phasendetektor mit ternärem Ausgang

Info

Publication number
DE69529960D1
DE69529960D1 DE69529960T DE69529960T DE69529960D1 DE 69529960 D1 DE69529960 D1 DE 69529960D1 DE 69529960 T DE69529960 T DE 69529960T DE 69529960 T DE69529960 T DE 69529960T DE 69529960 D1 DE69529960 D1 DE 69529960D1
Authority
DE
Germany
Prior art keywords
phase detector
ternary output
ternary
output
detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69529960T
Other languages
English (en)
Other versions
DE69529960T2 (de
Inventor
Bertrand J Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chartoleaux KG LLC
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of DE69529960D1 publication Critical patent/DE69529960D1/de
Application granted granted Critical
Publication of DE69529960T2 publication Critical patent/DE69529960T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
DE69529960T 1994-10-26 1995-07-20 Phasendetektor mit ternärem Ausgang Expired - Lifetime DE69529960T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/329,277 US5455540A (en) 1994-10-26 1994-10-26 Modified bang-bang phase detector with ternary output

Publications (2)

Publication Number Publication Date
DE69529960D1 true DE69529960D1 (de) 2003-04-24
DE69529960T2 DE69529960T2 (de) 2003-12-04

Family

ID=23284665

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69529960T Expired - Lifetime DE69529960T2 (de) 1994-10-26 1995-07-20 Phasendetektor mit ternärem Ausgang

Country Status (4)

Country Link
US (2) US5455540A (de)
EP (1) EP0709966B1 (de)
JP (1) JPH08228147A (de)
DE (1) DE69529960T2 (de)

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US7170964B2 (en) * 2002-08-07 2007-01-30 Broadcom Corporation Transition insensitive timing recovery method and apparatus
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US20040114702A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corporation Bang-bang phase detector for full-rate and half-rate schemes clock and data recovery and method therefor
GB2397956B (en) * 2003-01-29 2005-11-30 Phyworks Ltd Phase detector
JP4242741B2 (ja) * 2003-09-19 2009-03-25 パナソニック株式会社 デバッグ用信号処理回路
US8085857B1 (en) 2003-09-25 2011-12-27 Cypress Semiconductor Corporation Digital-compatible multi-state-sense input
US20050238092A1 (en) * 2004-04-22 2005-10-27 Ng Devin K Method and system for error estimation for adaptive equalization in communication systems
US7436921B1 (en) * 2004-11-05 2008-10-14 Rockwell Collins, Inc. Frequency sampling phase detector
US7864911B2 (en) * 2006-09-13 2011-01-04 Sony Corporation System and method for implementing a phase detector to support a data transmission procedure
US8315349B2 (en) * 2007-10-31 2012-11-20 Diablo Technologies Inc. Bang-bang phase detector with sub-rate clock
EP2252003A1 (de) * 2009-05-12 2010-11-17 CoreOptics Inc. Phasenbestimmungsverfahren und Phasendetektor
WO2016097412A1 (en) * 2014-12-19 2016-06-23 Selex Es Ltd Digital phase meter and phase detection method
CN109150171B (zh) * 2018-09-14 2022-04-05 南京邮电大学 一种高速低抖动的鉴频鉴相器及时钟数据恢复电路

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Also Published As

Publication number Publication date
US5592125A (en) 1997-01-07
EP0709966B1 (de) 2003-03-19
EP0709966A3 (de) 1997-06-18
US5455540A (en) 1995-10-03
EP0709966A2 (de) 1996-05-01
JPH08228147A (ja) 1996-09-03
DE69529960T2 (de) 2003-12-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: DOT ASSETS NO. 12, LLC, WILMINGTON, US