DE69522498T2 - Signalübertragungsverfahren, Signalübertragungsschaltkreis und dafür geeigneter integrierter Halbleiterschaltkreis - Google Patents

Signalübertragungsverfahren, Signalübertragungsschaltkreis und dafür geeigneter integrierter Halbleiterschaltkreis

Info

Publication number
DE69522498T2
DE69522498T2 DE69522498T DE69522498T DE69522498T2 DE 69522498 T2 DE69522498 T2 DE 69522498T2 DE 69522498 T DE69522498 T DE 69522498T DE 69522498 T DE69522498 T DE 69522498T DE 69522498 T2 DE69522498 T2 DE 69522498T2
Authority
DE
Germany
Prior art keywords
signal transmission
circuit
integrated semiconductor
suitable integrated
transmission method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69522498T
Other languages
English (en)
Other versions
DE69522498D1 (de
Inventor
Toru Iwata
Hiroyuki Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69522498D1 publication Critical patent/DE69522498D1/de
Application granted granted Critical
Publication of DE69522498T2 publication Critical patent/DE69522498T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
DE69522498T 1994-06-03 1995-06-01 Signalübertragungsverfahren, Signalübertragungsschaltkreis und dafür geeigneter integrierter Halbleiterschaltkreis Expired - Fee Related DE69522498T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12253394 1994-06-03

Publications (2)

Publication Number Publication Date
DE69522498D1 DE69522498D1 (de) 2001-10-11
DE69522498T2 true DE69522498T2 (de) 2002-04-18

Family

ID=14838221

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69522498T Expired - Fee Related DE69522498T2 (de) 1994-06-03 1995-06-01 Signalübertragungsverfahren, Signalübertragungsschaltkreis und dafür geeigneter integrierter Halbleiterschaltkreis

Country Status (6)

Country Link
US (1) US5638013A (de)
EP (1) EP0685846B1 (de)
KR (1) KR100190179B1 (de)
CN (1) CN1093336C (de)
DE (1) DE69522498T2 (de)
TW (1) TW385540B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3300593B2 (ja) * 1995-06-15 2002-07-08 株式会社東芝 半導体集積回路装置
US5946470A (en) * 1996-05-15 1999-08-31 Intel Corporation Method and apparatus for voltage level shifting and deskewing the inputs to a high performance microprocessor
JP3087839B2 (ja) * 1997-08-28 2000-09-11 日本電気株式会社 半導体装置、そのテスト方法
US6147884A (en) * 1999-06-28 2000-11-14 Agilent Technologies, Inc. Method and apparatus for low-power charge transition in an I/O system of an integrated circuit
EP1443650A3 (de) * 2003-01-30 2006-11-15 STMicroelectronics Pvt. Ltd Verfahren und Vorrichtung zur Reduzierung des Leistungsverbrauchs in einer digitalen Schaltung mit Ladungsneuverteilungschaltungen
US7002506B1 (en) * 2004-12-23 2006-02-21 Texas Instruments Incorporated Providing pipe line ADC with acceptable bit error and power efficiency combination
US8476962B2 (en) * 2009-11-18 2013-07-02 Freescale Semiconductor, Inc. System having multiple voltage tiers and method therefor
US8169257B2 (en) * 2009-11-18 2012-05-01 Freescale Semiconductor, Inc. System and method for communicating between multiple voltage tiers
US11185304B2 (en) * 2016-11-03 2021-11-30 Khalifa University of Science and Technology Systems and method for acoustic power scalable charge-redistribution ultrasonic system with on-chip aberration compensation for portable ultrasonic applications

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2805210B2 (ja) * 1989-06-09 1998-09-30 日本テキサス・インスツルメンツ株式会社 昇圧回路
JPH0421112A (ja) * 1990-05-16 1992-01-24 Matsushita Electric Ind Co Ltd 昇圧電圧発生回路
KR920010633A (ko) * 1990-11-30 1992-06-26 김광호 반도체 메모리 장치의 기준전압 발생회로

Also Published As

Publication number Publication date
US5638013A (en) 1997-06-10
CN1119374A (zh) 1996-03-27
KR100190179B1 (ko) 1999-06-01
TW385540B (en) 2000-03-21
DE69522498D1 (de) 2001-10-11
CN1093336C (zh) 2002-10-23
EP0685846A1 (de) 1995-12-06
EP0685846B1 (de) 2001-09-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee