DE69520266T2 - Schnelles NOR-NOR programmierbares logisches Feld mit Einphasentakt - Google Patents

Schnelles NOR-NOR programmierbares logisches Feld mit Einphasentakt

Info

Publication number
DE69520266T2
DE69520266T2 DE69520266T DE69520266T DE69520266T2 DE 69520266 T2 DE69520266 T2 DE 69520266T2 DE 69520266 T DE69520266 T DE 69520266T DE 69520266 T DE69520266 T DE 69520266T DE 69520266 T2 DE69520266 T2 DE 69520266T2
Authority
DE
Germany
Prior art keywords
fast
programmable logic
single phase
phase clock
logic field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69520266T
Other languages
English (en)
Other versions
DE69520266D1 (de
Inventor
Robert Beat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Ltd filed Critical STMicroelectronics Ltd Great Britain
Application granted granted Critical
Publication of DE69520266D1 publication Critical patent/DE69520266D1/de
Publication of DE69520266T2 publication Critical patent/DE69520266T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
DE69520266T 1994-12-29 1995-12-27 Schnelles NOR-NOR programmierbares logisches Feld mit Einphasentakt Expired - Fee Related DE69520266T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9426335.7A GB9426335D0 (en) 1994-12-29 1994-12-29 A fast nor-nor pla operating from a single phase clock

Publications (2)

Publication Number Publication Date
DE69520266D1 DE69520266D1 (de) 2001-04-12
DE69520266T2 true DE69520266T2 (de) 2001-07-19

Family

ID=10766672

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69520266T Expired - Fee Related DE69520266T2 (de) 1994-12-29 1995-12-27 Schnelles NOR-NOR programmierbares logisches Feld mit Einphasentakt

Country Status (5)

Country Link
US (1) US5959465A (de)
EP (1) EP0720297B1 (de)
JP (1) JP3068447B2 (de)
DE (1) DE69520266T2 (de)
GB (1) GB9426335D0 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100466457B1 (ko) * 1995-11-08 2005-06-16 마츠시타 덴끼 산교 가부시키가이샤 신호전송회로,신호수신회로및신호송수신회로,신호전송방법,신호수신방법및신호송수신방법과반도체집적회로및그제어방법
US6134252A (en) * 1997-04-11 2000-10-17 Advanced Micro Devices, Inc. Enhanced glitch removal circuit
US6124735A (en) * 1997-12-11 2000-09-26 Intrinsity, Inc. Method and apparatus for a N-nary logic circuit using capacitance isolation
US6600959B1 (en) 2000-02-04 2003-07-29 International Business Machines Corporation Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays
US6229338B1 (en) * 2000-02-04 2001-05-08 International Business Machines Corporation Method and apparatus for reducing dynamic programmable logic array propagation delay
US7087954B2 (en) * 2001-08-30 2006-08-08 Micron Technology, Inc. In service programmable logic arrays with low tunnel barrier interpoly insulators
US6778441B2 (en) * 2001-08-30 2004-08-17 Micron Technology, Inc. Integrated circuit memory device and method
US7075829B2 (en) * 2001-08-30 2006-07-11 Micron Technology, Inc. Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
US7132711B2 (en) 2001-08-30 2006-11-07 Micron Technology, Inc. Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
US6963103B2 (en) 2001-08-30 2005-11-08 Micron Technology, Inc. SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US7068544B2 (en) * 2001-08-30 2006-06-27 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US6754108B2 (en) * 2001-08-30 2004-06-22 Micron Technology, Inc. DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US7042043B2 (en) * 2001-08-30 2006-05-09 Micron Technology, Inc. Programmable array logic or memory devices with asymmetrical tunnel barriers
US7476925B2 (en) * 2001-08-30 2009-01-13 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US7728622B2 (en) 2007-03-29 2010-06-01 Qualcomm Incorporated Software programmable logic using spin transfer torque magnetoresistive random access memory
US20090257263A1 (en) * 2008-04-15 2009-10-15 Vns Portfolio Llc Method and Apparatus for Computer Memory
US8295082B2 (en) * 2008-08-15 2012-10-23 Qualcomm Incorporated Gate level reconfigurable magnetic logic
WO2011136212A1 (ja) * 2010-04-27 2011-11-03 日本電気株式会社 論理回路エミュレータ及び論理回路エミュレータの制御方法
US9608637B2 (en) * 2015-08-14 2017-03-28 Qualcomm Incorporated Dynamic voltage level shifters employing pulse generation circuits, and related systems and methods

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0178437A1 (de) * 1984-09-19 1986-04-23 Siemens Aktiengesellschaft Programmierbare Schaltung in dynamischer C-MOS-Technik
CA1257343A (en) * 1986-07-02 1989-07-11 Robert C. Rose Self-timed programmable logic array with pre-charge circuit
IT1195119B (it) * 1986-08-04 1988-10-12 Cselt Centro Studi Lab Telecom Perfezionamenti alle schiere logi che programmabili dinamiche a struttura nor nor realizzate in tecnolo gia c mos
US4751407A (en) * 1986-12-19 1988-06-14 Hughes Aircraft Company Self-timing circuit
US4760290A (en) * 1987-05-21 1988-07-26 Vlsi Technology, Inc. Synchronous logic array circuit with dummy signal lines for controlling "AND" array output
JPH0193927A (ja) * 1987-10-06 1989-04-12 Fujitsu Ltd プログラム可能な論理回路
JPH01109922A (ja) * 1987-10-23 1989-04-26 Mitsubishi Electric Corp プログラマブルロジツクアレイ
JP2575899B2 (ja) * 1989-10-26 1997-01-29 株式会社東芝 プリチャージ式論理回路
JPH03231515A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp プログラマブル論理装置
US5121005A (en) * 1991-04-01 1992-06-09 Motorola, Inc. Programmable logic array with delayed active pull-ups on the column conductors

Also Published As

Publication number Publication date
GB9426335D0 (en) 1995-03-01
JPH08256051A (ja) 1996-10-01
US5959465A (en) 1999-09-28
EP0720297A1 (de) 1996-07-03
DE69520266D1 (de) 2001-04-12
EP0720297B1 (de) 2001-03-07
JP3068447B2 (ja) 2000-07-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee