DE69518326D1 - Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch - Google Patents

Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch

Info

Publication number
DE69518326D1
DE69518326D1 DE69518326T DE69518326T DE69518326D1 DE 69518326 D1 DE69518326 D1 DE 69518326D1 DE 69518326 T DE69518326 T DE 69518326T DE 69518326 T DE69518326 T DE 69518326T DE 69518326 D1 DE69518326 D1 DE 69518326D1
Authority
DE
Germany
Prior art keywords
power consumption
neural network
low
low power
low voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69518326T
Other languages
English (en)
Other versions
DE69518326T2 (de
Inventor
Vito Fabbrizio
Gianluca Colli
Alan Kramer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69518326D1 publication Critical patent/DE69518326D1/de
Application granted granted Critical
Publication of DE69518326T2 publication Critical patent/DE69518326T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Computational Linguistics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Neurology (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
DE69518326T 1995-10-13 1995-10-13 Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch Expired - Fee Related DE69518326T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830433A EP0768610B1 (de) 1995-10-13 1995-10-13 Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch

Publications (2)

Publication Number Publication Date
DE69518326D1 true DE69518326D1 (de) 2000-09-14
DE69518326T2 DE69518326T2 (de) 2001-01-18

Family

ID=8222032

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69518326T Expired - Fee Related DE69518326T2 (de) 1995-10-13 1995-10-13 Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch

Country Status (4)

Country Link
US (3) US6032140A (de)
EP (1) EP0768610B1 (de)
JP (1) JPH09198366A (de)
DE (1) DE69518326T2 (de)

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DE69518326T2 (de) * 1995-10-13 2001-01-18 St Microelectronics Srl Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch
US6112168A (en) * 1997-10-20 2000-08-29 Microsoft Corporation Automatically recognizing the discourse structure of a body of text
ITMI990737A1 (it) * 1999-04-09 2000-10-09 St Microelectronics Srl Procedimento per aumentare la precisione equivalente di calcolo in una memoria associativa analogica
US6580296B1 (en) 2000-09-22 2003-06-17 Rn2R, L.L.C. Low power differential conductance-based logic gate and method of operation thereof
WO2002069497A2 (en) * 2001-02-27 2002-09-06 Broadcom Corporation High speed latch comparators
US6501294B2 (en) 2001-04-26 2002-12-31 International Business Machines Corporation Neuron circuit
US6583651B1 (en) 2001-12-07 2003-06-24 Stmicroelectronics, Inc. Neural network output sensing and decision circuit and method
US7062476B2 (en) * 2002-06-17 2006-06-13 The Boeing Company Student neural network
US20080196766A1 (en) * 2007-02-21 2008-08-21 Wilber Ross Gandy Breakaway self-sealing safety valve
CN104520896B (zh) 2012-01-27 2017-09-29 韩国科学技术院 视觉神经电路装置及利用视觉神经电路装置的视觉神经模仿系统
US9760533B2 (en) 2014-08-14 2017-09-12 The Regents On The University Of Michigan Floating-gate transistor array for performing weighted sum computation
CN105095967B (zh) * 2015-07-16 2018-02-16 清华大学 一种多模态神经形态网络核
WO2017131632A1 (en) 2016-01-26 2017-08-03 Hewlett Packard Enterprise Development Lp Memristive arrays with offset elements
US9966137B2 (en) 2016-08-17 2018-05-08 Samsung Electronics Co., Ltd. Low power analog or multi-level memory for neuromorphic computing
US10483981B2 (en) 2016-12-30 2019-11-19 Microsoft Technology Licensing, Llc Highspeed/low power symbol compare
US11270194B2 (en) 2017-07-26 2022-03-08 International Business Machines Corporation System and method for constructing synaptic weights for artificial neural networks from signed analog conductance-pairs of varying significance
JP6773621B2 (ja) * 2017-09-15 2020-10-21 株式会社東芝 演算装置
US11074499B2 (en) 2017-11-20 2021-07-27 International Business Machines Corporation Synaptic weight transfer between conductance pairs with polarity inversion for reducing fixed device asymmetries
US11321608B2 (en) 2018-01-19 2022-05-03 International Business Machines Corporation Synapse memory cell driver
US10217512B1 (en) * 2018-05-15 2019-02-26 International Business Machines Corporation Unit cell with floating gate MOSFET for analog memory
US10489483B1 (en) * 2018-09-21 2019-11-26 National Technology & Engineering Solutions Of Sandia, Llc Circuit arrangement and technique for setting matrix values in three-terminal memory cells
EP3654250B1 (de) * 2018-11-13 2023-04-12 IMEC vzw Maschinenlernbeschleuniger

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US5155802A (en) * 1987-12-03 1992-10-13 Trustees Of The Univ. Of Penna. General purpose neural computer
JP2595051B2 (ja) * 1988-07-01 1997-03-26 株式会社日立製作所 半導体集積回路
JP2823229B2 (ja) * 1989-04-05 1998-11-11 株式会社東芝 電子回路、差動増幅回路、及びアナログ乗算回路
JPH02287670A (ja) * 1989-04-27 1990-11-27 Mitsubishi Electric Corp 半導体神経回路網
US5305250A (en) * 1989-05-05 1994-04-19 Board Of Trustees Operating Michigan State University Analog continuous-time MOS vector multiplier circuit and a programmable MOS realization for feedback neural networks
US4988891A (en) * 1989-05-09 1991-01-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor neural network including photosensitive coupling elements
JPH02310666A (ja) * 1989-05-25 1990-12-26 Mitsubishi Electric Corp 半導体神経回路装置
JP2662559B2 (ja) * 1989-06-02 1997-10-15 直 柴田 半導体装置
US5187680A (en) * 1989-06-15 1993-02-16 General Electric Company Neural net using capacitive structures connecting input lines and differentially sensed output line pairs
US4961002A (en) * 1989-07-13 1990-10-02 Intel Corporation Synapse cell employing dual gate transistor structure
US4956564A (en) * 1989-07-13 1990-09-11 Intel Corporation Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network
US5101361A (en) * 1989-09-29 1992-03-31 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Analog hardware for delta-backpropagation neural networks
JPH0634248B2 (ja) * 1989-12-16 1994-05-02 三菱電機株式会社 半導体神経回路網
JPH0782481B2 (ja) * 1989-12-26 1995-09-06 三菱電機株式会社 半導体神経回路網
US5056037A (en) * 1989-12-28 1991-10-08 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Analog hardware for learning neural networks
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US5146602A (en) * 1990-12-26 1992-09-08 Intel Corporation Method of increasing the accuracy of an analog neural network and the like
US5268320A (en) * 1990-12-26 1993-12-07 Intel Corporation Method of increasing the accuracy of an analog circuit employing floating gate memory devices
IT1244911B (it) * 1991-01-31 1994-09-13 Texas Instruments Italia Spa Architettura per rete neuronica fisicamente inseribile nel processo di apprendimento.
IT1244910B (it) * 1991-01-31 1994-09-13 Texas Instruments Italia Spa Cella convertitrice tensione-corrente, regolabile, realizzata mediante uno stadio differenziale, a transistori mos. in particolare per formare sinapsi di reti neuroniche e combinazione di tali celle per formare il corredo di sinapsi di un nucleo neuronico.
US5248956A (en) * 1991-04-05 1993-09-28 Center For Innovative Technology Electronically controllable resistor
US5422982A (en) * 1991-05-02 1995-06-06 Dow Corning Corporation Neural networks containing variable resistors as synapses
US5155377A (en) * 1991-08-20 1992-10-13 Intel Corporation Charge domain differential conductance synapse cell for neural networks
US5302838A (en) * 1992-06-09 1994-04-12 University Of Cincinnati Multi-quantum well injection mode device
US5256911A (en) * 1992-06-10 1993-10-26 Intel Corporation Neural network with multiplexed snyaptic processing
US5343555A (en) * 1992-07-06 1994-08-30 The Regents Of The University Of California Artificial neuron with switched-capacitor synapses using analog storage of synaptic weights
US5298796A (en) * 1992-07-08 1994-03-29 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Nonvolatile programmable neural network synaptic array
US5336937A (en) * 1992-08-28 1994-08-09 State University Of New York Programmable analog synapse and neural networks incorporating same
US5444821A (en) * 1993-11-10 1995-08-22 United Microelectronics Corp. Artificial neuron element with electrically programmable synaptic weight for neural networks
DE69518326T2 (de) * 1995-10-13 2001-01-18 St Microelectronics Srl Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch

Also Published As

Publication number Publication date
EP0768610B1 (de) 2000-08-09
JPH09198366A (ja) 1997-07-31
USRE41658E1 (en) 2010-09-07
US6032140A (en) 2000-02-29
EP0768610A1 (de) 1997-04-16
US6269352B1 (en) 2001-07-31
DE69518326T2 (de) 2001-01-18

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee