DE69516062D1 - DPLL und Entstopfungsschaltung unter Verwendung derselben - Google Patents

DPLL und Entstopfungsschaltung unter Verwendung derselben

Info

Publication number
DE69516062D1
DE69516062D1 DE69516062T DE69516062T DE69516062D1 DE 69516062 D1 DE69516062 D1 DE 69516062D1 DE 69516062 T DE69516062 T DE 69516062T DE 69516062 T DE69516062 T DE 69516062T DE 69516062 D1 DE69516062 D1 DE 69516062D1
Authority
DE
Germany
Prior art keywords
dpll
same
unblocking
circuit
unblocking circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69516062T
Other languages
English (en)
Other versions
DE69516062T2 (de
Inventor
Yoshinori Rokugo
Masaaki Itoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69516062D1 publication Critical patent/DE69516062D1/de
Publication of DE69516062T2 publication Critical patent/DE69516062T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)
DE69516062T 1994-09-12 1995-09-08 DPLL und Entstopfungsschaltung unter Verwendung derselben Expired - Lifetime DE69516062T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6217438A JPH0884071A (ja) 1994-09-12 1994-09-12 完全２次系ｄｐｌｌおよびそれを用いたデスタッフ回路

Publications (2)

Publication Number Publication Date
DE69516062D1 true DE69516062D1 (de) 2000-05-11
DE69516062T2 DE69516062T2 (de) 2001-01-11

Family

ID=16704237

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69516062T Expired - Lifetime DE69516062T2 (de) 1994-09-12 1995-09-08 DPLL und Entstopfungsschaltung unter Verwendung derselben

Country Status (5)

Country Link
US (1) US5604774A (de)
EP (1) EP0701330B1 (de)
JP (1) JPH0884071A (de)
KR (1) KR0184916B1 (de)
DE (1) DE69516062T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020082043A1 (en) * 1994-05-19 2002-06-27 Kari-Pekka Wilska Device for personal communications, data collection and data processing, and a circuit card
JP2817676B2 (ja) * 1995-07-31 1998-10-30 日本電気株式会社 Ｐｌｌ周波数シンセサイザ
JP2996205B2 (ja) * 1997-05-09 1999-12-27 日本電気株式会社 Ｐｄｈ低速信号切替式ｄｐｌｌ
JPH1155201A (ja) 1997-07-29 1999-02-26 Sony Corp 情報処理装置および方法、情報処理システム、並びに伝送媒体
IT1307715B1 (it) * 1999-09-30 2001-11-14 Cit Alcatel Circuito di desincronizzazione di flussi tributari in trame didivisione di tempo in reti di telecomunicazioni e relativo metodo.
US7512205B1 (en) * 2005-03-01 2009-03-31 Network Equipment Technologies, Inc. Baud rate generation using phase lock loops

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6315530A (ja) * 1986-07-08 1988-01-22 Sumitomo Electric Ind Ltd デイジタル位相同期ル−プ
JP2651688B2 (ja) * 1988-01-29 1997-09-10 京セラ株式会社 ディジタルｐｌｌ回路
US4827225A (en) * 1988-06-13 1989-05-02 Unisys Corporation Fast locking phase-locked loop utilizing frequency estimation
JPH0265314A (ja) * 1988-08-31 1990-03-06 Nec Corp インクリメント・ディクリメント・パルス演算回路
JPH02280414A (ja) * 1989-04-21 1990-11-16 Nec Corp 完全二次系ｄｐｌｌ
JPH05268077A (ja) * 1992-03-18 1993-10-15 Fujitsu Ltd ディジタルｐｌｌ回路
JP2985489B2 (ja) * 1992-03-31 1999-11-29 日本電気株式会社 位相同期ループ

Also Published As

Publication number Publication date
EP0701330A1 (de) 1996-03-13
KR0184916B1 (ko) 1999-04-15
DE69516062T2 (de) 2001-01-11
EP0701330B1 (de) 2000-04-05
JPH0884071A (ja) 1996-03-26
US5604774A (en) 1997-02-18
KR960012813A (ko) 1996-04-20

Similar Documents

Publication Publication Date Title
DE69842258D1 (de) Verzögerungsschaltung und Oszillator unter Verwendung derselben
FI932615A0 (fi) Anordning foer minimering av virvelstroemmar i en magnetisk avbildningsapparat foersedd med polskor
DE19580279T1 (de) Schlüsselanhänger- und Befestigung
DE69523193D1 (de) PLL-Schaltung mit verringter Einrastzeit
DE69512142D1 (de) Spannungsgesteuerter Oszillator
DE59208078D1 (de) Polfolienfarbstoffe und daraus hergestellte Polfolien
DE69116485T2 (de) Phasenverschiebungsvorrichtung und Lasergerät unter Verwendung desselben
NO950174D0 (no) PLL syntetiserer og fremgangsmåte for styring av samme
DE69431947T2 (de) Rauschunterdrückungsvorrichtung und datenkommunikationsgerät unter verwendung derselben
DE69534008D1 (de) Eine oszillator- und senderanordnung
DE69518687T2 (de) Versorgung-unterscheidendes und Versorgung-adaptierendes elektronisches System
SG68693A1 (en) Semiconductive ceramic and semiconductive ceramic element using the same
DE69710165D1 (de) Phasenregelschleife
DE69719414D1 (de) Piezoelektrischer Resonator und elektrisches Bauteil unter Verwendung derselben
DE69516062T2 (de) DPLL und Entstopfungsschaltung unter Verwendung derselben
FI946052A (fi) Säilytyskaappi
DE59510896D1 (de) Fernsteuerbare schaltungsanordnung
DE69723593D1 (de) Wahrnehmbarer Gehörschutzstöpsel
FI961985A0 (fi) Oscillatorkrets
DE59503730D1 (de) Steuerbarer oszillator
DE68928552D1 (de) Integrierte Halbleiterschaltung und System unter Verwendung derselben Schaltung
DE69108726D1 (de) Isolierungselement und der gebrauch davon bei einer isolationsanordnung.
FI980826A0 (fi) Kontroll av oeverbelastning i telekommunikationsnaet
FI98017B (fi) Ohjauskytkentä
DE29610161U1 (de) Verschlußanordnung und Garantieelement

Legal Events

Date Code Title Description
8364 No opposition during term of opposition