IT1307715B1 - Circuito di desincronizzazione di flussi tributari in trame didivisione di tempo in reti di telecomunicazioni e relativo metodo. - Google Patents
Circuito di desincronizzazione di flussi tributari in trame didivisione di tempo in reti di telecomunicazioni e relativo metodo.Info
- Publication number
- IT1307715B1 IT1307715B1 IT1999TO000841A ITTO990841A IT1307715B1 IT 1307715 B1 IT1307715 B1 IT 1307715B1 IT 1999TO000841 A IT1999TO000841 A IT 1999TO000841A IT TO990841 A ITTO990841 A IT TO990841A IT 1307715 B1 IT1307715 B1 IT 1307715B1
- Authority
- IT
- Italy
- Prior art keywords
- desinchronization
- division
- circuit
- time
- related method
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT1999TO000841A IT1307715B1 (it) | 1999-09-30 | 1999-09-30 | Circuito di desincronizzazione di flussi tributari in trame didivisione di tempo in reti di telecomunicazioni e relativo metodo. |
| EP00402589A EP1089474A3 (en) | 1999-09-30 | 2000-09-19 | Desynchronizer circuit for time division frame tributaries in telecommunications networks and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT1999TO000841A IT1307715B1 (it) | 1999-09-30 | 1999-09-30 | Circuito di desincronizzazione di flussi tributari in trame didivisione di tempo in reti di telecomunicazioni e relativo metodo. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITTO990841A1 ITTO990841A1 (it) | 2001-03-30 |
| IT1307715B1 true IT1307715B1 (it) | 2001-11-14 |
Family
ID=11418107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT1999TO000841A IT1307715B1 (it) | 1999-09-30 | 1999-09-30 | Circuito di desincronizzazione di flussi tributari in trame didivisione di tempo in reti di telecomunicazioni e relativo metodo. |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP1089474A3 (it) |
| IT (1) | IT1307715B1 (it) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4516083A (en) * | 1982-05-14 | 1985-05-07 | Motorola, Inc. | Fast lock PLL having out of lock detector control of loop filter and divider |
| US4920320A (en) * | 1988-12-19 | 1990-04-24 | Motorola, Inc. | Phase locked loop with optimally controlled bandwidth |
| US5402452A (en) * | 1992-08-25 | 1995-03-28 | Alcatel Network Systems, Inc. | Incremental phase smoothing desynchronizer and calculation apparatus |
| JPH0884071A (ja) * | 1994-09-12 | 1996-03-26 | Nec Corp | 完全２次系ｄｐｌｌおよびそれを用いたデスタッフ回路 |
| SE9503648D0 (sv) * | 1995-10-18 | 1995-10-18 | Ericsson Telefon Ab L M | Förfarande och anordning för snabbt återställande av faslåsning i ett transmissionssystem |
-
1999
- 1999-09-30 IT IT1999TO000841A patent/IT1307715B1/it active
-
2000
- 2000-09-19 EP EP00402589A patent/EP1089474A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP1089474A2 (en) | 2001-04-04 |
| ITTO990841A1 (it) | 2001-03-30 |
| EP1089474A3 (en) | 2005-07-06 |
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