DE69513568T2 - Steuerungsschaltung für einen verteilten Datenbus in einer integrierten Speicherschaltung - Google Patents

Steuerungsschaltung für einen verteilten Datenbus in einer integrierten Speicherschaltung

Info

Publication number
DE69513568T2
DE69513568T2 DE69513568T DE69513568T DE69513568T2 DE 69513568 T2 DE69513568 T2 DE 69513568T2 DE 69513568 T DE69513568 T DE 69513568T DE 69513568 T DE69513568 T DE 69513568T DE 69513568 T2 DE69513568 T2 DE 69513568T2
Authority
DE
Germany
Prior art keywords
data bus
distributed data
integrated memory
control circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69513568T
Other languages
English (en)
Other versions
DE69513568D1 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE69513568D1 publication Critical patent/DE69513568D1/de
Publication of DE69513568T2 publication Critical patent/DE69513568T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418Address circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
DE69513568T 1994-05-31 1995-05-24 Steuerungsschaltung für einen verteilten Datenbus in einer integrierten Speicherschaltung Expired - Fee Related DE69513568T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/251,718 US5521880A (en) 1994-05-31 1994-05-31 Integrated circuit memory having control circuitry for shared data bus

Publications (2)

Publication Number Publication Date
DE69513568D1 DE69513568D1 (de) 2000-01-05
DE69513568T2 true DE69513568T2 (de) 2000-03-30

Family

ID=22953113

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69513568T Expired - Fee Related DE69513568T2 (de) 1994-05-31 1995-05-24 Steuerungsschaltung für einen verteilten Datenbus in einer integrierten Speicherschaltung

Country Status (4)

Country Link
US (1) US5521880A (de)
EP (1) EP0685851B1 (de)
JP (1) JPH0845278A (de)
DE (1) DE69513568T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4332769C1 (de) * 1993-09-25 1994-12-15 Bosch Gmbh Robert Mikrorechner
US5909702A (en) * 1995-09-29 1999-06-01 Intel Corporation Memory address translations for programs code execution/relocation
TW307869B (en) * 1995-12-20 1997-06-11 Toshiba Co Ltd Semiconductor memory
DE19733708C2 (de) * 1997-08-04 1999-05-27 Siemens Ag Datenbus
KR100318420B1 (ko) 1999-06-28 2001-12-24 박종섭 동기식 반도체 메모리 소자의 파이프 레지스터
DE19963502B4 (de) * 1999-12-28 2008-01-03 Infineon Technologies Ag Schaltungsanordnung für einen integrierten Halbleiterspeicher mit Spaltenzugriff
US10559351B2 (en) 2017-02-20 2020-02-11 Texas Instruments Incorporated Methods and apparatus for reduced area control register circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2712128B2 (ja) * 1988-10-11 1998-02-10 株式会社日立製作所 半導体記憶装置
US5270974A (en) * 1990-09-07 1993-12-14 Alliance Semiconductor Corporation Monolithic fail bit memory
US5199002A (en) * 1990-10-01 1993-03-30 Integrated Device Technology, Inc. SRAM-address-change-detection circuit
US5247644A (en) * 1991-02-06 1993-09-21 Advanced Micro Devices, Inc. Processing system with improved sequential memory accessing
JPH05134973A (ja) * 1991-11-14 1993-06-01 Toshiba Corp データ転送装置
US5291444A (en) * 1991-12-23 1994-03-01 Texas Instruments Incorporated Combination DRAM and SRAM memory array

Also Published As

Publication number Publication date
EP0685851B1 (de) 1999-12-01
JPH0845278A (ja) 1996-02-16
US5521880A (en) 1996-05-28
DE69513568D1 (de) 2000-01-05
EP0685851A1 (de) 1995-12-06

Similar Documents

Publication Publication Date Title
DE69826353D1 (de) Integrierte Schaltung mit Bereitschaftmodussteuerschaltung für Speicher
DE69230516D1 (de) Tragfutteral für elektronische Speicherkarte
DE69620934T2 (de) Schreibschaltung für einen synchronen RAM Speicher
DE69933495D1 (de) Treiberschaltung für einen seriellen Bus
DE69626441T2 (de) Speicherentwurf für IC-Anschlüsse
DE69522326D1 (de) Bitmap-orientierte adressierung für einen flash-speicher
DE69511791D1 (de) Redundanzschema für Speicherschaltungen
DE69624160T2 (de) Verbinderanordnung für integrierte Schaltungskarte
DE59602959D1 (de) An datenbus betreibbarer stapelbarer datenträger
DE69624866D1 (de) Speicherschaltung für Texturmuster
DE69401556D1 (de) Dynamische Redundanzschaltung für integrierten Speicher
DE59709682D1 (de) Schwenkbares dezentrales Eingabe-/Ausgabemodul für einen Datenbus
DE69125876D1 (de) Kennzeichenschaltung für nichtflüchtige Speicheranordnung
FR2665029B1 (fr) Connecteur electrique pour cartes a memoire electronique.
DE69513568T2 (de) Steuerungsschaltung für einen verteilten Datenbus in einer integrierten Speicherschaltung
DE68927661D1 (de) Adressensteuerschaltung für einen Datenspeicher zur Anwendung in einer Signalverzögerungsschaltung
DE69832007D1 (de) Steuerschaltung für Computerspeicher
DE69730306D1 (de) Dateneinschreibschaltung für nichtflüchtigen Halbleiterspeicher
DE69122150D1 (de) Halbleiter-Speichereinrichtung mit verbesserter Kontrollfunktion für Datenbusse
DE69408124D1 (de) Fahrgestell für einen autobus
DE69021704D1 (de) Vorladeschaltung für Speicherbus.
DE69600633D1 (de) Eingangsschaltung für Halbleiterspeicher
GB2291233B (en) Semiconductor memory device with reduced data bus line load
DE59801722D1 (de) Integrierte speicherschaltung mit einer pufferschaltung
DE69413459D1 (de) Speicherschaltung für parallelen Datenausgang

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee