DE69511958T2 - Verfahren zum Herstellen einer Halbleitervorrichtung mit mindestens zwei feldeffekttransitoren verschiedener Abschnürspannung - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung mit mindestens zwei feldeffekttransitoren verschiedener Abschnürspannung

Info

Publication number
DE69511958T2
DE69511958T2 DE69511958T DE69511958T DE69511958T2 DE 69511958 T2 DE69511958 T2 DE 69511958T2 DE 69511958 T DE69511958 T DE 69511958T DE 69511958 T DE69511958 T DE 69511958T DE 69511958 T2 DE69511958 T2 DE 69511958T2
Authority
DE
Germany
Prior art keywords
voltages
producing
semiconductor device
field effect
effect transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69511958T
Other languages
English (en)
Other versions
DE69511958D1 (de
Inventor
Peter Michael Frijlink
Joseph Bellaiche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ommic SAS
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69511958D1 publication Critical patent/DE69511958D1/de
Publication of DE69511958T2 publication Critical patent/DE69511958T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
DE69511958T 1994-06-29 1995-06-15 Verfahren zum Herstellen einer Halbleitervorrichtung mit mindestens zwei feldeffekttransitoren verschiedener Abschnürspannung Expired - Lifetime DE69511958T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9408012 1994-06-29

Publications (2)

Publication Number Publication Date
DE69511958D1 DE69511958D1 (de) 1999-10-14
DE69511958T2 true DE69511958T2 (de) 2000-03-30

Family

ID=9464790

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69511958T Expired - Lifetime DE69511958T2 (de) 1994-06-29 1995-06-15 Verfahren zum Herstellen einer Halbleitervorrichtung mit mindestens zwei feldeffekttransitoren verschiedener Abschnürspannung

Country Status (4)

Country Link
US (1) US5654214A (de)
EP (1) EP0690506B1 (de)
JP (1) JP3986573B2 (de)
DE (1) DE69511958T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232159B1 (en) * 1998-07-22 2001-05-15 Matsushita Electric Industrial Co., Ltd. Method for fabricating compound semiconductor device
JP4631104B2 (ja) * 1999-06-04 2011-02-16 ソニー株式会社 半導体装置の製造方法
EP1198830B1 (de) 2000-02-04 2008-11-05 Ommic Verfahren zur herstellung einer halbleiteranordnung mit einem feldeffekt-transistor mit vergrabenem kanal
US6838325B2 (en) * 2002-10-24 2005-01-04 Raytheon Company Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor
TWI300975B (en) * 2006-06-08 2008-09-11 Nanya Technology Corp Method for fabricating recessed-gate mos transistor device
EP2040299A1 (de) * 2007-09-12 2009-03-25 Forschungsverbund Berlin e.V. Elektronische Bauelemente mit verbesserten Transfercharakteristiken und Methode zur Optimierung der Transfercharakteristiken solcher elektronischen Bauelementen.
US9443737B2 (en) 2013-04-03 2016-09-13 Texas Instruments Incorporated Method of forming metal contacts in the barrier layer of a group III-N HEMT
TWI615977B (zh) * 2013-07-30 2018-02-21 高效電源轉換公司 具有匹配臨界電壓之積體電路及其製造方法
CN108470721B (zh) * 2018-03-19 2021-05-25 Tcl华星光电技术有限公司 阵列基板的制作方法
CN110429063B (zh) * 2019-06-28 2021-12-10 福建省福联集成电路有限公司 一种低噪声值的半导体器件制造方法及器件
CN114121655B (zh) * 2021-11-16 2023-08-25 西安电子科技大学芜湖研究院 一种基于增强型器件的自终止刻蚀方法及器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553460A (en) * 1978-10-16 1980-04-18 Fujitsu Ltd Semiconductor integrated circuit
JPS59130478A (ja) * 1983-01-17 1984-07-27 Nec Corp 電界効果トランジスタの製造方法
JPS59220927A (ja) * 1983-05-31 1984-12-12 Fujitsu Ltd 半導体装置の製造方法
JP2630445B2 (ja) 1988-10-08 1997-07-16 富士通株式会社 半導体装置
JP2830414B2 (ja) * 1990-08-01 1998-12-02 住友電気工業株式会社 Ｍｅｓ構造電極の形成方法
JPH0555268A (ja) * 1991-08-29 1993-03-05 Nec Corp 半導体装置の製造方法
US5508535A (en) * 1992-01-09 1996-04-16 Mitsubishi Denki Kabushiki Kaisha Compound semiconductor devices
US5514605A (en) * 1994-08-24 1996-05-07 Nec Corporation Fabrication process for compound semiconductor device
JPH08111424A (ja) * 1994-10-11 1996-04-30 Mitsubishi Electric Corp 半導体装置の製造方法
US5556797A (en) * 1995-05-30 1996-09-17 Hughes Aircraft Company Method of fabricating a self-aligned double recess gate profile

Also Published As

Publication number Publication date
EP0690506A1 (de) 1996-01-03
EP0690506B1 (de) 1999-09-08
DE69511958D1 (de) 1999-10-14
US5654214A (en) 1997-08-05
JP3986573B2 (ja) 2007-10-03
JPH0864775A (ja) 1996-03-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: PRUEFER & PARTNER GBR, 81479 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: OMMIC SAS, LIMEIL-BREVANNES, FR